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Fri, 16 Oct 2026 09:54:43 -0500 Message-ID: <0ad96f34-97d6-4998-9cf3-4b09ab6c94a2@amd.com> Date: Fri, 16 Oct 2026 09:54:37 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/6] mailbox: Add AMD PL Mailbox soft IP controller To: Krzysztof Kozlowski , Ben Levinsky CC: , , , , , , , , , , , References: <20261014213426.2957480-1-ben.levinsky@amd.com> <20261014213426.2957480-5-ben.levinsky@amd.com> <20261015-aromatic-ibex-of-opposition-dafb43@quoll> Content-Language: en-US From: "Shah, Tanmay" In-Reply-To: <20261015-aromatic-ibex-of-opposition-dafb43@quoll> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PEPF0000000A:EE_|IA0PR12MB8326:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d52b61d-e491-4559-fbeb-08df2b956e8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|23010399003|36860700016|13003099007|11063799006|56012099006|10067099003|261009223027099003|18002099003|22082099003|4143699003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RwxIVHxTf7XIdBwFQ0YVRrCwdXc1SmJYsY8vpzF4L/a6OOCOIN/Bw2kh96r+oNzH6mHFB3Q3t5wDzdLvaBuW4iulhaArNaR1xgAlSZevWwa6FEpC2IqSRNEFoK89w50K54J6YsFWmhnCvgMtW33InrTZiOFscEs7E09rz3wan7L+uGqzH1YcyeCNhLMQOVfjGcpleILk4q99g7Yo3MLE0tKrGmPoDqk9mN55hURsgOC33DzXT1OBqZ7V5THkrjCXmFYa659zqtF7MlB4NRpB0B7EgVJRgzMhF2EsQnQSkOeGjzRdjLNq5nWarcIcyCp07xWFc8I06daYWaxsYfI5jsOCaSlmpOis0fvjuLj2s/iwVo0taKK/ATJYuC8t3QXcpWLh+rOocQ0JxxiWTKZDTPqP3SqqNxlnw8PDQ55dLgZ/wEsD4cYhN/H0s2tA7sH7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Oct 2026 14:54:51.3821 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d52b61d-e491-4559-fbeb-08df2b956e8f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: PH7PEPF0000000A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8326 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261016_075501_655704_FFFB5F86 X-CRM114-Status: GOOD ( 25.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: tanmay.shah@amd.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/15/2026 4:48 AM, Krzysztof Kozlowski wrote: > On Wed, Oct 14, 2026 at 02:34:24PM -0700, Ben Levinsky wrote: >> Add a mailbox-framework controller for the AMD programmable-logic >> Mailbox soft IP. Expose separate transmit and receive FIFO channels. >> >> Enable the interface clock only while a channel is started, before any >> register access, and disable it last when the channel shuts down. Keep >> provider probe free of register accesses and leave the IRQ disabled until >> a client starts the receive channel. Initialize each FIFO when its channel >> starts, use receive-threshold interrupts for incoming words, and poll the >> send-threshold status for transmit completion. Stop that polling from >> accessing registers once the transmit channel begins to shut down. >> >> Carry mailbox payloads in struct zynqmp_ipi_message, limited to the FIFO >> depth given by the device tree. The FIFO transfers 32-bit words and the >> hardware conveys neither a byte count nor the FIFO occupancy, so a >> transmit length that is not a multiple of four is zero-padded to a whole >> word. >> >> On a receive-threshold interrupt, read up to one FIFO depth of words and >> deliver them as one message, then acknowledge the interrupt. The event >> latches only when the FIFO goes from empty to nonempty, so a word that >> arrives between the drain and the acknowledge, or words left by the >> bounded drain, raise no new event. If the FIFO is nonempty after the >> acknowledge, toggle the threshold to latch a new event for them. >> >> Assisted-by: LLM sparse >> Signed-off-by: Ben Levinsky >> --- >> MAINTAINERS | 7 + >> drivers/mailbox/Kconfig | 10 + >> drivers/mailbox/Makefile | 1 + >> drivers/mailbox/amd-pl-mailbox.c | 369 +++++++++++++++++++++++++++++++ >> 4 files changed, 387 insertions(+) >> create mode 100644 drivers/mailbox/amd-pl-mailbox.c >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index f53047aa8d3c..4e28e0c311c0 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -1287,6 +1287,13 @@ S: Supported >> T: git https://gitlab.freedesktop.org/agd5f/linux.git >> F: drivers/gpu/drm/amd/pm/ >> >> +AMD PROGRAMMABLE LOGIC MAILBOX DRIVER >> +M: Ben Levinsky >> +L: linux-kernel@vger.kernel.org >> +S: Maintained >> +F: Documentation/devicetree/bindings/mailbox/amd,zynqmp-pl-mbox-2.1.yaml >> +F: drivers/mailbox/amd-pl-mailbox.c >> + >> AMD PSTATE DRIVER >> M: Huang Rui >> M: Mario Limonciello >> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig >> index ab869769e278..3c3f262c903c 100644 >> --- a/drivers/mailbox/Kconfig >> +++ b/drivers/mailbox/Kconfig >> @@ -8,6 +8,16 @@ menuconfig MAILBOX >> >> if MAILBOX >> >> +config AMD_PL_MAILBOX >> + tristate "AMD PL Mailbox soft IP controller" > > Missing depends on Zynq/Xilinx. > >> + depends on HAS_IOMEM >> + depends on OF >> + help >> + Mailbox controller for the AMD Programmable Logic Mailbox soft IP. >> + The controller exposes transmit and receive FIFO channels to mailbox >> + clients. It supports interrupt-driven receive notification and >> + polling-based transmit completion through the common mailbox framework. > > ... > >> + mb->controller.dev = dev; >> + mb->controller.ops = &amd_pl_mbox_ops; >> + mb->controller.chans = mb->chans; >> + mb->controller.num_chans = AMD_PL_MBOX_NUM_CHANS; >> + mb->controller.txdone_poll = true; >> + mb->controller.txpoll_period = 1; >> + mb->controller.of_xlate = amd_pl_mbox_xlate; >> + >> + ret = devm_request_irq(dev, mb->irq, amd_pl_mbox_irq, >> + IRQF_NO_AUTOEN, >> + dev_name(dev), mb); >> + if (ret) >> + return ret; >> + >> + return devm_mbox_controller_register(dev, &mb->controller); >> +} >> + >> +static const struct of_device_id amd_pl_mbox_of_match[] = { >> + { .compatible = "amd,zynqmp-pl-mbox-2.1" }, >> + { .compatible = "amd,versal-pl-mbox-2.1" }, >> + { .compatible = "amd,versal-net-pl-mbox-2.1" }, >> + { .compatible = "amd,versal2-pl-mbox-2.1" }, > > So all of them are compatible? Then why do you need all this? > Hi Krzysztof, This block will be used on 4 SoC - zynqmp, versal, versal-net & versal2. IIRC we should list each SoC where the device/hw block is available. That is why we listed all 4 of them. I am not sure if the compatible property in the YAML is presenting this correctly, but here I think it is good. Please suggest if there is a better way. Thank You. > Best regards, > Krzysztof