From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F074C43387 for ; Fri, 18 Jan 2019 16:57:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 58BBC2086D for ; Fri, 18 Jan 2019 16:57:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="eExKVuUx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 58BBC2086D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Xrp6I7DzwluM1xpR+Zi+FZSTrmQMO/t1QOjTvtQrDHk=; b=eExKVuUxQ6RXnT u2T9nidWu5e4lJV6mC/njResSiB4fuFREBdyC3W28PPfcPSnurPW+YGCR02KjhJpzLQD6PMA1mYr5 5PhULfM6sfTv7cdOMH1vY6Ihyhg+WewcPm6E7cnom55yI+/WTbuG81SYroVRIpXtdSdJJc8CedZQx wYABABLdHwPHQgNQf3YsQ+WwAP8Z1+DBH94O2kA4SduZSKwBkYEJGfjBzlz9RLPL/QHOHVGJujWLO NAPaNOIisQAo2gEV6zP+3UvtZhoviFuW7U9zDbHLgl9V+qZCFohOWR2ZZTrKWhoFTRkEwRyp37pFO SoUT/vTbKBzsSw7xgK1w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gkXSn-0005wN-0u; Fri, 18 Jan 2019 16:57:49 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gkXSc-0005jm-5J for linux-arm-kernel@lists.infradead.org; Fri, 18 Jan 2019 16:57:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D947180D; Fri, 18 Jan 2019 08:57:35 -0800 (PST) Received: from [10.1.197.45] (e112298-lin.cambridge.arm.com [10.1.197.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E684A3F7BE; Fri, 18 Jan 2019 08:57:33 -0800 (PST) Subject: Re: [PATCH v8 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking To: Catalin Marinas References: <1546956464-48825-1-git-send-email-julien.thierry@arm.com> <1546956464-48825-13-git-send-email-julien.thierry@arm.com> <20190118160920.GF118707@arrakis.emea.arm.com> From: Julien Thierry Message-ID: <0af2d75e-9a61-e53b-b2df-3d08d3f63d9c@arm.com> Date: Fri, 18 Jan 2019 16:57:32 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20190118160920.GF118707@arrakis.emea.arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190118_085738_648846_DB264655 X-CRM114-Status: GOOD ( 21.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, Ard Biesheuvel , marc.zyngier@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, Oleg Nesterov , joel@joelfernandes.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Catalin, On 18/01/2019 16:09, Catalin Marinas wrote: > Hi Julien, > > On Tue, Jan 08, 2019 at 02:07:30PM +0000, Julien Thierry wrote: >> + * Having two ways to control interrupt status is a bit complicated. Some >> + * locations like exception entries will have PSR.I bit set by the architecture >> + * while PMR is unmasked. >> + * We need the irqflags to represent that interrupts are disabled in such cases. >> + * >> + * For this, we lower the value read from PMR when the I bit is set so it is >> + * considered as an irq masking priority. (With PMR, lower value means masking >> + * more interrupts). >> + */ >> +#define _get_irqflags(daif_bits, pmr) \ >> +({ \ >> + unsigned long flags; \ >> + \ >> + BUILD_BUG_ON(GIC_PRIO_IRQOFF < (GIC_PRIO_IRQON & ~PSR_I_BIT)); \ >> + asm volatile(ALTERNATIVE( \ >> + "mov %0, %1\n" \ >> + "nop\n" \ >> + "nop", \ >> + "and %0, %1, #" __stringify(PSR_I_BIT) "\n" \ >> + "mvn %0, %0\n" \ >> + "and %0, %0, %2", \ >> + ARM64_HAS_IRQ_PRIO_MASKING) \ > > Can you write the last two instructions as a single: > > bic %0, %2, %0 Yes, makes sense. Although we won't need it anymore with your suggestion below. > >> + : "=&r" (flags) \ >> + : "r" (daif_bits), "r" (pmr) \ >> + : "memory"); \ >> + \ >> + flags; \ >> +}) >> + >> +/* >> * Save the current interrupt enable state. >> */ >> static inline unsigned long arch_local_save_flags(void) >> { >> - unsigned long flags; >> - asm volatile( >> - "mrs %0, daif // arch_local_save_flags" >> - : "=r" (flags) >> + unsigned long daif_bits; >> + unsigned long pmr; // Only used if alternative is on >> + >> + daif_bits = read_sysreg(daif); >> + >> + // Get PMR > > Nitpick: don't use C++ (or arm asm) comment style in C code. Noted. > >> + asm volatile(ALTERNATIVE( >> + "nop", >> + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1), >> + ARM64_HAS_IRQ_PRIO_MASKING) >> + : "=&r" (pmr) >> : >> : "memory"); >> + >> + return _get_irqflags(daif_bits, pmr); >> +} > > I find this confusing spread over two inline asm statements. IIUC, you > want something like below (it could be written as inline asm but I need > to understand it first): > > daif_bits = read_sysreg(daif); > > if (system_uses_irq_prio_masking()) { > pmr = read_gicreg(ICC_PMR_EL1); > flags = pmr & ~(daif_bits & PSR_I_BIT); > } else { > flags = daif_bits; > } > > return flags; > > In the case where the interrupts are disabled at the PSR level, is the > PMR value still relevant? Could we just return the GIC_PRIO_IRQOFF? > Something like: > > flags = read_sysreg(daif); > > if (system_uses_irq_prio_masking()) > flags = flags & PSR_I_BIT ? > GIC_PRIO_IRQOFF : read_gicreg(ICC_PMR_EL1); > You're right, returning GIC_PRIO_IRQOFF should be good enough (it is actually what happens in this version because GIC_PRIO_IRQOFF == GIC_PRIO_IRQON & ~PSR_I_BIT happens to be true). Your suggestion would make things easier to reason about. Maybe something like: static inline unsigned long arch_local_save_flags(void) { unsigned long daif_bits; unsigned long prio_off = GIC_PRIO_IRQOFF; daif_bits = read_sysreg(daif); asm volatile(ALTERNATIVE( "mov %0, %1\n" "nop\n" "nop", "mrs %0, SYS_ICC_PMR_EL1\n" "ands %1, %1, PSR_I_BIT\n" "csel %0, %0, %2, eq") : "=&r" (flags) : "r" (daif_bits), "r" (prio_off) : "memory"); return flags; } (Looks like it removes one nop from the alternative as well, unless I messed up something) Does that seem better to you? Thanks, -- Julien Thierry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel