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Mon, 01 Jun 2020 17:13:01 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 213FFC4339C; Mon, 1 Jun 2020 17:13:01 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 71EA2C433C6; Mon, 1 Jun 2020 17:13:00 +0000 (UTC) MIME-Version: 1.0 Date: Mon, 01 Jun 2020 22:43:00 +0530 From: Sai Prakash Ranjan To: Mike Leach Subject: Re: [PATCH 1/2] coresight: tmc: Add enable flag to indicate the status of ETR/ETF In-Reply-To: References: <6e62147c36c76b9485d14960dced4f6acda17591.1590947174.git.saiprakash.ranjan@codeaurora.org> Message-ID: <0b1ce383d9df84af3c23efad7eae21ae@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200601_101316_873330_F112E77F X-CRM114-Status: GOOD ( 15.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mathieu Poirier , Suzuki K Poulose , linux-arm-msm@vger.kernel.org, Coresight ML , Linux Kernel Mailing List , Stephen Boyd , linux-arm-kernel Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mike, Thanks for the review. On 2020-06-01 18:57, Mike Leach wrote: > Hi, > > On Mon, 1 Jun 2020 at 09:02, Sai Prakash Ranjan > wrote: >> >> Add a flag to check whether TMC ETR/ETF is enabled or not. >> This is later used in shutdown callback to determine if >> we require to disable ETR/ETF. >> >> Signed-off-by: Sai Prakash Ranjan >> --- >> drivers/hwtracing/coresight/coresight-tmc.c | 2 ++ >> drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ >> 2 files changed, 4 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc.c >> b/drivers/hwtracing/coresight/coresight-tmc.c >> index 39fba1d16e6e..5a271ebc4585 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc.c >> +++ b/drivers/hwtracing/coresight/coresight-tmc.c >> @@ -62,11 +62,13 @@ void tmc_flush_and_stop(struct tmc_drvdata >> *drvdata) >> >> void tmc_enable_hw(struct tmc_drvdata *drvdata) >> { >> + drvdata->enable = true; >> writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); >> } >> >> void tmc_disable_hw(struct tmc_drvdata *drvdata) >> { >> + drvdata->enable = false; >> writel_relaxed(0x0, drvdata->base + TMC_CTL); >> } >> >> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h >> b/drivers/hwtracing/coresight/coresight-tmc.h >> index 71de978575f3..d156860495c7 100644 >> --- a/drivers/hwtracing/coresight/coresight-tmc.h >> +++ b/drivers/hwtracing/coresight/coresight-tmc.h >> @@ -184,6 +184,7 @@ struct etr_buf { >> * @idr_mutex: Access serialisation for idr. >> * @sysfs_buf: SYSFS buffer for ETR. >> * @perf_buf: PERF buffer for ETR. >> + * @enable: Indicates whether ETR/ETF is enabled. >> */ >> struct tmc_drvdata { >> void __iomem *base; >> @@ -207,6 +208,7 @@ struct tmc_drvdata { >> struct mutex idr_mutex; >> struct etr_buf *sysfs_buf; >> struct etr_buf *perf_buf; >> + bool enable; > > Is this flag needed? > For TMC, drvdata->mode indicates if the device is in use. > Yes we can use mode flag, will make this change in the next version. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel