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Mon, 31 Aug 2026 17:34:12 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v3 08/13] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Date: Mon, 31 Aug 2026 17:33:33 -0700 Message-ID: <0b5282c7e850f1a1c650e43670899b4ef5335efd.1788222486.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD83:EE_|MW4PR12MB6950:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e1969de-05f1-4326-3c21-08df07c0ce1c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|1800799024|23010399003|82310400026|6133799003|10067099003|56012099006|11063799006|5023799004|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: Z46EkOmiWSs7v+6BEGFIS4Ily3WepxC4o5o5syLa5WyYyajAk50u0fXg9Zv2x5WjhMecgIb5CHiYStaZsnBcA2dbEhPOIMQKxKIHgvQQTHzMo413pjujZXDyyoCv0YS15vFM3Lot//i3cv7QdwRkvQ9cqX1GN3w+6/6fBhgjjOyUJ4BX9Py23vzvod60xJRBXeNuobRbJIfEEclq5eebjXCv/dZJUZc8kfSZxENvGTzuFz5gBhdPpXA7kpn7LmtwnR5Z0gwXrgPh+VRxIgFAd7hOIiaoocqeEtKKhMdSBgv3ipWoZpN5tz83l8dXYv3teBlMbEKfyWknhYroKA745TRIL4d7h4rO++r/hbVmXlo5C7WvFrsx8MbPMRQn+rHWLUPSHlhZdjDqzqyp4B+gRnXuNma/aPaQ6oSFxN+cethLRT/K2uqVEpDk+L0ytH3Nw8TFhW88R+kmECG19IJcbg2sScx4a8xRfcVPabLXbWmYiW20cQGCSBAbH7VD90fAR25Fi4lTDRbRBFKfCyx0mBnUA6tRrF75lvWXr6YiF0JdqAA+5QpfHhXAH8r44y1QAd7AV8ipVyP4kjlP2VYfEvpVaF5CQVJUI2fWEZ5n0pY2pYg3nMCJma9j3N7hibbWNgk5jLpuQhZMQM+7Wb5hvRGrk1pvbbta16yqZP3tCNAwcKy7fbqm5TdTo1dM2RZGoIc89QC+VkKSlVzqFz6Heg== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(1800799024)(23010399003)(82310400026)(6133799003)(10067099003)(56012099006)(11063799006)(5023799004)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YDhmuck7pbZJUoQDlHg73Y85PNGwl9kyQSiBrTqE3+YETAS/z9UC8iCYXZkwBliBZmO5PGSgOOKmForDSd6QfX2AZIlqdMd4PZttosdh5NxbnRDt98miZ9TPl3rJte9Afwmq7Sfjc7AE2j2klUFUyK6eE9I2St9LY+hVpCILf5zyL08MMPeA37rr1YWAMb04Lr4SFXajyRG8KMKvuKv7qrfzVKLQUPmJNJkxlj7bxVk31nue5/ito4PmElA/IKY3TlLNTA9ulcgvhZQyGumd4nxLrwOy8D0maKWe2+/KEpmAPVLE9xS0RPFXJvw/NZuLrSZCm3FrlbhV2IeKOEZjUv8SmmxkXskMTt/qsPPmPsykGSRIILPrEOz2nEXGVMaZZ0hxaeUoVixh//pkWHanaz2jeETFzZM/9aGEF7+HbXpKZlcX6GM2ZUb6iYHW7BPj X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2026 00:34:38.1428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e1969de-05f1-4326-3c21-08df07c0ce1c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD83.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6950 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_173449_893089_D7388B42 X-CRM114-Status: GOOD ( 14.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org arm_smmu_setup_irqs() has three failure paths that leave the priq without a handler: a missing priq IRQ line, devm_request_threaded_irq() failure on the priq IRQ, and devm_request_threaded_irq() failure on the combined IRQ. Each path warned but kept ARM_SMMU_FEAT_PRI set in smmu->features. With FEAT_PRI still set, arm_smmu_setup_irqs() enables IRQ_CTRL_PRIQ_IRQEN against a handler that does not exist, and a later change would then have arm_smmu_probe_device() call pci_enable_pri() on PCIe endpoints, allowing them to issue PRI Page Requests that pile up in the priq with no drainer. Separately, arm_smmu_device_reset() has already enabled CR0_PRIQEN before it invoked arm_smmu_setup_irqs(), so the hardware queue would stay enabled regardless of what setup_irqs decides. Clear ARM_SMMU_FEAT_PRI in all three failure paths, so that subsequent code treats PRI as unavailable. And disable CR0_PRIQEN after the setup function returns. A kdump kernel cannot service page requests: strip FEAT_PRI when detecting features, so downstream PRI setup is skipped. Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d45d97f356cf0..60f21591de9e8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4937,9 +4937,11 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) dev_warn(smmu->dev, "failed to enable priq irq\n"); smmu->priq.q.irq = 0; + smmu->features &= ~ARM_SMMU_FEAT_PRI; } } else { dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); + smmu->features &= ~ARM_SMMU_FEAT_PRI; } } else { /* An unrequested IRQ (e.g. set by DT) must not be disabled */ @@ -4974,6 +4976,7 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) if (ret < 0) { dev_warn(smmu->dev, "failed to enable combined irq\n"); smmu->combined_irq = 0; + smmu->features &= ~ARM_SMMU_FEAT_PRI; } } else arm_smmu_setup_unique_irqs(smmu); @@ -5154,6 +5157,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } + /* arm_smmu_setup_irqs() might have unset the ARM_SMMU_FEAT_PRI */ + if (!(smmu->features & ARM_SMMU_FEAT_PRI)) + enables &= ~CR0_PRIQEN; + if (is_kdump_kernel()) enables &= ~(CR0_EVTQEN | CR0_PRIQEN); @@ -5295,7 +5302,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) } /* Boolean feature flags */ - if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) + if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI && !is_kdump_kernel()) smmu->features |= ARM_SMMU_FEAT_PRI; if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) -- 2.43.0