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[89.27.92.210]) by smtp.gmail.com with ESMTPSA id g6-20020a2ea4a6000000b0025e5631194dsm2240520ljm.21.2022.08.23.01.12.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Aug 2022 01:12:29 -0700 (PDT) Message-ID: <0bda4ff9-fc08-77f2-0e06-7469dcaec6d8@linaro.org> Date: Tue, 23 Aug 2022 11:12:28 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support Content-Language: en-US To: Serge Semin , Michal Simek , Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , Krzysztof Kozlowski , Rob Herring , Manish Narani Cc: Serge Semin , Alexey Malahov , Michail Ivanov , Pavel Parkhomenko , Punnaiah Choudary Kalluri , Dinh Nguyen , James Morse , Robert Richter , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220822191957.28546-1-Sergey.Semin@baikalelectronics.ru> <20220822191957.28546-3-Sergey.Semin@baikalelectronics.ru> From: Krzysztof Kozlowski In-Reply-To: <20220822191957.28546-3-Sergey.Semin@baikalelectronics.ru> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220823_011234_632506_F67EDB0D X-CRM114-Status: GOOD ( 17.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22/08/2022 22:19, Serge Semin wrote: > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > are individual IRQs for each ECC and DFI events.The dedicated scrubber Missing space before "The". > clock source is absent since it's fully synchronous to the core clock. You need allOf:if-then restricting this per variant. > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > registers space. > > Signed-off-by: Serge Semin > --- > .../memory-controllers/snps,dw-umctl2-ddrc.yaml | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml > index 8db92210cfe1..899a6c5f9806 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml > +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml > @@ -26,6 +26,7 @@ properties: > enum: > - snps,ddrc-3.80a > - xlnx,zynqmp-ddrc-2.40a > + - baikal,bt1-ddrc Messed order. Don't add stuff at the end, but in alphabetical order. > > interrupts: > description: > @@ -49,7 +50,14 @@ properties: > enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] > > reg: > - maxItems: 1 > + minItems: 1 > + maxItems: 2 > + > + reg-names: > + minItems: 1 > + items: > + - const: umctl2 > + - const: phy You need allOf:if-then restricting this per variant. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel