[PATCH 0/2] Add HDMI support for Exynos5420 platform

[PATCH 0/2] Add HDMI support for Exynos5420 platform

[Javier Martinez Canillas]

Hello,

This series adds HDMI support for Exynos5420/5422/5800 machines by adding a
node for the DISP1 power domain which is used by the HDMI and MIXER modules.

It also adds IDs for the attached devices parent and input clocks that are
used by the Exynos power domain driver to re-parent the devices input clocks
when the DISP1 power domain is powered off and on.

Thanks a lot to Joonyoung Shim and Krzysztof Kozlowski for point me in the
right direction.

The series is based on Marek Szyprowski's patch
'ARM: DTS: Exynos: convert to generic power domain bindings'
(http://www.spinics.net/lists/linux-samsung-soc/msg40584.html)

The patches were tested on an Exynos5420 Peach Pit and Exynos5800 Peach Pi
Chromebooks and an Exynos5422 Odroid XU3.

NOTE: There is an issue noticed with these patches and is that if the kconfig
CONFIG_DRM_EXYNOS_DP symbol is disabled and only CONFIG_DRM_EXYNOS_HDMI is
enabled, then disabling the framebuffer and enabling it again with:

# echo 0 > /sys/devices/platform/exynos-drm/graphics/fb0/blank                                                           
# echo 1 > /sys/devices/platform/exynos-drm/graphics/fb0/blank

makes the system to crash due the exynos_mixer driver needing clocks enabled
by the exynos_hdmi driver that are gated on hdmi_poweroff().

The same issue has been reported on other Exynos platforms so it's orthogonal
to this series and needs to be fixed for all platforms.

Javier Martinez Canillas (2):
  clk: exynos5420: Add IDs for clocks used in DISP1 power domain
  ARM: dts: Add DISP1 power domain for exynos5420

 arch/arm/boot/dts/exynos5420.dtsi      | 17 +++++++++++++++++
 drivers/clk/samsung/clk-exynos5420.c   | 23 ++++++++++++-----------
 include/dt-bindings/clock/exynos5420.h |  6 ++++++
 3 files changed, 35 insertions(+), 11 deletions(-)

Patches 1 and 2 depend on each other so they have to either be merged through
the same tree or patch 1 has to be merged through clock tree and create a topic
branch to be pulled by the linux-samsung tree.

Best regards,
Javier

[PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

[Javier Martinez Canillas]

When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.

So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:

ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)

Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
---
 drivers/clk/samsung/clk-exynos5420.c   | 23 ++++++++++++-----------
 include/dt-bindings/clock/exynos5420.h |  6 ++++++
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 848d602efc06..07d666cc6a29 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 			SRC_TOP3, 0, 1),
 	MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
 			SRC_TOP3, 4, 1),
-	MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
-			SRC_TOP3, 8, 1),
+	MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
+			mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
 	MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
 			SRC_TOP3, 12, 1),
 	MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
@@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
 			SRC_TOP4, 28, 1),
 
-	MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
-			SRC_TOP5, 0, 1),
+	MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
+			mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
 	MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
 			SRC_TOP5, 4, 1),
 	MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
@@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 			SRC_TOP5, 16, 1),
 	MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
 			SRC_TOP5, 20, 1),
-	MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
-			SRC_TOP5, 24, 1),
+	MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
+			mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
 	MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
 			SRC_TOP5, 28, 1),
 
@@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 			SRC_TOP10, 0, 1),
 	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
 			SRC_TOP10, 4, 1),
-	MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
+	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
+			SRC_TOP10, 8, 1),
 	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
 			SRC_TOP10, 12, 1),
 	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
@@ -717,8 +718,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
 			SRC_TOP11, 28, 1),
 
-	MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
-			SRC_TOP12, 4, 1),
+	MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
+			mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
 	MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
 			SRC_TOP12, 8, 1),
 	MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
@@ -726,8 +727,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
 	MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
 	MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
 			SRC_TOP12, 20, 1),
-	MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
-			SRC_TOP12, 24, 1),
+	MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
+			mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
 	MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
 			SRC_TOP12, 28, 1),
 
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 8dc0913f1775..99da0d117a7d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -204,6 +204,12 @@
 #define CLK_MOUT_MAUDIO0	643
 #define CLK_MOUT_USER_ACLK333	644
 #define CLK_MOUT_SW_ACLK333	645
+#define CLK_MOUT_USER_ACLK200_DISP1	646
+#define CLK_MOUT_SW_ACLK200	647
+#define CLK_MOUT_USER_ACLK300_DISP1     648
+#define CLK_MOUT_SW_ACLK300     649
+#define CLK_MOUT_USER_ACLK400_DISP1     650
+#define CLK_MOUT_SW_ACLK400     651
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
-- 
2.1.3

[PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

[Sylwester Nawrocki]

Hi,

On 20/01/15 11:35, Javier Martinez Canillas wrote:
> When a power domain is powered off on Exynos5420 SoC, the input clocks of
> the devices attached to this power domain are re-parented to oscclk and
> restored to the original parent after powering on the power domain.
> 
> So a reference to the input and parent clocks for the devices attached to
> a power domain are needed to be able to do the re-parenting. The DISP1 pd
> includes modules which uses the following clocks:
> 
> ACLK_200_DISP1 (MIXER and HDMILINK)
> ACLK_300_DISP1 (FIMD1)
> ACLK_400_DISP1 (Internal Buses)
> 
> Each of these clocks are generated as the output of a clock mux so add an
> ID for all of these clock muxes and their parents to be referenced in the
> DISP1 power domain device node.
> 
> Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

The patch looks OK to me, I'm fine with it being merged via Kukjin's tree
due to the dts dependencies (including other pending dts patches touching
the arch/arm/boot/dts/exynos5420.dtsi file).
I think we need also Mike ACK for that, I could also queue the patch for
the clk tree and create a topic branch, but merging both patches via
arm-soc seems a more sane option in this case.

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

--
Thanks,
Sylwester

[PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

[Mike Turquette]

Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
> Hi,
> 
> On 20/01/15 11:35, Javier Martinez Canillas wrote:
> > When a power domain is powered off on Exynos5420 SoC, the input clocks of
> > the devices attached to this power domain are re-parented to oscclk and
> > restored to the original parent after powering on the power domain.
> > 
> > So a reference to the input and parent clocks for the devices attached to
> > a power domain are needed to be able to do the re-parenting. The DISP1 pd
> > includes modules which uses the following clocks:
> > 
> > ACLK_200_DISP1 (MIXER and HDMILINK)
> > ACLK_300_DISP1 (FIMD1)
> > ACLK_400_DISP1 (Internal Buses)
> > 
> > Each of these clocks are generated as the output of a clock mux so add an
> > ID for all of these clock muxes and their parents to be referenced in the
> > DISP1 power domain device node.
> > 
> > Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> 
> The patch looks OK to me, I'm fine with it being merged via Kukjin's tree
> due to the dts dependencies (including other pending dts patches touching
> the arch/arm/boot/dts/exynos5420.dtsi file).
> I think we need also Mike ACK for that, I could also queue the patch for
> the clk tree and create a topic branch, but merging both patches via
> arm-soc seems a more sane option in this case.
> 
> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

Acked-by: Michael Turquette <mturquette@linaro.org>

> 
> --
> Thanks,
> Sylwester
> 

[PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

[Javier Martinez Canillas]

Hello,

On 01/20/2015 06:54 PM, Mike Turquette wrote:
> Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
>> Hi,
>> 
>> On 20/01/15 11:35, Javier Martinez Canillas wrote:
>> > When a power domain is powered off on Exynos5420 SoC, the input clocks of
>> > the devices attached to this power domain are re-parented to oscclk and
>> > restored to the original parent after powering on the power domain.
>> > 
>> > So a reference to the input and parent clocks for the devices attached to
>> > a power domain are needed to be able to do the re-parenting. The DISP1 pd
>> > includes modules which uses the following clocks:
>> > 
>> > ACLK_200_DISP1 (MIXER and HDMILINK)
>> > ACLK_300_DISP1 (FIMD1)
>> > ACLK_400_DISP1 (Internal Buses)
>> > 
>> > Each of these clocks are generated as the output of a clock mux so add an
>> > ID for all of these clock muxes and their parents to be referenced in the
>> > DISP1 power domain device node.
>> > 
>> > Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>> 
>> The patch looks OK to me, I'm fine with it being merged via Kukjin's tree
>> due to the dts dependencies (including other pending dts patches touching
>> the arch/arm/boot/dts/exynos5420.dtsi file).
>> I think we need also Mike ACK for that, I could also queue the patch for
>> the clk tree and create a topic branch, but merging both patches via
>> arm-soc seems a more sane option in this case.
>> 
>> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> 
> Acked-by: Michael Turquette <mturquette@linaro.org>
> 

Thanks a lot Sylwester and Mike for your acks.

Kukjin, could you please pick $subject and "Patch 2/2 ARM: dts: Add DISP1
power domain for exynos5420" through your tree?

Best regards,
Javier

[PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

[Kukjin Kim]

Javier Martinez Canillas wrote:
> 
> Hello,
> 
Hi,

> On 01/20/2015 06:54 PM, Mike Turquette wrote:
> > Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
> >> Hi,
> >>
> >> On 20/01/15 11:35, Javier Martinez Canillas wrote:
> >> > When a power domain is powered off on Exynos5420 SoC, the input clocks of
> >> > the devices attached to this power domain are re-parented to oscclk and
> >> > restored to the original parent after powering on the power domain.
> >> >
> >> > So a reference to the input and parent clocks for the devices attached to
> >> > a power domain are needed to be able to do the re-parenting. The DISP1 pd
> >> > includes modules which uses the following clocks:
> >> >
> >> > ACLK_200_DISP1 (MIXER and HDMILINK)
> >> > ACLK_300_DISP1 (FIMD1)
> >> > ACLK_400_DISP1 (Internal Buses)
> >> >
> >> > Each of these clocks are generated as the output of a clock mux so add an
> >> > ID for all of these clock muxes and their parents to be referenced in the
> >> > DISP1 power domain device node.
> >> >
> >> > Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
> >>
> >> The patch looks OK to me, I'm fine with it being merged via Kukjin's tree
> >> due to the dts dependencies (including other pending dts patches touching
> >> the arch/arm/boot/dts/exynos5420.dtsi file).
> >> I think we need also Mike ACK for that, I could also queue the patch for
> >> the clk tree and create a topic branch, but merging both patches via
> >> arm-soc seems a more sane option in this case.
> >>
> >> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> >
> > Acked-by: Michael Turquette <mturquette@linaro.org>
> >
> 
> Thanks a lot Sylwester and Mike for your acks.
> 
> Kukjin, could you please pick $subject and "Patch 2/2 ARM: dts: Add DISP1
> power domain for exynos5420" through your tree?
> 
Sure, I will after applying Marek's generic power domain patch.

Thanks,
Kukjin

[PATCH 1/2] clk: exynos5420: Add IDs for clocks used in DISP1 power domain

[Javier Martinez Canillas]

Hello Kukjin,

On 01/23/2015 07:51 AM, Kukjin Kim wrote:
>> >>
>> >> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> >
>> > Acked-by: Michael Turquette <mturquette@linaro.org>
>> >
>> 
>> Thanks a lot Sylwester and Mike for your acks.
>> 
>> Kukjin, could you please pick $subject and "Patch 2/2 ARM: dts: Add DISP1
>> power domain for exynos5420" through your tree?
>> 
> Sure, I will after applying Marek's generic power domain patch.
>

Awesome, thanks a lot for your help!
 
> Thanks,
> Kukjin
> 

Best regards,
Javier

[PATCH 2/2] ARM: dts: Add DISP1 power domain for exynos5420

[Javier Martinez Canillas]

The DISP1 power domain on Exynos5420 SoC includes the FIMD1, MIXER
and HDMI modules. Add a device node for this power domain and mark
these modules as consumer of the DISP1 power domain.

When a power domain is powered on and off, the input clocks of the
devices attached to it are reparented. So a reference to the input
and parent clocks of the devices are needed to manage that.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
---
 arch/arm/boot/dts/exynos5420.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e5cb74d2b9f5..9dc2e9773b30 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -274,6 +274,20 @@
 		#power-domain-cells = <0>;
 	};
 
+	disp_pd: power-domain at 100440C0 {
+		compatible = "samsung,exynos4210-pd";
+		reg = <0x100440C0 0x20>;
+		#power-domain-cells = <0>;
+		clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
+			 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
+			 <&clock CLK_MOUT_SW_ACLK300>,
+			 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
+			 <&clock CLK_MOUT_SW_ACLK400>,
+			 <&clock CLK_MOUT_USER_ACLK400_DISP1>;
+		clock-names = "oscclk", "pclk0", "clk0",
+			      "pclk1", "clk1", "pclk2", "clk2";
+	};
+
 	pinctrl_0: pinctrl at 13400000 {
 		compatible = "samsung,exynos5420-pinctrl";
 		reg = <0x13400000 0x1000>;
@@ -541,6 +555,7 @@
 	fimd: fimd at 14400000 {
 		clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
 		clock-names = "sclk_fimd", "fimd";
+		power-domains = <&disp_pd>;
 	};
 
 	adc: adc at 12D10000 {
@@ -714,6 +729,7 @@
 		phy = <&hdmiphy>;
 		samsung,syscon-phandle = <&pmu_system_controller>;
 		status = "disabled";
+		power-domains = <&disp_pd>;
 	};
 
 	hdmiphy: hdmiphy at 145D0000 {
@@ -726,6 +742,7 @@
 		interrupts = <0 94 0>;
 		clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
 		clock-names = "mixer", "sclk_hdmi";
+		power-domains = <&disp_pd>;
 	};
 
 	gsc_0: video-scaler at 13e00000 {
-- 
2.1.3