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Tue, 15 Sep 2026 09:38:42 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v5 08/15] iommu/arm-smmu-v3: Disable the queue IRQs before disabling the SMMU Date: Tue, 15 Sep 2026 09:38:20 -0700 Message-ID: <0ca69e93a9370e4e172e4335104859648b8755c2.1789446520.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00018074:EE_|DS7PR12MB6190:EE_ X-MS-Office365-Filtering-Correlation-Id: cda51bcf-5cf0-4eef-b16a-08df1347df2c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700016|23010399003|18002099003|22082099003|3023799007|10067099003|56012099006|5023799004|11063799006; X-Microsoft-Antispam-Message-Info: aqXsvX3jPhkqUO40LK3P+iIIks91ag/j4ic/VNY/limc/U75SgHi9st06+o2VHXlM8yJURzNm7YFN5V+jF1iKcpGZncQehV67PkeUVgl7q7ko/NDscnxceo7aUktXyl6hMfHJ1ihc7sbqk2dVq/b6nR3Rw6+6pTDtNeyMRv5eeLKqsYxUmmtry4sIMhyFrPalqLthCYKW2mxLFJ8X8wKB2xsrgcMF7V78Ehr3UziSULKZFTf9DussyQ0ZJIzkrMA8E5rhnA1TrozTkV+kkizChisQ+b5b6a/QxUnv8gDNo9P3cFG0se+oLqE2x3eDRCii7F4OYa0i/QNJFdA1yrWltTO23Kv6LXLVjnrDPAqaVbbDUQWZLz90P2+LGTJB3FZESyKHMiQsIlk+qfxbXvMgQ/MDlJAgTduKYKW51Dho76qTf6WxzwI0hxL4ZbH7oAckyloRaeCJ3cICOniI31Sh4PnJWivsLab6nmGkFmePtaSS0JVKBrRF3QNE4np5GmT8i4MCHN7iKjZpxU1YbVvkkQ656Q2eF+wYSNAH7nGzwHk+Zyg3sT9cqES1iDRCcDnOBdxmVOJZU9kh2nQyvoBc1DLPuAsqdDaIoIJ3FL0tza7ieJg45kmBWMSmeix21uu+iR6UZuavuI9C5/XFD+DcbxuaQB+ylDKK9wEtMSmGjT3IZfrhAXCjl8Opj8CpeWwfsiC0bzJPCsRmfZ9rZaK/Q== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700016)(23010399003)(18002099003)(22082099003)(3023799007)(10067099003)(56012099006)(5023799004)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YXNos66D5pxDaxyVfiGbrmgcGhMOQLCcK21nT+0zCCUTyqw5L48xzo0xK39TC4PFzsdzX+4RylAX/+muZHF7iqnH/jrHpCRQ99McOrCWKpMgbWFLv6QeIQ90KvhGLU8DfsztAWYqD9qlv6radNaxYCM0BI8ZTuhbJceQPOs+h/pfhXBSS5zHCbodO7wambuZ75/nx0eAXZfJGHo/aZzHJIEaClHHpdIztKlmY5xu32NO5felrqkHDe74MXyvmg1zPWvLZy0DJwCJGrsKuGwytoJ2DzHEhuZVy7PFQdruWbjcvXvy/vNlpiW8E7w5Gv4fN4Fgq7vJJz9/l/Le+YgBGvgpWGx5kOTiwqrus/m9tqbHq7ktAK/sT7a5yS41QXuFQ039cqAUiHzE01hW+vQjHiYtcbNlAoTXTooxmYPEXLmO0l6sW4tRu7hvgsctwyIZ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2026 16:39:11.5729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cda51bcf-5cf0-4eef-b16a-08df1347df2c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00018074.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6190 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260915_093924_325235_BA6FEA9C X-CRM114-Status: GOOD ( 16.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The EVTQ, PRIQ and combined IRQ handlers are threaded and issue commands of their own, e.g. a CMDQ_OP_PRI_RESP for a page request. Disabling the SMMU while one is in flight hands that command to a queue consuming nothing, so its poll waits out a full timeout. Two paths disable the SMMU while those IRQs are still requested: a failing arm_smmu_device_reset() returns to a probe that disables the device itself, and arm_smmu_disable_action() covers an unbind or any later probe failure. Both can run after arm_smmu_setup_irqs() requested the IRQs. Disable those IRQs first in both paths, so that no handler is left running once the SMMU goes down. arm_smmu_device_shutdown() needs no change of its own here, since it already just calls arm_smmu_disable_action(). Also clear an IRQ number when its request fails or is skipped for a missing ARM_SMMU_FEAT_PRI, keeping disable_irq() to the IRQs that this driver truly owns. Note that the IOPF queue needs no such care of its own, as devres frees the IRQs before running the release action of that queue, which came earlier in arm_smmu_init_queues(). Assisted-by: LLM Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 36 ++++++++++++++++++--- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 9ebf3123e19d7..d2a6dc756c783 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4914,8 +4914,10 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) arm_smmu_evtq_thread, IRQF_ONESHOT, "arm-smmu-v3-evtq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable evtq irq\n"); + smmu->evtq.q.irq = 0; + } } else { dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); } @@ -4938,12 +4940,17 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) IRQF_ONESHOT, "arm-smmu-v3-priq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable priq irq\n"); + smmu->priq.q.irq = 0; + } } else { dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); } + } else { + /* An unrequested IRQ (e.g. set by DT) must not be disabled */ + smmu->priq.q.irq = 0; } } @@ -4971,8 +4978,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) arm_smmu_combined_irq_thread, IRQF_ONESHOT, "arm-smmu-v3-combined-irq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable combined irq\n"); + smmu->combined_irq = 0; + } } else arm_smmu_setup_unique_irqs(smmu); @@ -4999,10 +5008,22 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu) return ret; } +/* Quiesce the queue IRQ threads, e.g. before disabling the SMMU */ +static void arm_smmu_disable_irqs(struct arm_smmu_device *smmu) +{ + if (smmu->combined_irq) + disable_irq(smmu->combined_irq); + if (smmu->evtq.q.irq) + disable_irq(smmu->evtq.q.irq); + if (smmu->priq.q.irq) + disable_irq(smmu->priq.q.irq); +} + static void arm_smmu_disable_action(void *data) { struct arm_smmu_device *smmu = data; + arm_smmu_disable_irqs(smmu); if (smmu->impl_ops && smmu->impl_ops->device_disable) smmu->impl_ops->device_disable(smmu); arm_smmu_device_disable(smmu); @@ -5149,18 +5170,23 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) ARM_SMMU_CR0ACK); if (ret) { dev_err(smmu->dev, "failed to enable SMMU interface\n"); - return ret; + goto err_disable_irqs; } if (smmu->impl_ops && smmu->impl_ops->device_reset) { ret = smmu->impl_ops->device_reset(smmu); if (ret) { dev_err(smmu->dev, "failed to reset impl\n"); - return ret; + goto err_disable_irqs; } } return 0; + +err_disable_irqs: + /* The probe error path cannot tell if the IRQs were requested */ + arm_smmu_disable_irqs(smmu); + return ret; } #define IIDR_IMPLEMENTER_ARM 0x43b -- 2.43.0