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X-CSE-ConnectionGUID: Fm4WJO+JQtCEf0ZpwAwKqA== X-CSE-MsgGUID: 4+gyDQLjQUepiV5YM5XrCA== X-IronPort-AV: E=Sophos;i="6.25,243,1779174000"; d="scan'208";a="61743666" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Aug 2026 10:14:43 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 25 Aug 2026 10:14:43 -0700 Received: from [10.159.227.160] (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 25 Aug 2026 10:14:41 -0700 Message-ID: <0cc2d875-7aab-4091-816c-031f21f3cbac@microchip.com> Date: Tue, 25 Aug 2026 19:14:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] arm64: dts: microchip: lan969x: add SDMMC nodes To: Robert Marko , , , , , , , , , , , CC: References: <20260824110432.1074136-1-robert.marko@sartura.hr> <20260824110432.1074136-2-robert.marko@sartura.hr> Content-Language: en-US, fr From: Aubin Constans In-Reply-To: <20260824110432.1074136-2-robert.marko@sartura.hr> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260825_101446_132307_C4B46058 X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 24/08/2026 12:56, Robert Marko wrote: > Add nodes for both SDMMC controllers. > > Signed-off-by: Robert Marko > --- > arch/arm64/boot/dts/microchip/lan9691.dtsi | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/dts/microchip/lan9691.dtsi > index a8541c6a098d..2d943ea75768 100644 > --- a/arch/arm64/boot/dts/microchip/lan9691.dtsi > +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi > @@ -414,6 +414,30 @@ qspi0: spi@e0804000 { > status = "disabled"; > }; > > + sdmmc0: mmc@e0830000 { > + compatible = "microchip,lan9691-sdhci", > + "microchip,sam9x60-sdhci"; > + reg = <0xe0830000 0x00000300>; > + interrupts = ; > + clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>; > + clock-names = "hclock", "multclk"; > + assigned-clocks = <&clks GCK_ID_SDMMC0>; > + assigned-clock-rates = <100000000>; If always targeting an e.MMC, capped at the High Speed DDR mode, one might consider a multiple of 52 MHz here. > + status = "disabled"; > + }; > + > + sdmmc1: mmc@e0838000 { > + compatible = "microchip,lan9691-sdhci", > + "microchip,sam9x60-sdhci"; > + reg = <0xe0838000 0x00000300>; > + interrupts = ; > + clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>; > + clock-names = "hclock", "multclk"; > + assigned-clocks = <&clks GCK_ID_SDMMC1>; > + assigned-clock-rates = <45000000>; > + status = "disabled"; > + }; > + > qspi2: spi@e0834000 { > compatible = "microchip,lan9691-qspi"; > reg = <0xe0834000 0x00000100>, > -- > 2.55.0 >