From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAD67CD128A for ; Sun, 7 Apr 2024 06:29:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To: References:Message-ID:Date:Subject:To:From:Reply-To:Cc:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=d6v0a4m8YuBNxMy3rn3WbMP19ktCKQFMZpFObysV/Y4=; b=gFc1S0Qq9y4G5F 7DYfUW0/NJTZ46W0x9+/IaTZpQQePvNJTgS0O1AGh5w1+O4oztWp8vWIcXdqsruukonyYrsjLPkWR 2kAVwODYDQeZTxbGVztDVaF6i/3bPtt10fqA3FXloN55ev7R5DwIR51i3iNnikFlh5JYabqMu1VlN +HrYDE4mEXSOZuTUWHiRMD13OP/Epo79IBWacpnBUKMgjBAbnjj05ne1Q6qg6Am2vzIdUR7VC29XJ IyfUJVw1r1SFTKrDsvxHwEM6dkrCz5hXtv9qrSp1wBcOyGMFKN4/F3vQ6GZiSyAjSkQQGER9FgbgA djM78gGFr178K6SVQvLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rtM1J-0000000Btew-3ZA0; Sun, 07 Apr 2024 06:28:49 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rtM1F-0000000BtdL-2je2 for linux-arm-kernel@lists.infradead.org; Sun, 07 Apr 2024 06:28:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1712471325; x=1744007325; h=from:to:subject:date:message-id:references:in-reply-to: content-id:content-transfer-encoding:mime-version; bh=n9Yyi98yxneO+uUBsEWQs8gX01bwQK7zJlZTOspGlA0=; b=ci0+Sn41h6behcgsoGpZbyV8Ur/1p/aZq0+dOssTwp3oFnaLwnz/0r73 U+LRK289NHIUitnVcQijrt2Lt3EQvgwzlTrk795szVcjW5DaCgnCAq6/M f/r9+hVh1eX8x11LqwiUUjRfS5fU2XJNyB3gl+rtFRj9yOSCkMGxTIm0Q rg9s8FkzcC0LOdyiveBIRFLvLaiGA/WWqsWRvabTVSkTYS50I3rLVsG2k mDr1Ec+9B/B/B4uWekHgxDGPXTAMkokRgK2yYZIjVvuPty3FuPiCuVEMy Awjt+d+3BIrSYKgHFgSBT6Z7amkGTcPL7oIY/Ba0Ud7czO1oFPbKwFKT1 g==; X-CSE-ConnectionGUID: A8dpXT1lQGisY6KcKuglZA== X-CSE-MsgGUID: q/1sXc9RSH2NmVTPpAZXsA== X-IronPort-AV: E=Sophos;i="6.07,184,1708412400"; d="scan'208";a="20443810" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 06 Apr 2024 23:28:42 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Sat, 6 Apr 2024 23:28:15 -0700 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (10.10.215.250) by email.microchip.com (10.10.87.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Sat, 6 Apr 2024 23:28:14 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=OPooCgpZKVjY0FKPAe9IL9D868QR0e3HIgKp4Q5Zw4F/eqDPZmMnlTDL4GEW58vbPldvct9WXzhG2WvGwDtm5kU6DlFjjJI8f7rWFRatgYlXOm/iI4SYfk9BxJPBM+1psZF0V/EK2B1DSDmhTT+3THZMfOVpdwlNHXCIy2C392WxcI0pxKsczlAyZK/e9a7QN+siusMOxtBewVyuH/txJx1YShG+nC2+HrU1sufyLk1QH3/6d6ZyVL4FQP1yJLCRWZUBKYZbts3Q+cH7GiZ+epo1gz+uiCyWLK3iP/uvpLI/lGrtHMxFGBS3B950DuKGsYf9Ku34KzXqIldrigWM2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n9Yyi98yxneO+uUBsEWQs8gX01bwQK7zJlZTOspGlA0=; b=KbFGJ4rrzp9OUNgPfzaTradeXVBAqRO7MJqoPziJjgGjJyDD5eeM73XDQ1sG6FnLxoZCBPCvEIVTYeNHrth1OEZKw/9BJKRLR10EY7tm+Bwast0IL2dTgXutjagw47kysGRTgnXXSu4gr+g1XtZjDnjMDNFF4P8ytdIlefst7uUZX4s0kkGJeL++4ZuDXq0agQg6BCOcTRfLTzVgtgf4PoAxBHCN4vihGPC0IAejjGdERBp+eJZpIkJPsNjEMob9Xm5M6ia13TkaNt4+8B3YCm+ZrK4bNKwEgGttgON3PWDjDCxo6UIF/CG8CBMcWjZdx4SGEHkfUUsNeiNpKzo0vg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchip.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=n9Yyi98yxneO+uUBsEWQs8gX01bwQK7zJlZTOspGlA0=; b=XV4UyDlXC2KYCjKGRzH6INV3BwB1nID7UFvG0RJ8hiJVH2Pjxbjy6FeY3i3WvcayzjxvotInbR3aRBr3vh3QXb66IAY6+CvU0pevOAy2PA7Q9xgvjAkT7gIuqx+YcvAAOf9FKXtQL2LV7BXu3QY8Ilsa2sdnE/cBTlH2C/76SHIOFsIQYmm/ulc4GJ2spdejHdZQgX3JxQVmrjnES/xYS1WXeDDMdLlVFwiPaOE6acY/Y/eBkEYZRXnU5iErxZ56BmZ8fZR2EoUQDP1e5UMJmz/WbTvndYWJN1wcMqt4PQ4Euvogjh596jHXeHK4R32PijaZMLxWCM0oPSfaOd5HQw== Received: from DM6PR11MB4185.namprd11.prod.outlook.com (2603:10b6:5:195::29) by IA1PR11MB8099.namprd11.prod.outlook.com (2603:10b6:208:448::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.33; Sun, 7 Apr 2024 06:28:12 +0000 Received: from DM6PR11MB4185.namprd11.prod.outlook.com ([fe80::8115:283b:fe3b:5983]) by DM6PR11MB4185.namprd11.prod.outlook.com ([fe80::8115:283b:fe3b:5983%5]) with mapi id 15.20.7452.019; Sun, 7 Apr 2024 06:28:12 +0000 From: To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v5 2/4] drm/bridge: add lvds controller support for sam9x7 Thread-Topic: [PATCH v5 2/4] drm/bridge: add lvds controller support for sam9x7 Thread-Index: AQHahxMFXv0LFRSma0S3uMnMXf9irrFcW12A Date: Sun, 7 Apr 2024 06:28:12 +0000 Message-ID: <0e392443-ed5d-42af-81b6-b6f48c64dbcb@microchip.com> References: <20240405043536.274220-1-dharma.b@microchip.com> <20240405043536.274220-3-dharma.b@microchip.com> In-Reply-To: <20240405043536.274220-3-dharma.b@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: DM6PR11MB4185:EE_|IA1PR11MB8099:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: z/p68tNvbUTAHEKO5AR4G+/zGD5AtuArFFPkpvUC1Sxxh4eKgfzPR46vH5H7r5AmoZ2b9Aqagi5mzBI1Gy9vVaJ0stUtSd5HwJRQrikOv0WuiCDwIhtbPZ1rc8SyolkpCQAHL9Tcg/qXVmF23UaZZggamtDFk6yQs6i+1zRuUDYx95FIT5RbIa+LLoHAzpHnV79pwphOcfuuvW/g0fD3UAtrL3w5Mz12dvSZ6GShC2afCC8rwLSPovZegT9WifxfjheYslZ9+h2aSW2WrrTSnnAH5hLSTqfi3q46pVmzyVaNGGQiEfT+PiRqVKeW5x2ClcmhktqO6Y4UUtvhFlkUw0+/dKEIJEoyS2CawzaiF6ok6YRRxu47Zz8vkcSKSBvBY4WQndu38A13Soh3/yk53qIWJ05tLswqBvVP/QagG+JQqBD48WqojmTbGvqXlY9pFtJmSqHYo1LVLKGbEFWMsrMJru7MoUvt5KQD7UDXjg/WaqZJHIXx+ZeY2uu83aSt6UMxbm4jFNATeWWsAMY7CQryVIqckGYPFcvFZnkF9K/20LTi6w1EPyoPIF1IkrAHFXu5la7IB+FTyvC0MTAJAY0pi9+PCuJ5FmdkgDBBN2dodH9jSdD3ZzodZ5MAFeyeBPLWH/Zc6WecVUjo24B81rMrpz/CGGkzip+Ce9IIyr8e9bkVZl8fpKHoNvoOKip+ x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR11MB4185.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(7416005)(1800799015)(376005)(366007)(921011);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?B?cVN1cWE5cGNXcVgvTER4UW4zYTR2ZkhmZ3kzVWlBeG5FWVc3MDEvbXFuZHdl?= =?utf-8?B?amZSd0ZvL1l6SjNJSm5GUUIzTUV5d2xjamZZKy8vNmJxYlZTTDNhZVFMRGNU?= =?utf-8?B?WWZhWnRLWm9aU0JSdWsxZnhUb2VIb0laMGlwSlRpZkxwWFpDNnMvdFk4ZEk2?= =?utf-8?B?TVM3bVNBSUZ1eGxwQ1FtY0NrTktoK3BNTk5ybFlUQy8wdXlDRlhGZGpjSTZW?= =?utf-8?B?bndLeDU5Rkwyc3Evc0h6TFYxVFNsS3hUdklZVGtXRnZ2YjdCK0dPUXFKMVpx?= =?utf-8?B?eGdiTjM3VTVWT256Z1RDbVNqYTIxRWdYVG5YRWo5c2V0dW50ZHJYT2VvMmNa?= =?utf-8?B?NVNYcytRSGVJbW1UVG9YL2xaWnJqUFFGWU1Hc3lFb2J6UWlqUDFXeEVpeVlD?= =?utf-8?B?MWwyWlV6WE9vWFJObVFQUm4wNHZOTVBZdi9xMDA0aTh3WVczdWVsT0R3eHlL?= =?utf-8?B?RnNVSXplL056YjJsOGhJYkoyWGxxRm5LVWllY0FUSjltbmxTVk0xK0NRckdu?= =?utf-8?B?WlFGdE5rSFBUaUExeTRiQjdoWGJ5V1k1QmNFS0pCNFg5Y0RvVTQ0S1BOUFI5?= =?utf-8?B?NlpwWHRzWTRFMmxhVGg0c0dwNGRiclNxQnhQV0NDNUI5V1N0RVo2aVgvNkIy?= =?utf-8?B?dEhYaU5nV09id3ZXaTBqMlhDS0QwMEhRd3l1Wmw1aUhQZ1BNV3hFdUxCWlRw?= =?utf-8?B?dnBCMWd1YkFhR1M3bkg5NDZmTzFvRThKTVZvSE54aDhXQyswTFBPRUQvd3l6?= =?utf-8?B?ZlFVL2JtNVBEWVVyT0FkcXVRbmpTRTMybXZTMUM1VGdjU1BxaStXUnA2Mzk3?= =?utf-8?B?U0c3eXNjZ1QyOTJDMXZtVWc3b1RGZFJ0S002TkJIWUtrUEtLZFdEdlorb0hY?= =?utf-8?B?M0pYRURyU0dVckFuV3lUSkoxamZ3LzJhdzJvR3gwVlEzc1A0RmZTWVVra1JQ?= =?utf-8?B?d2dZVHF5LzNzU1RpaTQ1bU5zRnNFQi90aVpBckFJcTY0K3EwZ2lYL2ozeEdu?= =?utf-8?B?SHdibG91T0xQcW9ES2Nad25qN0dPRis0bEFBM1JYaE5JZGtjV1NrRmMxS0E3?= =?utf-8?B?WVZWT2ZoRnFVWURITTB0cnpoeVEyN0RVOStsVEN1dU1idTF3ZC9kOGVvVVh5?= =?utf-8?B?aWo3dFlqTlJiakJTRXNYQzJUS25yNlRZOXR6L2JhZ3V6ZFErN0Q4MWRNbmZO?= =?utf-8?B?VFYxM3FFTWlENmN0MS9SUjYva29nOGFvNkM1RnFSOS9EZ0Z3OUpvUm9kcnlH?= =?utf-8?B?V1MveGxVU2FLMDA5QXVhOVZsV3ZSOS9EOUhsYTZleS9uV0ZPRitUeHJYZGhx?= =?utf-8?B?OElmYzYwZk5CbkJwbnByUjAzaWd2THREUE10enBXQ0JhMU8xMlpuVFlHRFVK?= =?utf-8?B?UE52SnhBVU4rTGp3Umt4eldrR1ZoY1NnZnVRMEFDNDk2Q2IydzRESVVhQXdm?= =?utf-8?B?bWxoMjZINFZ3TW1uWHRmb3lQL2dJalF6SG1uUnVDajY1RFZjWlhVMUgvcGVS?= =?utf-8?B?YjV2YnNvaC9vbzU5SmpuTndvdUM1SjIyUjVwMjhUZnR2ekFoa2dMUUkwSHdN?= =?utf-8?B?UkY0RVVNKytrRTdjRE9zM2NCMlN2OVRYMjFqeWhTY2xMNmtsNXlyL1FBM1R3?= =?utf-8?B?TmdMZ3pJdVU2NWZlWWZYbEg5R0s5V216L0JLS1FHSm9FUllEL1dFTFJ5RjVF?= =?utf-8?B?UHBIQkloaC9oNndZN0V3RWVCN3hWZG5SNm1EV0FmWDJnUFg3RDFQcU1meFA1?= =?utf-8?B?c0dObWV6M2tFNmVwZGpoRGVmTFdWUVNKSG0ra0d0OFh0cEJrYzZGTk52K2Fk?= =?utf-8?B?bDZ5UjhNQi9yMXhiTW9sc0FmUmU2a2RvS2ZoZHpWR0NxandFUHpKcUJ1NlFQ?= =?utf-8?B?TG9MaUc3RWZIMXpGc2xXdVV5dGlqcVdxQk5kWWFNb211c0FFV1cwWm41Tnp1?= =?utf-8?B?WlRXVnBlYXNueXZjN2xEb0tGbHZZVzd6NDdWckRYUGlFWEF6RnA5ZnBLb01r?= =?utf-8?B?NjY0TXhBK01IVHNLWXF2YjdIWTc5NHUzMmFLZGJ5OXduc1lPK0hMbW1RSHdT?= =?utf-8?B?QWU1V3RSTk1zZnhsSFoyNWcwQUJmSW5NQk15dU9tcXZUbGNLRGlXSnhGcVpl?= =?utf-8?B?aVYyQ1JvcXBsdmlyNVpSODBjbUxhTStJTkhlZHJIYXI1eWVKTlJtNG5jeFlX?= =?utf-8?B?Qmc9PQ==?= Content-ID: <33400910CE2DE442ABFCCE03667AA30B@namprd11.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB4185.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 310bfc44-829f-489b-053a-08dc56cbe66c X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Apr 2024 06:28:12.3895 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4k+08WA5nlwSoPqsXVoWcxGIACYdkpEmnw3RoyNBiaukfq3ynmawQWM2WtbRsXsG6oEUeruQvQrIhApGYE10JbOUGOrONH+PHPp6M4sRofw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB8099 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240406_232845_965459_28F4E416 X-CRM114-Status: GOOD ( 24.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 4/5/24 10:05 AM, Dharma Balasubiramani wrote: > Add a new LVDS controller driver for sam9x7 which does the following: > - Prepares and enables the LVDS Peripheral clock > - Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself > to the global bridge list. > - Identifies its output endpoint as panel and adds it to the encoder > display pipeline > - Enables the LVDS serializer Acked-by: Hari Prasath Gujulan Elango > > Signed-off-by: Manikandan Muralidharan > Signed-off-by: Dharma Balasubiramani > --- > Changelog > v4 -> v5 > - Drop the unused variable 'format'. > - Use DRM wrapper for dev_err() to maintain uniformity. > - return -ENODEV instead of -EINVAL to maintain consistency with other DRM > bridge drivers. > v3 -> v4 > - No changes. > v2 ->v3 > - Correct Typo error "serializer". > - Consolidate get() and prepare() functions and use devm_clk_get_prepared(). > - Remove unused variable 'ret' in probe(). > - Use devm_pm_runtime_enable() and drop the mchp_lvds_remove(). > v1 -> v2 > - Drop 'res' variable and combine two lines into one. > - Handle deferred probe properly, use dev_err_probe(). > - Don't print anything on deferred probe. Dropped print. > - Remove the MODULE_ALIAS and add MODULE_DEVICE_TABLE(). > - symbol 'mchp_lvds_driver' was not declared. It should be static. > --- > drivers/gpu/drm/bridge/Kconfig | 7 + > drivers/gpu/drm/bridge/Makefile | 1 + > drivers/gpu/drm/bridge/microchip-lvds.c | 228 ++++++++++++++++++++++++ > 3 files changed, 236 insertions(+) > create mode 100644 drivers/gpu/drm/bridge/microchip-lvds.c > > diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig > index efd996f6c138..889098e2d65f 100644 > --- a/drivers/gpu/drm/bridge/Kconfig > +++ b/drivers/gpu/drm/bridge/Kconfig > @@ -190,6 +190,13 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW > to DP++. This is used with the i.MX6 imx-ldb > driver. You are likely to say N here. > > +config DRM_MICROCHIP_LVDS_SERIALIZER > + tristate "Microchip LVDS serializer support" > + depends on OF > + depends on DRM_ATMEL_HLCDC > + help > + Support for Microchip's LVDS serializer. > + > config DRM_NWL_MIPI_DSI > tristate "Northwest Logic MIPI DSI Host controller" > depends on DRM > diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile > index 017b5832733b..7df87b582dca 100644 > --- a/drivers/gpu/drm/bridge/Makefile > +++ b/drivers/gpu/drm/bridge/Makefile > @@ -13,6 +13,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o > obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o > obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o > obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o > +obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) += microchip-lvds.o > obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o > obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o > obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o > diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c > new file mode 100644 > index 000000000000..149704f498a6 > --- /dev/null > +++ b/drivers/gpu/drm/bridge/microchip-lvds.c > @@ -0,0 +1,228 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries > + * > + * Author: Manikandan Muralidharan > + * Author: Dharma Balasubiramani > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define LVDS_POLL_TIMEOUT_MS 1000 > + > +/* LVDSC register offsets */ > +#define LVDSC_CR 0x00 > +#define LVDSC_CFGR 0x04 > +#define LVDSC_SR 0x0C > +#define LVDSC_WPMR 0xE4 > + > +/* Bitfields in LVDSC_CR (Control Register) */ > +#define LVDSC_CR_SER_EN BIT(0) > + > +/* Bitfields in LVDSC_CFGR (Configuration Register) */ > +#define LVDSC_CFGR_PIXSIZE_24BITS 0 > +#define LVDSC_CFGR_DEN_POL_HIGH 0 > +#define LVDSC_CFGR_DC_UNBALANCED 0 > +#define LVDSC_CFGR_MAPPING_JEIDA BIT(6) > + > +/*Bitfields in LVDSC_SR */ > +#define LVDSC_SR_CS BIT(0) > + > +/* Bitfields in LVDSC_WPMR (Write Protection Mode Register) */ > +#define LVDSC_WPMR_WPKEY_MASK GENMASK(31, 8) > +#define LVDSC_WPMR_WPKEY_PSSWD 0x4C5644 > + > +struct mchp_lvds { > + struct device *dev; > + void __iomem *regs; > + struct clk *pclk; > + struct drm_panel *panel; > + struct drm_bridge bridge; > + struct drm_bridge *panel_bridge; > +}; > + > +static inline struct mchp_lvds *bridge_to_lvds(struct drm_bridge *bridge) > +{ > + return container_of(bridge, struct mchp_lvds, bridge); > +} > + > +static inline u32 lvds_readl(struct mchp_lvds *lvds, u32 offset) > +{ > + return readl_relaxed(lvds->regs + offset); > +} > + > +static inline void lvds_writel(struct mchp_lvds *lvds, u32 offset, u32 val) > +{ > + writel_relaxed(val, lvds->regs + offset); > +} > + > +static void lvds_serialiser_on(struct mchp_lvds *lvds) > +{ > + unsigned long timeout = jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS); > + > + /* The LVDSC registers can only be written if WPEN is cleared */ > + lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & > + LVDSC_WPMR_WPKEY_MASK)); > + > + /* Wait for the status of configuration registers to be changed */ > + while (lvds_readl(lvds, LVDSC_SR) & LVDSC_SR_CS) { > + if (time_after(jiffies, timeout)) { > + DRM_DEV_ERROR(lvds->dev, "%s: timeout error\n", > + __func__); > + return; > + } > + usleep_range(1000, 2000); > + } > + > + /* Configure the LVDSC */ > + lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | > + LVDSC_CFGR_DC_UNBALANCED | > + LVDSC_CFGR_DEN_POL_HIGH | > + LVDSC_CFGR_PIXSIZE_24BITS)); > + > + /* Enable the LVDS serializer */ > + lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); > +} > + > +static int mchp_lvds_attach(struct drm_bridge *bridge, > + enum drm_bridge_attach_flags flags) > +{ > + struct mchp_lvds *lvds = bridge_to_lvds(bridge); > + > + bridge->encoder->encoder_type = DRM_MODE_ENCODER_LVDS; > + > + return drm_bridge_attach(bridge->encoder, lvds->panel_bridge, > + bridge, flags); > +} > + > +static void mchp_lvds_enable(struct drm_bridge *bridge) > +{ > + struct mchp_lvds *lvds = bridge_to_lvds(bridge); > + int ret; > + > + ret = clk_enable(lvds->pclk); > + if (ret < 0) { > + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); > + return; > + } > + > + ret = pm_runtime_get_sync(lvds->dev); > + if (ret < 0) { > + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); > + clk_disable(lvds->pclk); > + return; > + } > + > + lvds_serialiser_on(lvds); > +} > + > +static void mchp_lvds_disable(struct drm_bridge *bridge) > +{ > + struct mchp_lvds *lvds = bridge_to_lvds(bridge); > + > + pm_runtime_put(lvds->dev); > + clk_disable(lvds->pclk); > +} > + > +static const struct drm_bridge_funcs mchp_lvds_bridge_funcs = { > + .attach = mchp_lvds_attach, > + .enable = mchp_lvds_enable, > + .disable = mchp_lvds_disable, > +}; > + > +static int mchp_lvds_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mchp_lvds *lvds; > + struct device_node *port; > + > + if (!dev->of_node) > + return -ENODEV; > + > + lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); > + if (!lvds) > + return -ENOMEM; > + > + lvds->dev = dev; > + > + lvds->regs = devm_ioremap_resource(lvds->dev, > + platform_get_resource(pdev, IORESOURCE_MEM, 0)); > + if (IS_ERR(lvds->regs)) > + return PTR_ERR(lvds->regs); > + > + lvds->pclk = devm_clk_get_prepared(lvds->dev, "pclk"); > + if (IS_ERR(lvds->pclk)) > + return dev_err_probe(lvds->dev, PTR_ERR(lvds->pclk), > + "could not get pclk_lvds prepared\n"); > + > + port = of_graph_get_remote_node(dev->of_node, 1, 0); > + if (!port) { > + DRM_DEV_ERROR(dev, > + "can't find port point, please init lvds panel port!\n"); > + return -ENODEV; > + } > + > + lvds->panel = of_drm_find_panel(port); > + of_node_put(port); > + > + if (IS_ERR(lvds->panel)) > + return -EPROBE_DEFER; > + > + lvds->panel_bridge = devm_drm_panel_bridge_add(dev, lvds->panel); > + > + if (IS_ERR(lvds->panel_bridge)) > + return PTR_ERR(lvds->panel_bridge); > + > + lvds->bridge.of_node = dev->of_node; > + lvds->bridge.type = DRM_MODE_CONNECTOR_LVDS; > + lvds->bridge.funcs = &mchp_lvds_bridge_funcs; > + > + dev_set_drvdata(dev, lvds); > + devm_pm_runtime_enable(dev); > + > + drm_bridge_add(&lvds->bridge); > + > + return 0; > +} > + > +static const struct of_device_id mchp_lvds_dt_ids[] = { > + { > + .compatible = "microchip,sam9x75-lvds", > + }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, mchp_lvds_dt_ids); > + > +static struct platform_driver mchp_lvds_driver = { > + .probe = mchp_lvds_probe, > + .driver = { > + .name = "microchip-lvds", > + .of_match_table = mchp_lvds_dt_ids, > + }, > +}; > +module_platform_driver(mchp_lvds_driver); > + > +MODULE_AUTHOR("Manikandan Muralidharan "); > +MODULE_AUTHOR("Dharma Balasubiramani "); > +MODULE_DESCRIPTION("Low Voltage Differential Signaling Controller Driver"); > +MODULE_LICENSE("GPL"); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel