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X-CSE-ConnectionGUID: ukm/hrLiTMm6IMnH2cJKMA== X-CSE-MsgGUID: 5/kwA740T26ycGDYnnh3Jg== X-IronPort-AV: E=McAfee;i="6800,10657,11465"; a="62465438" X-IronPort-AV: E=Sophos;i="6.16,240,1744095600"; d="scan'208";a="62465438" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2025 00:10:09 -0700 X-CSE-ConnectionGUID: HFp5YyxzShG8ZygBfit8+A== X-CSE-MsgGUID: dPn4q0uRTlCcfFecEvm0Yw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,240,1744095600"; d="scan'208";a="148225683" Received: from allen-sbox.sh.intel.com (HELO [10.239.159.30]) ([10.239.159.30]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2025 00:10:01 -0700 Message-ID: <0e3c15ab-f38f-43e3-9de0-78e8ce486aca@linux.intel.com> Date: Mon, 16 Jun 2025 15:09:02 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 10/25] iommufd/viommu: Add IOMMUFD_CMD_HW_QUEUE_ALLOC ioctl To: Nicolin Chen Cc: jgg@nvidia.com, kevin.tian@intel.com, corbet@lwn.net, will@kernel.org, bagasdotme@gmail.com, robin.murphy@arm.com, joro@8bytes.org, thierry.reding@gmail.com, vdumpa@nvidia.com, jonathanh@nvidia.com, shuah@kernel.org, jsnitsel@redhat.com, nathan@kernel.org, peterz@infradead.org, yi.l.liu@intel.com, mshavit@google.com, praan@google.com, zhangzekun11@huawei.com, iommu@lists.linux.dev, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kselftest@vger.kernel.org, patches@lists.linux.dev, mochs@nvidia.com, alok.a.tiwari@oracle.com, vasant.hegde@amd.com, dwmw2@infradead.org References: <7dfb002613f224f57a069d27e7bf2b306b0a5ba0.1749884998.git.nicolinc@nvidia.com> <1ab8030b-8d2f-4ebe-a280-6d0e4e1d17c7@linux.intel.com> Content-Language: en-US From: Baolu Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250616_001010_772192_CC40F6C9 X-CRM114-Status: GOOD ( 17.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/16/25 15:04, Nicolin Chen wrote: > On Mon, Jun 16, 2025 at 02:54:10PM +0800, Baolu Lu wrote: >> On 6/16/25 14:47, Nicolin Chen wrote: >>> On Mon, Jun 16, 2025 at 02:12:04PM +0800, Baolu Lu wrote: >>>> On 6/14/25 15:14, Nicolin Chen wrote: >>>>> + if (!viommu->ops || !viommu->ops->get_hw_queue_size || >>>>> + !viommu->ops->hw_queue_init_phys) { >>>>> + rc = -EOPNOTSUPP; >>>>> + goto out_put_viommu; >>>>> + } >>> Hmm, here it does abort when !viommu->ops->hw_queue_init_phys .. >>> >>>>> + /* >>>>> + * FIXME once ops->hw_queue_init is introduced, this should check "if >>>>> + * ops->hw_queue_init_phys". And "access" should be initialized to NULL. >>>>> + */ >>>> I just don't follow here. Up until now, only viommu->ops-> >>>> hw_queue_init_phys has been added, which means the current code only >>>> supports hardware queues that access guest memory using physical >>>> addresses. The access object is not needed for the other type of >>>> hardware queue that uses guest IOVA. >>>> >>>> So, why not just abort here if ops->hw_queue_init_phys is not supported >>>> by the IOMMU driver? >>> .. so, it already does. >>> >>>> Leave other logics to the patches that introduce >>>> ops->hw_queue_init? I guess that would make this patch more readible. >>> The patch is doing in the way to support the hw_queue_init_phys >>> case only. It is just adding some extra FIXMEs as the guideline >>> for the future patch adding hw_queue_init op. >>> >>> I personally don't feel these are confusing. Maybe you can help >>> point out what specific wording feels odd here? Maybe "FIXME"s >>> should be "TODO"s? >> Oh, I probably misunderstood the logic here. For both hw_queue_init and >> hw_queue_init_phys, using an access object to pin the pages for hardware >> access is necessary, right? My understanding was that pinning pages is >> only required for hw_queue_init_phys. > No. The access is only used by the ops->hw_queue_init_phys case. > > The ops->hw_queue_init case will use the cmd->nesting_parent_iova > directly without calling iommufd_hw_queue_alloc_phys(). > > This FIXME means that, when adding ops->hw_queue_init, add this: > > - struct iommufd_access *access; > + struct iommufd_access *access = NULL; > ... > - access = iommufd_hw_queue_alloc_phys(cmd, viommu, &base_pa); > + if (ops->hw_queue_init_phys) { > + access = iommufd_hw_queue_alloc_phys(cmd, viommu, &base_pa); > > Also, the other FIXME guideline states that these two ops should be > mutually exclusive. So, add this too: > + if (WARN_ON_ONCE(ops->hw_queue_init && > + ops->hw_queue_init_phys)) { > + rc = -EOPNOTSUPP; Okay, above matches my understanding. Thanks for the explanation. Thanks, baolu