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From: Sean Anderson <sean.anderson@linux.dev>
To: Mark Brown <broonie@kernel.org>
Cc: "Mahapatra, Amit Kumar" <amit.kumar-mahapatra@amd.com>,
	"Simek, Michal" <michal.simek@amd.com>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	Jinjie Ruan <ruanjinjie@huawei.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Miquel Raynal <miquel.raynal@bootlin.com>,
	"amitrkcian2002@gmail.com" <amitrkcian2002@gmail.com>,
	"git (AMD-Xilinx)" <git@amd.com>
Subject: Re: [PATCH 5/7] spi: zynqmp-gqspi: Split the bus
Date: Tue, 21 Jan 2025 11:17:03 -0500	[thread overview]
Message-ID: <0ee72316-11e1-4930-8c49-92db8d148b8a@linux.dev> (raw)
In-Reply-To: <f1310bb6-48ef-4bdf-a359-f34b0d849a4d@sirena.org.uk>

On 1/21/25 11:01, Mark Brown wrote:
> On Tue, Jan 21, 2025 at 10:53:53AM -0500, Sean Anderson wrote:
>> On 1/21/25 08:19, Mahapatra, Amit Kumar wrote:
> 
>> > IMHO, restricting users to fixed names is not ideal. A better approach would be to 
>> > introduce a Device Tree (DT) property for the bus number and select the bus 
>> > accordingly.
> 
>> Why? It's not an artificial restriction; it reflects the hardware. And this is how
>> SPI busses are typically represented. If you have two SPI busses, there should be
>> two devicetree nodes.
> 
> Perhaps the thing is more that the buses are named instead of numbered?

Well, we could number them, but it's not like they have different
addresses in memory. They use all the same registers except for a bit in
the genfifo. So it doesn't make sense to do address translation (e.g.
with reg/ranges).

As for the names, these are the names used by the documentation, as well
as the exising driver. There are some references to SPI0/SPI1, but there
are more to upper/lower. If you want to bikeshed spi-0/spi-1 instead of
spi-lower/spi-upper, be my guest.

--Sean


  reply	other threads:[~2025-01-21 16:18 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-16 23:21 [PATCH 0/7] spi: zynqmp-gqspi: Split the bus and add GPIO support Sean Anderson
2025-01-16 23:21 ` [PATCH 1/7] dt-bindings: spi: zynqmp-qspi: Split the bus Sean Anderson
2025-01-22  0:16   ` David Lechner
2025-01-23 16:24     ` Sean Anderson
2025-01-23 21:59       ` David Lechner
2025-01-23 22:37         ` Sean Anderson
2025-01-24 13:35           ` Mark Brown
2025-06-12 23:44         ` Sean Anderson
2025-06-13 14:20           ` David Lechner
2025-06-13 15:57             ` Sean Anderson
2025-06-13 16:44               ` Sean Anderson
2025-06-13 16:53               ` David Lechner
2025-01-16 23:21 ` [PATCH 2/7] spi: zynqmp-gqspi: Pass speed/mode directly to config_op Sean Anderson
2025-01-16 23:21 ` [PATCH 3/7] spi: zynqmp-gqspi: Configure SPI mode dynamically Sean Anderson
2025-01-16 23:21 ` [PATCH 4/7] spi: zynqmp-gqspi: Refactor out controller initialization Sean Anderson
2025-01-16 23:21 ` [PATCH 5/7] spi: zynqmp-gqspi: Split the bus Sean Anderson
2025-01-21 13:19   ` Mahapatra, Amit Kumar
2025-01-21 15:53     ` Sean Anderson
2025-01-21 16:01       ` Mark Brown
2025-01-21 16:17         ` Sean Anderson [this message]
2025-01-16 23:21 ` [PATCH 6/7] spi: zynqmp-gqspi: Support GPIO chip selects Sean Anderson
2025-01-16 23:21 ` [PATCH 7/7] ARM64: xilinx: zynqmp: Convert to split QSPI bus Sean Anderson
2025-01-16 23:24 ` [PATCH 0/7] spi: zynqmp-gqspi: Split the bus and add GPIO support Sean Anderson

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