From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E49DEC25B75 for ; Mon, 3 Jun 2024 11:27:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z2YdYsRqfrSZYhnqaemAKPCnAcR/2V1/tfk/0Pztlp8=; b=3s37adqURJJiA6 HOIIQfyYDDOkHoS0Vb9/5f2ZOmFh+hUDK8bOrzE1+ctPmvvW2IMoMnI3VurcHgwGFE+bJ+qFfre1X nqEf6Vm+5+X1ZBMgzlz4FqHbtwtZ0dZJ2C9E4nqVfZnUNMSaqa0He2BQ6H4sqfP+escBOqM7djR+6 P/58zr3Z6pSYBi0KkOzkleAExyclLshjM+XfyV4dIuCMfMa9TGAWxjb53UhJANIhB70lDiUmoX7+3 Qv+35IZmbEbPRhImMDhuTbodIufG+6coBNcIutRA7KgSRNTDjGQHOmt6ZNQ+nWbGB9/eC1EviNt+e L31vbr1v9hmcW9LEsmLg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sE5qp-0000000GX4S-2V0E; Mon, 03 Jun 2024 11:27:43 +0000 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sE5qm-0000000GX3f-3zkV for linux-arm-kernel@lists.infradead.org; Mon, 03 Jun 2024 11:27:42 +0000 Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4539iu4O031125; Mon, 3 Jun 2024 11:27:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UOksZSJ5PozHDIJoVWdlMTf6jW6RoBLoVXN1Y8S/oII=; b=GJW63uyaQBHZzyEf J5lu4ervzIqtP58piB/ifoOU/b0sgRdKdYW/12oXSPHwLMea0CKGKmB75y1mv2fz jjgYe/HLuhwpqMBrmGx87Q6UwA1fsG9ZK9IGXd7nrIybRW1WO6+TZHO5mI5w2ZEp sUwHOQpjSRCe6GX3g2s6loyptFx5VKFt9GOQ3rmMLFRAuSF6CHlQaTKdme0HdVkI CAy2hh/SlSFkqmF+o2eV+4g2zM/moetQalUNwY+x5wrI3jZKnXGYsKG1KoJ4ogkm MMXiUa5eAZ1OdrVjmA32Uuaw86MauSIkIOqMKqy5QCa0ahgo31/kikDd1P5procz MCNRgA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3yfw6v3x8u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 03 Jun 2024 11:27:28 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 453BRRMc032665 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 3 Jun 2024 11:27:27 GMT Received: from [10.217.90.34] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 3 Jun 2024 04:27:19 -0700 Message-ID: <0ef00c92-b88f-48df-b9ba-2973c62285af@quicinc.com> Date: Mon, 3 Jun 2024 16:57:15 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next] net: stmmac: dwmac-qcom-ethqos: Add support for 2.5G SGMII To: "Russell King (Oracle)" CC: Andrew Halaney , Vinod Koul , Bhupesh Sharma , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , Maxime Coquelin , , , , , , References: <20231218071118.21879-1-quic_snehshah@quicinc.com> <4zbf5fmijxnajk7kygcjrcusf6tdnuzsqqboh23nr6f3rb3c4g@qkfofhq7jmv6> <8b80ab09-8444-4c3d-83b0-c7dbf5e58658@quicinc.com> <8f94489d-5f0e-4166-a14e-4959098a5c80@quicinc.com> Content-Language: en-US From: Sneh Shah In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jqtoM667x7WK9C9nDRZQZsjynG8xdZXN X-Proofpoint-ORIG-GUID: jqtoM667x7WK9C9nDRZQZsjynG8xdZXN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-06-03_07,2024-05-30_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 malwarescore=0 impostorscore=0 mlxscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406030096 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240603_042741_062510_12694271 X-CRM114-Status: GOOD ( 22.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 5/30/2024 1:39 AM, Russell King (Oracle) wrote: > On Wed, May 29, 2024 at 07:43:15PM +0530, Sneh Shah wrote: >> In this version of qualcomm ethernet, PCS is not an independent HW >> block. It is integrated to MAC block itself. It has very limited >> configuration.Here PCS doesn't have it's own link speed/duplex >> capabities. Hence we are bypassing all this PCS related functionalities. > > I want to concentrate on this part first - we'll address the 2.5G > issues separately once I've got a picture of this hardware (and thus > can work out what needs to change in my phylink_pcs implementation to > support the standard Cisco SGMII speeds. > > From what I understand you're saying, your integrated PCS is different > from the DesignWare integrated PCS? It's an inbuilt PCS block within designware ETHQoS core. > > Which core does it use? dwmac4_core.c or dwmac1000_core.c, or some > other? Not knowing which core makes asking the following questions > harder, since I'm having to double them up to cover both cores with > their different definitions. it is dwmac4 core with 0xe0 offset. > > Does it only present its status via the GMAC_PHYIF_CONTROL_STATUS or > GMAC_RGSMIIIS register? It is present via GMAC_PHYIF_CONTROL_STATUS. > > From what you're saying: > - if using the dwmac1000 core, then for the registers at GMAC_PCS_BASE > (0xc0 offset)... > - if using the dwmac4 core, then for registers at GMAC_PCS_BASE > (0xe0 offset)... > ... is it true that only the GMAC_AN_CTRL() register is implemented > and none of the other registers listed in stmmac_pcs.h? > > In terms of interrupts when the link status changes, how do they > present? Are they through the GMAC_INT_RGSMIIS interrupt only? > What about GMAC_INT_PCS_LINK or GMAC_INT_PCS_ANE? Or in the case > of the other core, is it through the PCS_RGSMIIIS_IRQ interrupt > only? Similarly, what about PCS_LINK_IRQ or PCS_ANE_IRQ? we only have GMAC_AN_CTRL and GMAC_AN_STATUS register. There is no separate IRQ line for PCS link or autoneg. It is notified via MAC interrupt line only. > > Thanks. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel