From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53873C43461 for ; Tue, 8 Sep 2020 09:53:44 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE3E32078E for ; Tue, 8 Sep 2020 09:53:43 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="p6ycsB4A" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CE3E32078E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wOHvy5zDtUipT1nMtcTrRfc8xNZ5TtlDKuOvpppADf4=; b=p6ycsB4A7wDcaZsBYIQCr9EqJ LrD25iFsEM+FcEV6jmTpeWeDKZz4I4wp59cBD+yc34J30x3TQgI2jg6rwbzOMiUq9vAscfLXaaWH5 4bQuVBTn3ryT5LbqFhD9gm47ZjzaJy41+7oGn7Ggot2W0lxDE6gqN39JScbgYmECA/vKeT3wuyFBW YiZ7kRhWYmaey/Wye+eZpR1ccQ8q/fL9EJZBt8c1aqG50nSZsRdGnQtmQiV5u1sGhlbvTnIFsZlMY x4ZJ/vTTlFHzeYjE4qmxjWFPn/aOeW7myBRCf+JrNeUpYAtw0dGEwTz7x8K7QGTJaw/NX+G7GGzi9 Dj3teZFnw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFaIV-0003Ln-JL; Tue, 08 Sep 2020 09:52:19 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFaIT-0003LL-67 for linux-arm-kernel@lists.infradead.org; Tue, 08 Sep 2020 09:52:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 48A2831B; Tue, 8 Sep 2020 02:52:16 -0700 (PDT) Received: from [10.57.6.175] (unknown [10.57.6.175]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 24D683F66E; Tue, 8 Sep 2020 02:52:11 -0700 (PDT) Subject: Re: [PATCH v2] Coresight: etm4x: add support for Self-hosted trace To: jonathan.zhouwen@huawei.com, linux-arm-kernel@lists.infradead.org References: <1598860966-70616-1-git-send-email-jonathan.zhouwen@huawei.com> From: Suzuki K Poulose Message-ID: <0ef7d1ec-09e5-06c9-8ff3-a68dbd42422b@arm.com> Date: Tue, 8 Sep 2020 10:56:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <1598860966-70616-1-git-send-email-jonathan.zhouwen@huawei.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200908_055217_353193_A2034ED3 X-CRM114-Status: GOOD ( 23.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhangshaokun@hisilicon.com, catalin.marinas@arm.com, will@kernel.org, mathieu.poirier@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08/31/2020 09:02 AM, Jonathan Zhou wrote: > ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4 > Self-hosted Trace Extensions. It provides control of exception > levels and security states. Let's add this feature detection and > enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is > supported. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Suzuki K Poulose > Cc: Shaokun Zhang > Signed-off-by: Jonathan Zhou > --- > arch/arm64/include/asm/sysreg.h | 8 ++++++++ > drivers/hwtracing/coresight/coresight-etm4x.c | 23 +++++++++++++++++++++++ > 2 files changed, 31 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 554a7e8ecb07..53da5f326667 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -184,6 +184,13 @@ > > #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) > > +/* Trace Filter control */ > +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) > +/* Trace is allowed at EL0 */ > +#define SYS_TRFCR_EL1_E0TRE BIT(0) > +/* Trace is allowed at EL1 */ > +#define SYS_TRFCR_EL1_E1TRE BIT(1) > + Please drop SYS suffix for the fields. > #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) > #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) > #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) > @@ -772,6 +779,7 @@ > #define ID_AA64MMFR2_CNP_SHIFT 0 > > /* id_aa64dfr0 */ > +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40 > #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 > #define ID_AA64DFR0_PMSVER_SHIFT 32 > #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 96425e818fc2..f72b457c2bad 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -28,6 +28,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -785,6 +786,24 @@ static void etm4_init_arch_data(void *info) > CS_LOCK(drvdata->base); > } > > +static void etm4_init_sysctrl(void *info) > +{ > + u64 sys_trfcr_el1, dfr0; > + int trace_filt; > + > + dfr0 = read_sysreg(id_aa64dfr0_el1); > + > + trace_filt = cpuid_feature_extract_unsigned_field(dfr0, > + ID_AA64DFR0_SELF_HOSTED_SHIFT); > + /* if selfhosted trace implemented, enable trace EL0 as default. */ What about EL1 ? We do support kernel tracing. I believe we need to do this every time when we enable etm4, based on the selected config. Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel