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Thu, 28 Aug 2025 21:09:17 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1ADA04002D; Thu, 28 Aug 2025 21:07:34 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9DE2276BE64; Thu, 28 Aug 2025 21:06:37 +0200 (CEST) Received: from [10.130.77.120] (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 28 Aug 2025 21:06:35 +0200 Message-ID: <0fbf4be0-af6e-4119-a838-e3fc9ab1fc9d@foss.st.com> Date: Thu, 28 Aug 2025 21:06:33 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v13 06/11] PCI: stm32: Add PCIe Endpoint support for STM32MP25 To: Bjorn Helgaas CC: , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20250828172253.GA949714@bhelgaas> From: Christian Bruel Content-Language: en-US In-Reply-To: <20250828172253.GA949714@bhelgaas> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.130.77.120] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-28_04,2025-08-28_01,2025-03-28_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250828_200931_042058_4A635B34 X-CRM114-Status: GOOD ( 17.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/28/25 19:22, Bjorn Helgaas wrote: > On Wed, Aug 20, 2025 at 09:54:06AM +0200, Christian Bruel wrote: >> Add driver to configure the STM32MP25 SoC PCIe Gen1 2.5GT/s or Gen2 5GT/s >> controller based on the DesignWare PCIe core in endpoint mode. >> ... > >> +static int stm32_pcie_start_link(struct dw_pcie *pci) >> +{ >> + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); >> + int ret; >> + >> + if (stm32_pcie->link_status == STM32_PCIE_EP_LINK_ENABLED) { >> + dev_dbg(pci->dev, "Link is already enabled\n"); >> + return 0; >> + } > > While looking at the "incorrectly reset" comment, I noticed > stm32_pcie->link_status and wondered why it exists. It looks like > it's only used in stm32_pcie_start_link() and stm32_pcie_stop_link(), > and I don't see similar tracking in other drivers. > > It feels a little racy because the link might go down for reasons > other than calling stm32_pcie_stop_link(). I think that as an excess of paranoid that was meant to protect against a driver unbind when the link hasn’t started yet. In that case, stm32_pcie_remove() would disable a link that’s already disabled. But that shouldn’t be a problem to disable twice the ltssm enable bit, as well as the perst irq. I’ll look into removing it. Is it okay if I do this with a fixup patch? thank you Christian > >> + dev_dbg(pci->dev, "Enable link\n"); >> + >> + ret = stm32_pcie_enable_link(pci); >> + if (ret) { >> + dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); >> + return ret; >> + } >> + >> + enable_irq(stm32_pcie->perst_irq); >> + >> + stm32_pcie->link_status = STM32_PCIE_EP_LINK_ENABLED; >> + >> + return 0; >> +} >> + >> +static void stm32_pcie_stop_link(struct dw_pcie *pci) >> +{ >> + struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); >> + >> + if (stm32_pcie->link_status == STM32_PCIE_EP_LINK_DISABLED) { >> + dev_dbg(pci->dev, "Link is already disabled\n"); >> + return; >> + } >> + >> + dev_dbg(pci->dev, "Disable link\n"); >> + >> + disable_irq(stm32_pcie->perst_irq); >> + >> + stm32_pcie_disable_link(pci); >> + >> + stm32_pcie->link_status = STM32_PCIE_EP_LINK_DISABLED; >> +}