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Mon, 31 Aug 2026 17:34:13 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v3 09/13] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Date: Mon, 31 Aug 2026 17:33:34 -0700 Message-ID: <0fe5f381aae307045e4cab97f8000c575f34a9ee.1788222486.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7C:EE_|CYYPR12MB8989:EE_ X-MS-Office365-Filtering-Correlation-Id: 581265a7-13e6-47c7-92c9-08df07c0ce68 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|1800799024|82310400026|376014|36860700016|18002099003|22082099003|56012099006|11063799006|10067099003; X-Microsoft-Antispam-Message-Info: hxNTsQl79WvODWvuvi9d2IxRUHjqcVsip5ujP1lSygKSmHOqinXzg7iiBhTUbiit7tkytgFtqGgZw7prIyRAawLdm19IhSLqImrZ7yMmBSXpUE+SrYorpyF+RcoI+amEScXWu6B9uPpVFeSDrqw/18oYaRDt8nfBnlxHoxUVnrh3P/UNSo8EqvRBa+dAy1aCgeIslq6AgynpmSAOgmS+o4pCFuvs/pwYfXuldcQuVTiFttcf8q7RXlZ77hCu7ZYMt/X86Q7touBU8GNIas8ZvWOjZ3B4O6SPSYrp1wOdxNN0soVk6kgRk6yMth5tdruJWwBV3A2rKup6xcHA4dMb8VVeC88KG0fs6NDXBWRJfXIWPLiMBLIobfeNLBWrms/bJzswlmKMvgGC/KgLX5KuyvCXZ6iVWJgZlmO61nQDq8WZ76aJLHbeuhudIhnxn1o3yxKQ3E4PIgtnNbskUeCPIyoEUCVgz2UVg7+Aru/53YkDbvW+tkKBqlxw04hN4GVZfKpWOkT71qeV35CsZCD5urIztjsKF8zXAm7KUgQ7PbjyeUhIBmnYqGKrorJes+M4BCFGa7V02sYkyK+YNV+Mhn7mp6MDXDLO/vIQRcTrCbe1ntNvJwOQM0zT1kECqFpyoFzQrTnoP6j+BnngxHZZv2dtEQIwJNwb8mqLw7Kjwat98szwhdB+cWEMw8X+IJfzmtKBzzYpDInxIKZd6gODgQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(7416014)(1800799024)(82310400026)(376014)(36860700016)(18002099003)(22082099003)(56012099006)(11063799006)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mmzEbGdAtb57C3JoGDaoIWSB7v5BzUYHNcxpZZFCHyEtc0yjxIcJdVW0LoxHaqx6lM9psrhYfqMyTshF9qlR0NyLlFThc1PE+AUMqiA+6/aerKG7HaCCOKv5ldvBDwjBywju57WzDWeGuihYHlFUD2qx7WdVQn3fYE7isVsz1PpVWLcHVlm7oDntyydzQuotIjZTX0q5gnem0i/fxDBoPECDEmcF7edTeHNTRDonsrYXAVel6YsJ0m0t9d/cOFVN+f2gelq9niyb6RfyO/XyaBUzBLVEq+EWIYSSjNoX1FPm3LaXWipEB/mIZX8nHg3LuYCyHtJPZPdAfRspc2FCyIa+r35c/ETexLGiRVVMi3xFzRwPogUZ441cyNzURIO//YAmzNGURWn1BXj2PqR2JRExLqnJ2blLrgC1XSzf+nCgvnU+1dy/3SPD9K4aqiEe X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2026 00:34:38.6382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 581265a7-13e6-47c7-92c9-08df07c0ce68 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8989 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260831_173448_179254_AA223A40 X-CRM114-Status: GOOD ( 18.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Now, arm_smmu_page_response() can issue CMDQ_OP_PRI_RESP for page requests from the IOPF infrastructure. Forward PRI requests from the priq into the IOPF infrastructure for PRI-enabled masters by building an iopf_fault from the priq entry and calling iommu_report_device_fault(). For an unrecognised StreamID or a master without master->pri_enabled, fall through to the existing "unexpected PRI request" log + LAST-page DENY path to release the credit per the PCIe PRI spec. Merge its two info prints in the path into one single ratelimited line, as a malfunctioning device can spam unrecognised requests and easily flood the kernel log. Discard any PASID Stop Marker (LRW = 0b100) prior to the fault report and the DENY fallback both, because a Stop Marker does not expect a response. The IOPF infrastructure requires the driver to discard it, as per the doc at iommu_report_device_fault(). This also matches the intel-iommu code. Note that master->pri_enabled will only be set by a later change, once all the PRI paths are ready. On PRIQ overflow, partial requests stored via report_partial_fault() whose LAST-page entry was lost stay in iopf_param->partial. Drop them by calling iopf_queue_discard_partial(), matching intel-iommu's handling. Do it after the queue is fully drained, since the visible entries all precede the loss point: a group whose LAST-page entry is still in the queue gets assembled before the discard, rather than losing its stored partials to it. Nor can a new arrival race against the discard, since an active overflow inhibits new entries from being written to the PRI queue (IHI0070 8.1), up until a final CONS write acknowledges it. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 59 +++++++++++++++++++-- 1 file changed, 55 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 60f21591de9e8..502b5c7673bc9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2368,6 +2368,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) { + struct arm_smmu_master *master; u32 sid, ssid; u16 grpid; bool ssv, last; @@ -2378,9 +2379,47 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) last = FIELD_GET(PRIQ_0_PRG_LAST, evt[0]); grpid = FIELD_GET(PRIQ_1_PRG_IDX, evt[1]); - dev_info(smmu->dev, "unexpected PRI request received:\n"); - dev_info(smmu->dev, - "\tsid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n", + /* + * A PASID Stop Marker (LRW = 0b100) does not expect a response and + * must be discarded before fault reporting: see the documentation + * at iommu_report_device_fault(). + */ + if (last && !(evt[0] & (PRIQ_0_PERM_READ | PRIQ_0_PERM_WRITE))) + return; + + mutex_lock(&smmu->streams_mutex); + master = arm_smmu_find_master(smmu, sid); + if (master && master->pri_enabled) { + struct iopf_fault iopf_fault = {}; + struct iommu_fault *fault = &iopf_fault.fault; + + fault->type = IOMMU_FAULT_PAGE_REQ; + if (last) + fault->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE; + if (ssv) { + fault->prm.flags |= + IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; + fault->prm.pasid = ssid; + } + fault->prm.grpid = grpid; + if (evt[0] & PRIQ_0_PERM_READ) + fault->prm.perm |= IOMMU_FAULT_PERM_READ; + if (evt[0] & PRIQ_0_PERM_WRITE) + fault->prm.perm |= IOMMU_FAULT_PERM_WRITE; + if (evt[0] & PRIQ_0_PERM_EXEC) + fault->prm.perm |= IOMMU_FAULT_PERM_EXEC; + if (evt[0] & PRIQ_0_PERM_PRIV) + fault->prm.perm |= IOMMU_FAULT_PERM_PRIV; + fault->prm.addr = FIELD_GET(PRIQ_1_ADDR_MASK, evt[1]) << 12; + + iommu_report_device_fault(master->dev, &iopf_fault); + mutex_unlock(&smmu->streams_mutex); + return; + } + mutex_unlock(&smmu->streams_mutex); + + dev_info_ratelimited(smmu->dev, + "unexpected PRI request: sid 0x%08x.0x%05x: [%u%s] %sprivileged %s%s%s access at iova 0x%016llx\n", sid, ssid, grpid, last ? "L" : "", evt[0] & PRIQ_0_PERM_PRIV ? "" : "un", evt[0] & PRIQ_0_PERM_READ ? "R" : "", @@ -2400,15 +2439,27 @@ static irqreturn_t arm_smmu_priq_thread(int irq, void *dev) struct arm_smmu_queue *q = &smmu->priq.q; struct arm_smmu_ll_queue *llq = &q->llq; u64 evt[PRIQ_ENT_DWORDS]; + bool overflow = false; do { while (!queue_remove_raw(q, evt)) arm_smmu_handle_ppr(smmu, evt); - if (queue_sync_prod_in(q) == -EOVERFLOW) + if (queue_sync_prod_in(q) == -EOVERFLOW) { dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); + overflow = true; + } } while (!queue_empty(llq)); + /* + * Discard the partial faults after the drain, so any group with its + * LAST-page entry visible in the queue gets assembled beforehand. An + * active overflow condition inhibits new entries from being written + * to the PRI queue, until it gets acknowledged below. + */ + if (overflow) + iopf_queue_discard_partial(smmu->evtq.iopf); + /* Sync our overflow flag, as we believe we're up to speed */ queue_sync_cons_ovf(q); return IRQ_HANDLED; -- 2.43.0