[PATCH v5 00/27] Add support for sam9x7 SoC family

[PATCH v5 00/27] Add support for sam9x7 SoC family

[Varshini Rajendran]

This patch series adds support for the new SoC family - sam9x7.
 - The device tree, configs and drivers are added
 - Clock driver for sam9x7 is added
 - Support for basic peripherals is added
 - Target board SAM9X75 Curiosity is added

 Changes in v5:
 --------------

 - Addressed all the review comments in the patches
 - Picked up all Acked-by and Reviewed-by tags
 - Dropped applied patches from the series
 - Addressed the ABI breakage reported in the IRQ patch
 - All the specific changes are captured in the corresponding patches

 Changes in v4:
 --------------

 - Addressed all the review comments in the patches
 - Picked up all Acked-by and Reviewed-by tags
 - Dropped applied patches from the series
 - Added pwm node and related dt binding documentation
 - Added support for exporting some clocks to DT
 - Dropped USB related patches and changes. See NOTE.
 - All the specific changes are captured in the corresponding patches

 NOTE: Owing to the discussion here
 https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=B7t+KS_kOinxaRx38=WxA@mail.gmail.com/
 the USB related changes are dropped from this series in order to enable
 us to work on the mentioned issues before adding new compatibles as
 said. The issues/warnings will be addressed in subsequent patches.
 After which the USB related support for sam9x7 SoCs will be added. Hope
 this works out fine.

 Changes in v3:
 --------------

 - Fixed the DT documentation errors pointed out in v2.
 - Dropped Acked-by tag in tcb DT doc patch as it had to be adapted
   according to sam9x7 correctly.
 - Picked by the previously missed tags.
 - Dropped this patch "dt-bindings: usb: generic-ehci: Document clock-names
   property" as the warning was not found while validating DT-schema for
   at91-sam9x75_curiosity.dtb.
 - Dropped redundant words in the commit message.
 - Fixed the CHECK_DTBS warnings validated against
   at91-sam9x75_curiosity.dtb.
 - Renamed dt nodes according to naming convention.
 - Dropped unwanted status property in dts.
 - Removed nodes that are not in use from the board dts.
 - Removed spi DT doc patch from the series as it was already applied
   and a fix patch was applied subsequently. Added a patch to remove the
   compatible to adapt sam9x7.
 - Added sam9x7 compatibles in usb dt documentation.


 Changes in v2:
 --------------

 - Added sam9x7 specific compatibles in DT with fallbacks
 - Documented all the newly added DT compatible strings
 - Added device tree for the target board sam9x75 curiosity and
   documented the same in the DT bindings documentation
 - Removed the dt nodes that are not supported at the moment
 - Removed the configs added by previous version that are not supported
   at the moment
 - Fixed all the corrections in the commit message
 - Changed all the instances of copyright year to 2023
 - Added sam9x7 flag in PIT64B configuration
 - Moved macro definitions to header file
 - Added another divider in mck characteristics in the pmc driver
 - Fixed the memory leak in the pmc driver
 - Dropped patches that are no longer needed
 - Picked up Acked-by and Reviewed-by tags


Varshini Rajendran (27):
  dt-bindings: atmel-sysreg: add sam9x7
  dt-bindings: atmel-ssc: add microchip,sam9x7-ssc
  dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.
  ARM: at91: pm: add support for sam9x7 SoC family
  ARM: at91: pm: add sam9x7 SoC init config
  ARM: at91: add support in SoC driver for new sam9x7
  dt-bindings: clocks: atmel,at91sam9x5-sckc
  dt-bindings: clocks: atmel,at91rm9200-pmc
  clk: at91: clk-sam9x60-pll: re-factor to support individual core freq
    outputs
  clk: at91: sam9x7: add support for HW PLL freq dividers
  clk: at91: sama7g5: move mux table macros to header file
  dt-bindings: clock: at91: Allow PLLs to be exported and referenced in
    DT
  clk: at91: sam9x7: add sam9x7 pmc driver
  dt-bindings: interrupt-controller: Add support for sam9x7 aic
  dt-bindings: interrupt-controller: Document the property
    microchip,nr-irqs
  irqchip/atmel-aic5: Add support to get nr_irqs from DT for sam9x60 &
    sam9x7
  ARM: dts: at91: sam9x60: Add nirqs property in the dt node
  power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7
  power: reset: at91-reset: add reset support for sam9x7 SoC
  power: reset: at91-reset: add sdhwc support for sam9x7 SoC
  dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7
  dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7
  ARM: at91: Kconfig: add config flag for SAM9X7 SoC
  ARM: configs: at91: enable config flags for sam9x7 SoC family
  ARM: dts: at91: sam9x7: add device tree for SoC
  dt-bindings: arm: add sam9x75 curiosity board
  ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

 .../devicetree/bindings/arm/atmel-at91.yaml   |    6 +
 .../devicetree/bindings/arm/atmel-sysregs.txt |    7 +-
 .../bindings/clock/atmel,at91rm9200-pmc.yaml  |    2 +
 .../bindings/clock/atmel,at91sam9x5-sckc.yaml |    4 +-
 .../interrupt-controller/atmel,aic.yaml       |   28 +-
 .../devicetree/bindings/misc/atmel-ssc.txt    |    1 +
 .../power/reset/atmel,sama5d2-shdwc.yaml      |    3 +
 .../reset/atmel,at91sam9260-reset.yaml        |    4 +
 .../bindings/serial/atmel,at91-usart.yaml     |    9 +-
 arch/arm/boot/dts/microchip/Makefile          |    3 +
 .../dts/microchip/at91-sam9x75_curiosity.dts  |  312 +++++
 arch/arm/boot/dts/microchip/sam9x60.dtsi      |    1 +
 arch/arm/boot/dts/microchip/sam9x7.dtsi       | 1226 +++++++++++++++++
 arch/arm/configs/at91_dt_defconfig            |    1 +
 arch/arm/mach-at91/Kconfig                    |   22 +-
 arch/arm/mach-at91/Makefile                   |    1 +
 arch/arm/mach-at91/generic.h                  |    2 +
 arch/arm/mach-at91/pm.c                       |   29 +
 arch/arm/mach-at91/sam9x7.c                   |   33 +
 drivers/clk/at91/Makefile                     |    1 +
 drivers/clk/at91/clk-sam9x60-pll.c            |   42 +-
 drivers/clk/at91/pmc.h                        |   18 +
 drivers/clk/at91/sam9x60.c                    |    7 +
 drivers/clk/at91/sam9x7.c                     |  946 +++++++++++++
 drivers/clk/at91/sama7g5.c                    |   42 +-
 drivers/irqchip/irq-atmel-aic5.c              |    8 +-
 drivers/power/reset/Kconfig                   |    4 +-
 drivers/power/reset/at91-sama5d2_shdwc.c      |    1 +
 drivers/soc/atmel/soc.c                       |   23 +
 drivers/soc/atmel/soc.h                       |    9 +
 include/dt-bindings/clock/at91.h              |    4 +
 31 files changed, 2750 insertions(+), 49 deletions(-)
 create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
 create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi
 create mode 100644 arch/arm/mach-at91/sam9x7.c
 create mode 100644 drivers/clk/at91/sam9x7.c

-- 
2.25.1

[PATCH v5 01/27] dt-bindings: atmel-sysreg: add sam9x7

[Varshini Rajendran]

Add RAM controller & SFR DT bindings.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/arm/atmel-sysregs.txt | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
index 67a66bf74895..1339298203c6 100644
--- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -11,7 +11,8 @@ PIT Timer required properties:
   shared across all System Controller members.
 
 PIT64B Timer required properties:
-- compatible: Should be "microchip,sam9x60-pit64b"
+- compatible: Should be "microchip,sam9x60-pit64b" or
+			"microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"
 - reg: Should contain registers location and length
 - interrupts: Should contain interrupt for PIT64B timer
 - clocks: Should contain the available clock sources for PIT64B timer.
@@ -31,7 +32,8 @@ RAMC SDRAM/DDR Controller required properties:
 			"atmel,at91sam9g45-ddramc",
 			"atmel,sama5d3-ddramc",
 			"microchip,sam9x60-ddramc",
-			"microchip,sama7g5-uddrc"
+			"microchip,sama7g5-uddrc",
+			"microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc".
 - reg: Should contain registers location and length
 
 Examples:
@@ -63,6 +65,7 @@ required properties:
 	"atmel,<chip>-sfrbu", "syscon"
   <chip> can be "sama5d3", "sama5d4" or "sama5d2".
   It also can be "microchip,sam9x60-sfr", "syscon".
+  It also can be "microchip,sam9x7-sfr", "microchip,sam9x60-sfr", "syscon".
 - reg: Should contain registers location and length
 
 	sfr@f0038000 {
-- 
2.25.1

[PATCH v5 02/27] dt-bindings: atmel-ssc: add microchip,sam9x7-ssc

[Varshini Rajendran]

Add microchip,sam9x7-ssc to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/misc/atmel-ssc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/misc/atmel-ssc.txt b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
index f9fb412642fe..894875826de9 100644
--- a/Documentation/devicetree/bindings/misc/atmel-ssc.txt
+++ b/Documentation/devicetree/bindings/misc/atmel-ssc.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
+	       or "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"
 	- atmel,at91rm9200-ssc: support pdc transfer
 	- atmel,at91sam9g45-ssc: support dma transfer
 - reg: Should contain SSC registers location and length
-- 
2.25.1

[PATCH v5 03/27] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Varshini Rajendran]

Add sam9x7 compatible to DT bindings documentation.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Corrected the order of bindings.
- sam9x60 bindings in the dts and dt documentation in future series.
---
 .../devicetree/bindings/serial/atmel,at91-usart.yaml     | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
index eb2992a447d7..f466c38518c4 100644
--- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
+++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
@@ -23,13 +23,20 @@ properties:
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart
       - items:
-          - const: microchip,sam9x60-usart
+          - enum:
+              - microchip,sam9x60-usart
+              - microchip,sam9x7-usart
           - const: atmel,at91sam9260-usart
       - items:
           - const: microchip,sam9x60-dbgu
           - const: microchip,sam9x60-usart
           - const: atmel,at91sam9260-dbgu
           - const: atmel,at91sam9260-usart
+      - items:
+          - const: microchip,sam9x7-dbgu
+          - const: atmel,at91sam9260-dbgu
+          - const: microchip,sam9x7-usart
+          - const: atmel,at91sam9260-usart
 
   reg:
     maxItems: 1
-- 
2.25.1

Re: [PATCH v5 03/27] dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1806 bytes --]

On Wed, Jul 03, 2024 at 03:56:40PM +0530, Varshini Rajendran wrote:
> Add sam9x7 compatible to DT bindings documentation.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v5:
> - Corrected the order of bindings.
> - sam9x60 bindings in the dts and dt documentation in future series.
> ---
>  .../devicetree/bindings/serial/atmel,at91-usart.yaml     | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> index eb2992a447d7..f466c38518c4 100644
> --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml
> @@ -23,13 +23,20 @@ properties:
>            - const: atmel,at91sam9260-dbgu
>            - const: atmel,at91sam9260-usart
>        - items:
> -          - const: microchip,sam9x60-usart
> +          - enum:
> +              - microchip,sam9x60-usart
> +              - microchip,sam9x7-usart
>            - const: atmel,at91sam9260-usart
>        - items:
>            - const: microchip,sam9x60-dbgu
>            - const: microchip,sam9x60-usart
>            - const: atmel,at91sam9260-dbgu
>            - const: atmel,at91sam9260-usart
> +      - items:
> +          - const: microchip,sam9x7-dbgu
> +          - const: atmel,at91sam9260-dbgu

> +          - const: microchip,sam9x7-usart

I still think that this particular compatible shouldn't be here, but I
did say I would accept this version.
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> +          - const: atmel,at91sam9260-usart
>  
>    reg:
>      maxItems: 1
> -- 
> 2.25.1
> 

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[PATCH v5 04/27] ARM: at91: pm: add support for sam9x7 SoC family

[Varshini Rajendran]

Add support and pm init config for sam9x7 SoC.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Changes in v5:
- Removed usb related ids.
- Added sam9x7 specific rtc, rtt compatibles instead of sam9x60.
- Removed gmac id.
- Removed a blank line.
---
 arch/arm/mach-at91/generic.h |  2 ++
 arch/arm/mach-at91/pm.c      | 29 +++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+)

diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 0c3960a8b3eb..acf0b3c82a30 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -12,6 +12,7 @@
 extern void __init at91rm9200_pm_init(void);
 extern void __init at91sam9_pm_init(void);
 extern void __init sam9x60_pm_init(void);
+extern void __init sam9x7_pm_init(void);
 extern void __init sama5_pm_init(void);
 extern void __init sama5d2_pm_init(void);
 extern void __init sama7_pm_init(void);
@@ -19,6 +20,7 @@ extern void __init sama7_pm_init(void);
 static inline void __init at91rm9200_pm_init(void) { }
 static inline void __init at91sam9_pm_init(void) { }
 static inline void __init sam9x60_pm_init(void) { }
+static inline void __init sam9x7_pm_init(void) { }
 static inline void __init sama5_pm_init(void) { }
 static inline void __init sama5d2_pm_init(void) { }
 static inline void __init sama7_pm_init(void) { }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 345b91dc6627..c0c861e1b8c1 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -233,6 +233,13 @@ static const struct of_device_id sama7g5_ws_ids[] = {
 	{ /* sentinel */ }
 };
 
+static const struct of_device_id sam9x7_ws_ids[] = {
+	{ .compatible = "microchip,sam9x7-rtc",		.data = &ws_info[1] },
+	{ .compatible = "microchip,sam9x7-rtt",		.data = &ws_info[4] },
+	{ .compatible = "microchip,sam9x7-gem",		.data = &ws_info[5] },
+	{ /* sentinel */ }
+};
+
 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
 {
 	const struct wakeup_source_info *wsi;
@@ -1362,6 +1369,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
 	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
 	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
 	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
+	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
 	{ /* sentinel */ },
 };
 
@@ -1499,6 +1507,27 @@ void __init sam9x60_pm_init(void)
 	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
 }
 
+void __init sam9x7_pm_init(void)
+{
+	static const int modes[] __initconst = {
+		AT91_PM_STANDBY, AT91_PM_ULP0,
+	};
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_SOC_SAM9X7))
+		return;
+
+	at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
+	ret = at91_dt_ramc(false);
+	if (ret)
+		return;
+
+	at91_pm_init(NULL);
+
+	soc_pm.ws_ids = sam9x7_ws_ids;
+	soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
+}
+
 void __init at91sam9_pm_init(void)
 {
 	int ret;
-- 
2.25.1

Re: [PATCH v5 04/27] ARM: at91: pm: add support for sam9x7 SoC family

[claudiu beznea]

On 03.07.2024 13:26, Varshini Rajendran wrote:
>  static int at91_pm_config_ws(unsigned int pm_mode, bool set)
>  {
>  	const struct wakeup_source_info *wsi;
> @@ -1362,6 +1369,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
>  	{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
>  	{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
>  	{ .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
> +	{ .compatible = "microchip,sam9x7-pmc", .data = &pmc_infos[4] },
>  	{ /* sentinel */ },

I would keep this sorted alphanumerically. No need to resent this, I'll
adjust when applying (and send a patch to adjust it for sama5d2, d3, d4).

[PATCH v5 05/27] ARM: at91: pm: add sam9x7 SoC init config

[Varshini Rajendran]

Add SoC init config for sam9x7 family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Removed unnecessary header file.
- Added a space in the return type for clarity.
---
 arch/arm/mach-at91/Makefile |  1 +
 arch/arm/mach-at91/sam9x7.c | 33 +++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 arch/arm/mach-at91/sam9x7.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 794bd12ab0a8..7d8a7bc44e65 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -7,6 +7,7 @@
 obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o
 obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam9.o
 obj-$(CONFIG_SOC_SAM9X60)	+= sam9x60.o
+obj-$(CONFIG_SOC_SAM9X7)	+= sam9x7.o
 obj-$(CONFIG_SOC_SAMA5)		+= sama5.o sam_secure.o
 obj-$(CONFIG_SOC_SAMA7)		+= sama7.o
 obj-$(CONFIG_SOC_SAMV7)		+= samv7.o
diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
new file mode 100644
index 000000000000..e1ff30b5b09b
--- /dev/null
+++ b/arch/arm/mach-at91/sam9x7.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Setup code for SAM9X7.
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+
+#include "generic.h"
+
+static void __init sam9x7_init(void)
+{
+	of_platform_default_populate(NULL, NULL, NULL);
+
+	sam9x7_pm_init();
+}
+
+static const char * const sam9x7_dt_board_compat[] __initconst = {
+	"microchip,sam9x7",
+	NULL
+};
+
+DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
+	/* Maintainer: Microchip */
+	.init_machine	= sam9x7_init,
+	.dt_compat	= sam9x7_dt_board_compat,
+MACHINE_END
-- 
2.25.1

Re: [PATCH v5 05/27] ARM: at91: pm: add sam9x7 SoC init config

[Alexandre Belloni]

On 03/07/2024 15:57:02+0530, Varshini Rajendran wrote:
> Add SoC init config for sam9x7 family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v5:
> - Removed unnecessary header file.
> - Added a space in the return type for clarity.
> ---
>  arch/arm/mach-at91/Makefile |  1 +
>  arch/arm/mach-at91/sam9x7.c | 33 +++++++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)
>  create mode 100644 arch/arm/mach-at91/sam9x7.c
> 
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 794bd12ab0a8..7d8a7bc44e65 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -7,6 +7,7 @@
>  obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o
>  obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam9.o
>  obj-$(CONFIG_SOC_SAM9X60)	+= sam9x60.o
> +obj-$(CONFIG_SOC_SAM9X7)	+= sam9x7.o
>  obj-$(CONFIG_SOC_SAMA5)		+= sama5.o sam_secure.o
>  obj-$(CONFIG_SOC_SAMA7)		+= sama7.o
>  obj-$(CONFIG_SOC_SAMV7)		+= samv7.o
> diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
> new file mode 100644
> index 000000000000..e1ff30b5b09b
> --- /dev/null
> +++ b/arch/arm/mach-at91/sam9x7.c
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Setup code for SAM9X7.
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/mach/arch.h>
> +
> +#include "generic.h"
> +
> +static void __init sam9x7_init(void)
> +{
> +	of_platform_default_populate(NULL, NULL, NULL);

Can you check whether this call is actually needed to boot the platform?

> +
> +	sam9x7_pm_init();
> +}
> +
> +static const char * const sam9x7_dt_board_compat[] __initconst = {
> +	"microchip,sam9x7",
> +	NULL
> +};
> +
> +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
> +	/* Maintainer: Microchip */
> +	.init_machine	= sam9x7_init,
> +	.dt_compat	= sam9x7_dt_board_compat,
> +MACHINE_END
> -- 
> 2.25.1
> 

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v5 05/27] ARM: at91: pm: add sam9x7 SoC init config

[Varshini.Rajendran]

Hi Alexandre,

On 03/07/24 4:25 pm, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 03/07/2024 15:57:02+0530, Varshini Rajendran wrote:
>> Add SoC init config for sam9x7 family.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v5:
>> - Removed unnecessary header file.
>> - Added a space in the return type for clarity.
>> ---
>>   arch/arm/mach-at91/Makefile |  1 +
>>   arch/arm/mach-at91/sam9x7.c | 33 +++++++++++++++++++++++++++++++++
>>   2 files changed, 34 insertions(+)
>>   create mode 100644 arch/arm/mach-at91/sam9x7.c
>>
>> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
>> index 794bd12ab0a8..7d8a7bc44e65 100644
>> --- a/arch/arm/mach-at91/Makefile
>> +++ b/arch/arm/mach-at91/Makefile
>> @@ -7,6 +7,7 @@
>>   obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
>>   obj-$(CONFIG_SOC_AT91SAM9)   += at91sam9.o
>>   obj-$(CONFIG_SOC_SAM9X60)    += sam9x60.o
>> +obj-$(CONFIG_SOC_SAM9X7)     += sam9x7.o
>>   obj-$(CONFIG_SOC_SAMA5)              += sama5.o sam_secure.o
>>   obj-$(CONFIG_SOC_SAMA7)              += sama7.o
>>   obj-$(CONFIG_SOC_SAMV7)              += samv7.o
>> diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
>> new file mode 100644
>> index 000000000000..e1ff30b5b09b
>> --- /dev/null
>> +++ b/arch/arm/mach-at91/sam9x7.c
>> @@ -0,0 +1,33 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Setup code for SAM9X7.
>> + *
>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>> + */
>> +
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +
>> +#include <asm/mach/arch.h>
>> +
>> +#include "generic.h"
>> +
>> +static void __init sam9x7_init(void)
>> +{
>> +     of_platform_default_populate(NULL, NULL, NULL);
> 
> Can you check whether this call is actually needed to boot the platform?
> 
Though the system boots, I can see many failures in crucial devices 
getting probed.

>> +
>> +     sam9x7_pm_init();
>> +}
>> +
>> +static const char * const sam9x7_dt_board_compat[] __initconst = {
>> +     "microchip,sam9x7",
>> +     NULL
>> +};
>> +
>> +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
>> +     /* Maintainer: Microchip */
>> +     .init_machine   = sam9x7_init,
>> +     .dt_compat      = sam9x7_dt_board_compat,
>> +MACHINE_END
>> --
>> 2.25.1
>>
> 
> --
> Alexandre Belloni, co-owner and COO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH v5 05/27] ARM: at91: pm: add sam9x7 SoC init config

[claudiu beznea]

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Add SoC init config for sam9x7 family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Removed unnecessary header file.
> - Added a space in the return type for clarity.
> ---
>  arch/arm/mach-at91/Makefile |  1 +
>  arch/arm/mach-at91/sam9x7.c | 33 +++++++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)
>  create mode 100644 arch/arm/mach-at91/sam9x7.c
> 
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index 794bd12ab0a8..7d8a7bc44e65 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -7,6 +7,7 @@
>  obj-$(CONFIG_SOC_AT91RM9200)	+= at91rm9200.o
>  obj-$(CONFIG_SOC_AT91SAM9)	+= at91sam9.o
>  obj-$(CONFIG_SOC_SAM9X60)	+= sam9x60.o
> +obj-$(CONFIG_SOC_SAM9X7)	+= sam9x7.o
>  obj-$(CONFIG_SOC_SAMA5)		+= sama5.o sam_secure.o
>  obj-$(CONFIG_SOC_SAMA7)		+= sama7.o
>  obj-$(CONFIG_SOC_SAMV7)		+= samv7.o
> diff --git a/arch/arm/mach-at91/sam9x7.c b/arch/arm/mach-at91/sam9x7.c
> new file mode 100644
> index 000000000000..e1ff30b5b09b
> --- /dev/null
> +++ b/arch/arm/mach-at91/sam9x7.c
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Setup code for SAM9X7.
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/mach/arch.h>
> +
> +#include "generic.h"
> +
> +static void __init sam9x7_init(void)
> +{
> +	of_platform_default_populate(NULL, NULL, NULL);
> +
> +	sam9x7_pm_init();
> +}
> +
> +static const char * const sam9x7_dt_board_compat[] __initconst = {
> +	"microchip,sam9x7",
> +	NULL
> +};
> +
> +DT_MACHINE_START(sam9x7_dt, "Microchip SAM9X7")
> +	/* Maintainer: Microchip */
> +	.init_machine	= sam9x7_init,
> +	.dt_compat	= sam9x7_dt_board_compat,
> +MACHINE_END

[PATCH v5 06/27] ARM: at91: add support in SoC driver for new sam9x7

[Varshini Rajendran]

Add support for SAM9X7 SoC in the SoC driver.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
Changes in v5:
- Changed the RAM size in bytes.
- Alphanumerically sorted the entries.
- Sorted SoC entries by name and size.
---
 drivers/soc/atmel/soc.c | 23 +++++++++++++++++++++++
 drivers/soc/atmel/soc.h |  9 +++++++++
 2 files changed, 32 insertions(+)

diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
index cc9a3e107479..2a42b28931c9 100644
--- a/drivers/soc/atmel/soc.c
+++ b/drivers/soc/atmel/soc.c
@@ -101,6 +101,29 @@ static const struct at91_soc socs[] __initconst = {
 		 AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
 		 "sam9x60 8MiB SDRAM SiP", "sam9x60"),
 #endif
+#ifdef CONFIG_SOC_SAM9X7
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X70_EXID_MATCH,
+		 "sam9x70", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X72_EXID_MATCH,
+		 "sam9x72", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1M_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 16MB DDR2 SiP", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D5M_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 64MB DDR2 SiP", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D1G_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 125MB DDR3L SiP ", "sam9x7"),
+	AT91_SOC(SAM9X7_CIDR_MATCH, SAM9X75_D2G_EXID_MATCH,
+		 AT91_CIDR_VERSION_MASK, SAM9X75_EXID_MATCH,
+		 "sam9x75 250MB DDR3L SiP", "sam9x7"),
+#endif
 #ifdef CONFIG_SOC_SAMA5
 	AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
 		 AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
index 7a9f47ce85fb..2c78e54255f7 100644
--- a/drivers/soc/atmel/soc.h
+++ b/drivers/soc/atmel/soc.h
@@ -44,6 +44,7 @@ at91_soc_init(const struct at91_soc *socs);
 #define AT91SAM9X5_CIDR_MATCH		0x019a05a0
 #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
 #define SAM9X60_CIDR_MATCH		0x019b35a0
+#define SAM9X7_CIDR_MATCH		0x09750020
 #define SAMA7G5_CIDR_MATCH		0x00162100
 
 #define AT91SAM9M11_EXID_MATCH		0x00000001
@@ -66,6 +67,14 @@ at91_soc_init(const struct at91_soc *socs);
 #define SAM9X60_D1G_EXID_MATCH		0x00000010
 #define SAM9X60_D6K_EXID_MATCH		0x00000011
 
+#define SAM9X70_EXID_MATCH		0x00000005
+#define SAM9X72_EXID_MATCH		0x00000004
+#define SAM9X75_D1G_EXID_MATCH		0x00000018
+#define SAM9X75_D2G_EXID_MATCH		0x00000020
+#define SAM9X75_D1M_EXID_MATCH		0x00000003
+#define SAM9X75_D5M_EXID_MATCH		0x00000010
+#define SAM9X75_EXID_MATCH		0x00000000
+
 #define SAMA7G51_EXID_MATCH		0x3
 #define SAMA7G52_EXID_MATCH		0x2
 #define SAMA7G53_EXID_MATCH		0x1
-- 
2.25.1

[PATCH v5 07/27] dt-bindings: clocks: atmel,at91sam9x5-sckc

[Varshini Rajendran]

Add bindings for SAM9X7's slow clock controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v5:
- Changed subject according to suggestion.
- Alphanumerically sorted entries.
- Updated Acked-by tag.
---
 .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml      | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
index 7be29877e6d2..c2283cd07f05 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
@@ -18,7 +18,9 @@ properties:
           - atmel,sama5d4-sckc
           - microchip,sam9x60-sckc
       - items:
-          - const: microchip,sama7g5-sckc
+          - enum:
+              - microchip,sam9x7-sckc
+              - microchip,sama7g5-sckc
           - const: microchip,sam9x60-sckc
 
   reg:
-- 
2.25.1

Re: [PATCH v5 07/27] dt-bindings: clocks: atmel,at91sam9x5-sckc

[claudiu beznea]

Hi, Varshini,

In my comment from v4 I meant to say:

dt-bindings: clk: at91: add sam9x7 -> dt-bindings: clocks: at91sam9x5-sckc:
add sam9x7

Suggestion was:
s/dt-bindings: clk: at91/dt-bindings: clocks: at91sam9x5-sckc

Anyway, I'll adjust it when applying. No need to resent just for this.

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Add bindings for SAM9X7's slow clock controller.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Other than the title:

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Changed subject according to suggestion.
> - Alphanumerically sorted entries.
> - Updated Acked-by tag.
> ---
>  .../devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml      | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> index 7be29877e6d2..c2283cd07f05 100644
> --- a/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> +++ b/Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml
> @@ -18,7 +18,9 @@ properties:
>            - atmel,sama5d4-sckc
>            - microchip,sam9x60-sckc
>        - items:
> -          - const: microchip,sama7g5-sckc
> +          - enum:
> +              - microchip,sam9x7-sckc
> +              - microchip,sama7g5-sckc
>            - const: microchip,sam9x60-sckc
>  
>    reg:

[PATCH v5 08/27] dt-bindings: clocks: atmel,at91rm9200-pmc

[Varshini Rajendran]

Add bindings for SAM9X7's pmc.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v5:
- Changed subject according to suggestion.
- Alphanumerically sorted entries.
- Updated Acked-by tag.
---
 .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml         | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
index c1bdcd9058ed..c9eb60776b4d 100644
--- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
+++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
@@ -42,6 +42,7 @@ properties:
               - atmel,sama5d3-pmc
               - atmel,sama5d4-pmc
               - microchip,sam9x60-pmc
+              - microchip,sam9x7-pmc
               - microchip,sama7g5-pmc
           - const: syscon
 
@@ -88,6 +89,7 @@ allOf:
           contains:
             enum:
               - microchip,sam9x60-pmc
+              - microchip,sam9x7-pmc
               - microchip,sama7g5-pmc
     then:
       properties:
-- 
2.25.1

Re: [PATCH v5 08/27] dt-bindings: clocks: atmel,at91rm9200-pmc

[claudiu beznea]

Same for this one:

dt-bindings: clocks: at91: add sam9x7 clock controller ->
dt-bindings: clocks: atmel,at91rm9200-pmc: add sam9x7 clock controller

I'll adjust it when applying.

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Add bindings for SAM9X7's pmc.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

Other than the title:

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Changed subject according to suggestion.
> - Alphanumerically sorted entries.
> - Updated Acked-by tag.
> ---
>  .../devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml         | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> index c1bdcd9058ed..c9eb60776b4d 100644
> --- a/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> +++ b/Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml
> @@ -42,6 +42,7 @@ properties:
>                - atmel,sama5d3-pmc
>                - atmel,sama5d4-pmc
>                - microchip,sam9x60-pmc
> +              - microchip,sam9x7-pmc
>                - microchip,sama7g5-pmc
>            - const: syscon
>  
> @@ -88,6 +89,7 @@ allOf:
>            contains:
>              enum:
>                - microchip,sam9x60-pmc
> +              - microchip,sam9x7-pmc
>                - microchip,sama7g5-pmc
>      then:
>        properties:

[PATCH v5 09/27] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs

[Varshini Rajendran]

SAM9X7 SoC family supports different core output frequencies for
different PLL IDs. To handle the same in the PLL driver, a separate
parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers
are aligned to the PLL driver by adding the core output freq range in
the PLL characteristics configurations.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------
 drivers/clk/at91/pmc.h             |  1 +
 drivers/clk/at91/sam9x60.c         |  7 +++++++
 drivers/clk/at91/sama7g5.c         |  7 +++++++
 4 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index ff65f7b916f0..b0314dfd7393 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -23,9 +23,6 @@
 #define UPLL_DIV		2
 #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
 
-#define FCORE_MIN		(600000000)
-#define FCORE_MAX		(1200000000)
-
 #define PLL_MAX_ID		7
 
 struct sam9x60_pll_core {
@@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 	unsigned long nmul = 0;
 	unsigned long nfrac = 0;
 
-	if (rate < FCORE_MIN || rate > FCORE_MAX)
+	if (rate < core->characteristics->core_output[0].min ||
+	    rate > core->characteristics->core_output[0].max)
 		return -ERANGE;
 
 	/*
@@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 	}
 
 	/* Check if resulted rate is a valid.  */
-	if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
+	if (tmprate < core->characteristics->core_output[0].min ||
+	    tmprate > core->characteristics->core_output[0].max)
 		return -ERANGE;
 
 	if (update) {
@@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			goto free;
 		}
 
-		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
+		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core,
+							characteristics->core_output[0].min,
 							parent_rate, true);
 		if (ret < 0) {
 			hw = ERR_PTR(ret);
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 0f52e80bcd49..bb9da35198d9 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -75,6 +75,7 @@ struct clk_pll_characteristics {
 	struct clk_range input;
 	int num_output;
 	const struct clk_range *output;
+	const struct clk_range *core_output;
 	u16 *icpll;
 	u8 *out;
 	u8 upll : 1;
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index e309cbf3cb9a..db6db9e2073e 100644
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = {
 	{ .min = 2343750, .max = 1200000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
 static const struct clk_pll_characteristics plla_characteristics = {
 	.input = { .min = 12000000, .max = 48000000 },
 	.num_output = ARRAY_SIZE(plla_outputs),
 	.output = plla_outputs,
+	.core_output = core_outputs,
 };
 
 static const struct clk_range upll_outputs[] = {
@@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
 	.input = { .min = 12000000, .max = 48000000 },
 	.num_output = ARRAY_SIZE(upll_outputs),
 	.output = upll_outputs,
+	.core_output = core_outputs,
 	.upll = true,
 };
 
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 91b5c6f14819..e6eb5afba93d 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -116,11 +116,17 @@ static const struct clk_range pll_outputs[] = {
 	{ .min = 2343750, .max = 1200000000 },
 };
 
+/* Fractional PLL core output range. */
+static const struct clk_range core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
 /* CPU PLL characteristics. */
 static const struct clk_pll_characteristics cpu_pll_characteristics = {
 	.input = { .min = 12000000, .max = 50000000 },
 	.num_output = ARRAY_SIZE(cpu_pll_outputs),
 	.output = cpu_pll_outputs,
+	.core_output = core_outputs,
 };
 
 /* PLL characteristics. */
@@ -128,6 +134,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
 	.input = { .min = 12000000, .max = 50000000 },
 	.num_output = ARRAY_SIZE(pll_outputs),
 	.output = pll_outputs,
+	.core_output = core_outputs,
 };
 
 /*
-- 
2.25.1

Re: [PATCH v5 09/27] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs

[claudiu beznea]

On 03.07.2024 13:27, Varshini Rajendran wrote:
> SAM9X7 SoC family supports different core output frequencies for
> different PLL IDs. To handle the same in the PLL driver, a separate
> parameter core_output is added. The sam9x60 and sama7g5 SoC PMC drivers
> are aligned to the PLL driver by adding the core output freq range in
> the PLL characteristics configurations.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 12 ++++++------
>  drivers/clk/at91/pmc.h             |  1 +
>  drivers/clk/at91/sam9x60.c         |  7 +++++++
>  drivers/clk/at91/sama7g5.c         |  7 +++++++
>  4 files changed, 21 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index ff65f7b916f0..b0314dfd7393 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -23,9 +23,6 @@
>  #define UPLL_DIV		2
>  #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
>  
> -#define FCORE_MIN		(600000000)
> -#define FCORE_MAX		(1200000000)
> -
>  #define PLL_MAX_ID		7
>  
>  struct sam9x60_pll_core {
> @@ -194,7 +191,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
>  	unsigned long nmul = 0;
>  	unsigned long nfrac = 0;
>  
> -	if (rate < FCORE_MIN || rate > FCORE_MAX)
> +	if (rate < core->characteristics->core_output[0].min ||
> +	    rate > core->characteristics->core_output[0].max)
>  		return -ERANGE;
>  
>  	/*
> @@ -214,7 +212,8 @@ static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
>  	}
>  
>  	/* Check if resulted rate is a valid.  */
> -	if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
> +	if (tmprate < core->characteristics->core_output[0].min ||
> +	    tmprate > core->characteristics->core_output[0].max)
>  		return -ERANGE;
>  
>  	if (update) {
> @@ -669,7 +668,8 @@ sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
>  			goto free;
>  		}
>  
> -		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
> +		ret = sam9x60_frac_pll_compute_mul_frac(&frac->core,
> +							characteristics->core_output[0].min,
>  							parent_rate, true);
>  		if (ret < 0) {
>  			hw = ERR_PTR(ret);
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 0f52e80bcd49..bb9da35198d9 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -75,6 +75,7 @@ struct clk_pll_characteristics {
>  	struct clk_range input;
>  	int num_output;
>  	const struct clk_range *output;
> +	const struct clk_range *core_output;
>  	u16 *icpll;
>  	u8 *out;
>  	u8 upll : 1;
> diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
> index e309cbf3cb9a..db6db9e2073e 100644
> --- a/drivers/clk/at91/sam9x60.c
> +++ b/drivers/clk/at91/sam9x60.c
> @@ -26,10 +26,16 @@ static const struct clk_range plla_outputs[] = {
>  	{ .min = 2343750, .max = 1200000000 },
>  };
>  
> +/* Fractional PLL core output range. */
> +static const struct clk_range core_outputs[] = {
> +	{ .min = 600000000, .max = 1200000000 },
> +};
> +
>  static const struct clk_pll_characteristics plla_characteristics = {
>  	.input = { .min = 12000000, .max = 48000000 },
>  	.num_output = ARRAY_SIZE(plla_outputs),
>  	.output = plla_outputs,
> +	.core_output = core_outputs,
>  };
>  
>  static const struct clk_range upll_outputs[] = {
> @@ -40,6 +46,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
>  	.input = { .min = 12000000, .max = 48000000 },
>  	.num_output = ARRAY_SIZE(upll_outputs),
>  	.output = upll_outputs,
> +	.core_output = core_outputs,
>  	.upll = true,
>  };
>  
> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
> index 91b5c6f14819..e6eb5afba93d 100644
> --- a/drivers/clk/at91/sama7g5.c
> +++ b/drivers/clk/at91/sama7g5.c
> @@ -116,11 +116,17 @@ static const struct clk_range pll_outputs[] = {
>  	{ .min = 2343750, .max = 1200000000 },
>  };
>  
> +/* Fractional PLL core output range. */
> +static const struct clk_range core_outputs[] = {
> +	{ .min = 600000000, .max = 1200000000 },
> +};
> +
>  /* CPU PLL characteristics. */
>  static const struct clk_pll_characteristics cpu_pll_characteristics = {
>  	.input = { .min = 12000000, .max = 50000000 },
>  	.num_output = ARRAY_SIZE(cpu_pll_outputs),
>  	.output = cpu_pll_outputs,
> +	.core_output = core_outputs,
>  };
>  
>  /* PLL characteristics. */
> @@ -128,6 +134,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
>  	.input = { .min = 12000000, .max = 50000000 },
>  	.num_output = ARRAY_SIZE(pll_outputs),
>  	.output = pll_outputs,
> +	.core_output = core_outputs,
>  };
>  
>  /*

[PATCH v5 10/27] clk: at91: sam9x7: add support for HW PLL freq dividers

[Varshini Rajendran]

Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system
PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and
4 respectively, both have a hardware divider /2. This has to be taken into
account in the software to obtain the right frequencies. Support for the
same is added in the PLL driver.

fcorepllack -----> HW Div = 2 -+--> fpllack
                               |
                               +--> HW Div = 2 ---> fplladiv2ck

In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz
after the hardware divider and the plladiv2 freq is 400 MHz after the
hardware divider (given that the DIVPMC is 0).

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Corrected typos in commit message.
- Rewrote the conditional statement.
---
 drivers/clk/at91/clk-sam9x60-pll.c | 30 ++++++++++++++++++++++++++++--
 drivers/clk/at91/pmc.h             |  1 +
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
index b0314dfd7393..fda041102224 100644
--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
 {
 	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 	struct sam9x60_frac *frac = to_sam9x60_frac(core);
+	unsigned long freq;
 
-	return parent_rate * (frac->mul + 1) +
+	freq = parent_rate * (frac->mul + 1) +
 		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
+
+	if (core->layout->div2)
+		freq >>= 1;
+
+	return freq;
 }
 
 static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
@@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
 }
 
+static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
+						       unsigned long parent_rate)
+{
+	return parent_rate >> 1;
+}
+
 static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
 					unsigned long *parent_rate,
 					unsigned long rate)
@@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
 	.restore_context = sam9x60_div_pll_restore_context,
 };
 
+static const struct clk_ops sam9x60_fixed_div_pll_ops = {
+	.prepare = sam9x60_div_pll_prepare,
+	.unprepare = sam9x60_div_pll_unprepare,
+	.is_prepared = sam9x60_div_pll_is_prepared,
+	.recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
+	.round_rate = sam9x60_div_pll_round_rate,
+	.save_context = sam9x60_div_pll_save_context,
+	.restore_context = sam9x60_div_pll_restore_context,
+};
+
 struct clk_hw * __init
 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 			      const char *name, const char *parent_name,
@@ -725,10 +747,14 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 	else
 		init.parent_names = &parent_name;
 	init.num_parents = 1;
-	if (flags & CLK_SET_RATE_GATE)
+
+	if (layout->div2)
+		init.ops = &sam9x60_fixed_div_pll_ops;
+	else if (flags & CLK_SET_RATE_GATE)
 		init.ops = &sam9x60_div_pll_ops;
 	else
 		init.ops = &sam9x60_div_pll_ops_chg;
+
 	init.flags = flags;
 
 	div->core.id = id;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index bb9da35198d9..91d1c6305d95 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -64,6 +64,7 @@ struct clk_pll_layout {
 	u8 frac_shift;
 	u8 div_shift;
 	u8 endiv_shift;
+	u8 div2;
 };
 
 extern const struct clk_pll_layout at91rm9200_pll_layout;
-- 
2.25.1

Re: [PATCH v5 10/27] clk: at91: sam9x7: add support for HW PLL freq dividers

[claudiu beznea]

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Add support for hardware dividers for PLL IDs in sam9x7 SoC. The system
> PLL - PLLA and the system PLL divided by 2 - PLLADIV2 with PLL ID 0 and
> 4 respectively, both have a hardware divider /2. This has to be taken into
> account in the software to obtain the right frequencies. Support for the
> same is added in the PLL driver.
> 
> fcorepllack -----> HW Div = 2 -+--> fpllack
>                                |
>                                +--> HW Div = 2 ---> fplladiv2ck
> 
> In this case the corepll freq is 1600 MHz. So, the plla freq is 800 MHz
> after the hardware divider and the plladiv2 freq is 400 MHz after the
> hardware divider (given that the DIVPMC is 0).
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Corrected typos in commit message.
> - Rewrote the conditional statement.
> ---
>  drivers/clk/at91/clk-sam9x60-pll.c | 30 ++++++++++++++++++++++++++++--
>  drivers/clk/at91/pmc.h             |  1 +
>  2 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index b0314dfd7393..fda041102224 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -73,9 +73,15 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
>  {
>  	struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
>  	struct sam9x60_frac *frac = to_sam9x60_frac(core);
> +	unsigned long freq;
>  
> -	return parent_rate * (frac->mul + 1) +
> +	freq = parent_rate * (frac->mul + 1) +
>  		DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
> +
> +	if (core->layout->div2)
> +		freq >>= 1;
> +
> +	return freq;
>  }
>  
>  static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
> @@ -432,6 +438,12 @@ static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
>  	return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
>  }
>  
> +static unsigned long sam9x60_fixed_div_pll_recalc_rate(struct clk_hw *hw,
> +						       unsigned long parent_rate)
> +{
> +	return parent_rate >> 1;
> +}
> +
>  static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
>  					unsigned long *parent_rate,
>  					unsigned long rate)
> @@ -606,6 +618,16 @@ static const struct clk_ops sam9x60_div_pll_ops_chg = {
>  	.restore_context = sam9x60_div_pll_restore_context,
>  };
>  
> +static const struct clk_ops sam9x60_fixed_div_pll_ops = {
> +	.prepare = sam9x60_div_pll_prepare,
> +	.unprepare = sam9x60_div_pll_unprepare,
> +	.is_prepared = sam9x60_div_pll_is_prepared,
> +	.recalc_rate = sam9x60_fixed_div_pll_recalc_rate,
> +	.round_rate = sam9x60_div_pll_round_rate,
> +	.save_context = sam9x60_div_pll_save_context,
> +	.restore_context = sam9x60_div_pll_restore_context,
> +};
> +
>  struct clk_hw * __init
>  sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
>  			      const char *name, const char *parent_name,
> @@ -725,10 +747,14 @@ sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
>  	else
>  		init.parent_names = &parent_name;
>  	init.num_parents = 1;
> -	if (flags & CLK_SET_RATE_GATE)
> +
> +	if (layout->div2)
> +		init.ops = &sam9x60_fixed_div_pll_ops;
> +	else if (flags & CLK_SET_RATE_GATE)
>  		init.ops = &sam9x60_div_pll_ops;
>  	else
>  		init.ops = &sam9x60_div_pll_ops_chg;
> +
>  	init.flags = flags;
>  
>  	div->core.id = id;
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index bb9da35198d9..91d1c6305d95 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -64,6 +64,7 @@ struct clk_pll_layout {
>  	u8 frac_shift;
>  	u8 div_shift;
>  	u8 endiv_shift;
> +	u8 div2;
>  };
>  
>  extern const struct clk_pll_layout at91rm9200_pll_layout;

[PATCH v5 11/27] clk: at91: sama7g5: move mux table macros to header file

[Varshini Rajendran]

Move the mux table init and fill macro function definitions from the
sama7g5 pmc driver to the pmc.h header file since they will be used
by other SoC's pmc drivers as well like sam9x7.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/pmc.h     | 16 ++++++++++++++++
 drivers/clk/at91/sama7g5.c | 35 ++++++++++-------------------------
 2 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 91d1c6305d95..4fb29ca111f7 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -121,6 +121,22 @@ struct at91_clk_pms {
 
 #define ndck(a, s) (a[s - 1].id + 1)
 #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
+
+#define PMC_INIT_TABLE(_table, _count)			\
+	do {						\
+		u8 _i;					\
+		for (_i = 0; _i < (_count); _i++)	\
+			(_table)[_i] = _i;		\
+	} while (0)
+
+#define PMC_FILL_TABLE(_to, _from, _count)		\
+	do {						\
+		u8 _i;					\
+		for (_i = 0; _i < (_count); _i++) {	\
+			(_to)[_i] = (_from)[_i];	\
+		}					\
+	} while (0)
+
 struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
 				   unsigned int nperiph, unsigned int ngck,
 				   unsigned int npck);
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index e6eb5afba93d..6706d1305baa 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -16,21 +16,6 @@
 
 #include "pmc.h"
 
-#define SAMA7G5_INIT_TABLE(_table, _count)		\
-	do {						\
-		u8 _i;					\
-		for (_i = 0; _i < (_count); _i++)	\
-			(_table)[_i] = _i;		\
-	} while (0)
-
-#define SAMA7G5_FILL_TABLE(_to, _from, _count)		\
-	do {						\
-		u8 _i;					\
-		for (_i = 0; _i < (_count); _i++) {	\
-			(_to)[_i] = (_from)[_i];	\
-		}					\
-	} while (0)
-
 static DEFINE_SPINLOCK(pmc_pll_lock);
 static DEFINE_SPINLOCK(pmc_mck0_lock);
 static DEFINE_SPINLOCK(pmc_mckX_lock);
@@ -1119,17 +1104,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 		if (!mux_table)
 			goto err_free;
 
-		SAMA7G5_INIT_TABLE(mux_table, 3);
-		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
-				   sama7g5_mckx[i].ep_count);
+		PMC_INIT_TABLE(mux_table, 3);
+		PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
+			       sama7g5_mckx[i].ep_count);
 		for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
 			u8 pll_id = sama7g5_mckx[i].ep[j].pll_id;
 			u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid;
 
 			tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
 		}
-		SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
-				   sama7g5_mckx[i].ep_count);
+		PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
+			       sama7g5_mckx[i].ep_count);
 
 		hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
 				   num_parents, NULL, parent_hws, mux_table,
@@ -1215,17 +1200,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
 		if (!mux_table)
 			goto err_free;
 
-		SAMA7G5_INIT_TABLE(mux_table, 3);
-		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
-				   sama7g5_gck[i].pp_count);
+		PMC_INIT_TABLE(mux_table, 3);
+		PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
+			       sama7g5_gck[i].pp_count);
 		for (j = 0; j < sama7g5_gck[i].pp_count; j++) {
 			u8 pll_id = sama7g5_gck[i].pp[j].pll_id;
 			u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid;
 
 			tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
 		}
-		SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
-				   sama7g5_gck[i].pp_count);
+		PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
+			       sama7g5_gck[i].pp_count);
 
 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
 						 &sama7g5_pcr_layout,
-- 
2.25.1

Re: [PATCH v5 11/27] clk: at91: sama7g5: move mux table macros to header file

[claudiu beznea]

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Move the mux table init and fill macro function definitions from the
> sama7g5 pmc driver to the pmc.h header file since they will be used
> by other SoC's pmc drivers as well like sam9x7.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
>  drivers/clk/at91/pmc.h     | 16 ++++++++++++++++
>  drivers/clk/at91/sama7g5.c | 35 ++++++++++-------------------------
>  2 files changed, 26 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
> index 91d1c6305d95..4fb29ca111f7 100644
> --- a/drivers/clk/at91/pmc.h
> +++ b/drivers/clk/at91/pmc.h
> @@ -121,6 +121,22 @@ struct at91_clk_pms {
>  
>  #define ndck(a, s) (a[s - 1].id + 1)
>  #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
> +
> +#define PMC_INIT_TABLE(_table, _count)			\
> +	do {						\
> +		u8 _i;					\
> +		for (_i = 0; _i < (_count); _i++)	\
> +			(_table)[_i] = _i;		\
> +	} while (0)
> +
> +#define PMC_FILL_TABLE(_to, _from, _count)		\
> +	do {						\
> +		u8 _i;					\
> +		for (_i = 0; _i < (_count); _i++) {	\
> +			(_to)[_i] = (_from)[_i];	\
> +		}					\
> +	} while (0)
> +
>  struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
>  				   unsigned int nperiph, unsigned int ngck,
>  				   unsigned int npck);
> diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
> index e6eb5afba93d..6706d1305baa 100644
> --- a/drivers/clk/at91/sama7g5.c
> +++ b/drivers/clk/at91/sama7g5.c
> @@ -16,21 +16,6 @@
>  
>  #include "pmc.h"
>  
> -#define SAMA7G5_INIT_TABLE(_table, _count)		\
> -	do {						\
> -		u8 _i;					\
> -		for (_i = 0; _i < (_count); _i++)	\
> -			(_table)[_i] = _i;		\
> -	} while (0)
> -
> -#define SAMA7G5_FILL_TABLE(_to, _from, _count)		\
> -	do {						\
> -		u8 _i;					\
> -		for (_i = 0; _i < (_count); _i++) {	\
> -			(_to)[_i] = (_from)[_i];	\
> -		}					\
> -	} while (0)
> -
>  static DEFINE_SPINLOCK(pmc_pll_lock);
>  static DEFINE_SPINLOCK(pmc_mck0_lock);
>  static DEFINE_SPINLOCK(pmc_mckX_lock);
> @@ -1119,17 +1104,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
>  		if (!mux_table)
>  			goto err_free;
>  
> -		SAMA7G5_INIT_TABLE(mux_table, 3);
> -		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
> -				   sama7g5_mckx[i].ep_count);
> +		PMC_INIT_TABLE(mux_table, 3);
> +		PMC_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table,
> +			       sama7g5_mckx[i].ep_count);
>  		for (j = 0; j < sama7g5_mckx[i].ep_count; j++) {
>  			u8 pll_id = sama7g5_mckx[i].ep[j].pll_id;
>  			u8 pll_compid = sama7g5_mckx[i].ep[j].pll_compid;
>  
>  			tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
>  		}
> -		SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
> -				   sama7g5_mckx[i].ep_count);
> +		PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
> +			       sama7g5_mckx[i].ep_count);
>  
>  		hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
>  				   num_parents, NULL, parent_hws, mux_table,
> @@ -1215,17 +1200,17 @@ static void __init sama7g5_pmc_setup(struct device_node *np)
>  		if (!mux_table)
>  			goto err_free;
>  
> -		SAMA7G5_INIT_TABLE(mux_table, 3);
> -		SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
> -				   sama7g5_gck[i].pp_count);
> +		PMC_INIT_TABLE(mux_table, 3);
> +		PMC_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table,
> +			       sama7g5_gck[i].pp_count);
>  		for (j = 0; j < sama7g5_gck[i].pp_count; j++) {
>  			u8 pll_id = sama7g5_gck[i].pp[j].pll_id;
>  			u8 pll_compid = sama7g5_gck[i].pp[j].pll_compid;
>  
>  			tmp_parent_hws[j] = sama7g5_plls[pll_id][pll_compid].hw;
>  		}
> -		SAMA7G5_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
> -				   sama7g5_gck[i].pp_count);
> +		PMC_FILL_TABLE(&parent_hws[3], tmp_parent_hws,
> +			       sama7g5_gck[i].pp_count);
>  
>  		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
>  						 &sama7g5_pcr_layout,

[PATCH v5 12/27] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT

[Varshini Rajendran]

Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
clock from phandle in DT for sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v5:
- Updated Acked-by tag.
---
 include/dt-bindings/clock/at91.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
index 3e3972a814c1..6ede88c3992d 100644
--- a/include/dt-bindings/clock/at91.h
+++ b/include/dt-bindings/clock/at91.h
@@ -38,6 +38,10 @@
 #define PMC_CPU			(PMC_MAIN + 9)
 #define PMC_MCK1		(PMC_MAIN + 10)
 
+/* SAM9X7 */
+#define PMC_PLLADIV2		(PMC_MAIN + 11)
+#define PMC_LVDSPLL		(PMC_MAIN + 12)
+
 #ifndef AT91_PMC_MOSCS
 #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
 #define AT91_PMC_LOCKA		1		/* PLLA Lock */
-- 
2.25.1

Re: [PATCH v5 12/27] dt-bindings: clock: at91: Allow PLLs to be exported and referenced in DT

[claudiu beznea]

On 03.07.2024 13:27, Varshini Rajendran wrote:
> Allow PLLADIV2 and LVDSPLL to be referenced as a PMC_TYPE_CORE
> clock from phandle in DT for sam9x7 SoC family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Updated Acked-by tag.
> ---
>  include/dt-bindings/clock/at91.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h
> index 3e3972a814c1..6ede88c3992d 100644
> --- a/include/dt-bindings/clock/at91.h
> +++ b/include/dt-bindings/clock/at91.h
> @@ -38,6 +38,10 @@
>  #define PMC_CPU			(PMC_MAIN + 9)
>  #define PMC_MCK1		(PMC_MAIN + 10)
>  
> +/* SAM9X7 */
> +#define PMC_PLLADIV2		(PMC_MAIN + 11)
> +#define PMC_LVDSPLL		(PMC_MAIN + 12)
> +
>  #ifndef AT91_PMC_MOSCS
>  #define AT91_PMC_MOSCS		0		/* MOSCS Flag */
>  #define AT91_PMC_LOCKA		1		/* PLLA Lock */

[PATCH v5 13/27] clk: at91: sam9x7: add sam9x7 pmc driver

[Varshini Rajendran]

Add a driver for the PMC clocks of sam9x7 Soc family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 drivers/clk/at91/Makefile |   1 +
 drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 947 insertions(+)
 create mode 100644 drivers/clk/at91/sam9x7.c

diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 89061b85e7d2..8e3684ba2c74 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
 obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
 obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
 obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
+obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
 obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
 obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
 obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
new file mode 100644
index 000000000000..b031280bbb32
--- /dev/null
+++ b/drivers/clk/at91/sam9x7.c
@@ -0,0 +1,946 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SAM9X7 PMC code.
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+static DEFINE_SPINLOCK(pmc_pll_lock);
+static DEFINE_SPINLOCK(mck_lock);
+
+/**
+ * enum pll_ids - PLL clocks identifiers
+ * @PLL_ID_PLLA:	PLLA identifier
+ * @PLL_ID_UPLL:	UPLL identifier
+ * @PLL_ID_AUDIO:	Audio PLL identifier
+ * @PLL_ID_LVDS:	LVDS PLL identifier
+ * @PLL_ID_PLLA_DIV2:	PLLA DIV2 identifier
+ * @PLL_ID_MAX:		Max PLL Identifier
+ */
+enum pll_ids {
+	PLL_ID_PLLA,
+	PLL_ID_UPLL,
+	PLL_ID_AUDIO,
+	PLL_ID_LVDS,
+	PLL_ID_PLLA_DIV2,
+	PLL_ID_MAX,
+};
+
+/**
+ * enum pll_type - PLL type identifiers
+ * @PLL_TYPE_FRAC:	fractional PLL identifier
+ * @PLL_TYPE_DIV:	divider PLL identifier
+ */
+enum pll_type {
+	PLL_TYPE_FRAC,
+	PLL_TYPE_DIV,
+};
+
+static const struct clk_master_characteristics mck_characteristics = {
+	.output = { .min = 32000000, .max = 266666667 },
+	.divisors = { 1, 2, 4, 3, 5},
+	.have_div3_pres = 1,
+};
+
+static const struct clk_master_layout sam9x7_master_layout = {
+	.mask = 0x373,
+	.pres_shift = 4,
+	.offset = 0x28,
+};
+
+/* Fractional PLL core output range. */
+static const struct clk_range plla_core_outputs[] = {
+	{ .min = 375000000, .max = 1600000000 },
+};
+
+static const struct clk_range upll_core_outputs[] = {
+	{ .min = 600000000, .max = 1200000000 },
+};
+
+static const struct clk_range lvdspll_core_outputs[] = {
+	{ .min = 400000000, .max = 800000000 },
+};
+
+static const struct clk_range audiopll_core_outputs[] = {
+	{ .min = 400000000, .max = 800000000 },
+};
+
+static const struct clk_range plladiv2_core_outputs[] = {
+	{ .min = 375000000, .max = 1600000000 },
+};
+
+/* Fractional PLL output range. */
+static const struct clk_range plla_outputs[] = {
+	{ .min = 732421, .max = 800000000 },
+};
+
+static const struct clk_range upll_outputs[] = {
+	{ .min = 300000000, .max = 600000000 },
+};
+
+static const struct clk_range lvdspll_outputs[] = {
+	{ .min = 10000000, .max = 800000000 },
+};
+
+static const struct clk_range audiopll_outputs[] = {
+	{ .min = 10000000, .max = 800000000 },
+};
+
+static const struct clk_range plladiv2_outputs[] = {
+	{ .min = 366210, .max = 400000000 },
+};
+
+/* PLL characteristics. */
+static const struct clk_pll_characteristics plla_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(plla_outputs),
+	.output = plla_outputs,
+	.core_output = plla_core_outputs,
+};
+
+static const struct clk_pll_characteristics upll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(upll_outputs),
+	.output = upll_outputs,
+	.core_output = upll_core_outputs,
+	.upll = true,
+};
+
+static const struct clk_pll_characteristics lvdspll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(lvdspll_outputs),
+	.output = lvdspll_outputs,
+	.core_output = lvdspll_core_outputs,
+};
+
+static const struct clk_pll_characteristics audiopll_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(audiopll_outputs),
+	.output = audiopll_outputs,
+	.core_output = audiopll_core_outputs,
+};
+
+static const struct clk_pll_characteristics plladiv2_characteristics = {
+	.input = { .min = 20000000, .max = 50000000 },
+	.num_output = ARRAY_SIZE(plladiv2_outputs),
+	.output = plladiv2_outputs,
+	.core_output = plladiv2_core_outputs,
+};
+
+/* Layout for fractional PLL ID PLLA. */
+static const struct clk_pll_layout plla_frac_layout = {
+	.mul_mask = GENMASK(31, 24),
+	.frac_mask = GENMASK(21, 0),
+	.mul_shift = 24,
+	.frac_shift = 0,
+	.div2 = 1,
+};
+
+/* Layout for fractional PLLs. */
+static const struct clk_pll_layout pll_frac_layout = {
+	.mul_mask = GENMASK(31, 24),
+	.frac_mask = GENMASK(21, 0),
+	.mul_shift = 24,
+	.frac_shift = 0,
+};
+
+/* Layout for DIV PLLs. */
+static const struct clk_pll_layout pll_divpmc_layout = {
+	.div_mask = GENMASK(7, 0),
+	.endiv_mask = BIT(29),
+	.div_shift = 0,
+	.endiv_shift = 29,
+};
+
+/* Layout for DIV PLL ID PLLADIV2. */
+static const struct clk_pll_layout plladiv2_divpmc_layout = {
+	.div_mask = GENMASK(7, 0),
+	.endiv_mask = BIT(29),
+	.div_shift = 0,
+	.endiv_shift = 29,
+	.div2 = 1,
+};
+
+/* Layout for DIVIO dividers. */
+static const struct clk_pll_layout pll_divio_layout = {
+	.div_mask	= GENMASK(19, 12),
+	.endiv_mask	= BIT(30),
+	.div_shift	= 12,
+	.endiv_shift	= 30,
+};
+
+/*
+ * PLL clocks description
+ * @n:		clock name
+ * @p:		clock parent
+ * @l:		clock layout
+ * @t:		clock type
+ * @c:		pll characteristics
+ * @f:		clock flags
+ * @eid:	export index in sam9x7->chws[] array
+ */
+static const struct {
+	const char *n;
+	const char *p;
+	const struct clk_pll_layout *l;
+	u8 t;
+	const struct clk_pll_characteristics *c;
+	unsigned long f;
+	u8 eid;
+} sam9x7_plls[][PLL_ID_MAX] = {
+	[PLL_ID_PLLA] = {
+		{
+			.n = "plla_fracck",
+			.p = "mainck",
+			.l = &plla_frac_layout,
+			.t = PLL_TYPE_FRAC,
+			/*
+			 * This feeds plla_divpmcck which feeds CPU. It should
+			 * not be disabled.
+			 */
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.c = &plla_characteristics,
+		},
+
+		{
+			.n = "plla_divpmcck",
+			.p = "plla_fracck",
+			.l = &pll_divpmc_layout,
+			.t = PLL_TYPE_DIV,
+			/* This feeds CPU. It should not be disabled */
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.eid = PMC_PLLACK,
+			.c = &plla_characteristics,
+		},
+	},
+
+	[PLL_ID_UPLL] = {
+		{
+			.n = "upll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.t = PLL_TYPE_FRAC,
+			.f = CLK_SET_RATE_GATE,
+			.c = &upll_characteristics,
+		},
+
+		{
+			.n = "upll_divpmcck",
+			.p = "upll_fracck",
+			.l = &pll_divpmc_layout,
+			.t = PLL_TYPE_DIV,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.eid = PMC_UTMI,
+			.c = &upll_characteristics,
+		},
+	},
+
+	[PLL_ID_AUDIO] = {
+		{
+			.n = "audiopll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.f = CLK_SET_RATE_GATE,
+			.c = &audiopll_characteristics,
+			.t = PLL_TYPE_FRAC,
+		},
+
+		{
+			.n = "audiopll_divpmcck",
+			.p = "audiopll_fracck",
+			.l = &pll_divpmc_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &audiopll_characteristics,
+			.eid = PMC_AUDIOPMCPLL,
+			.t = PLL_TYPE_DIV,
+		},
+
+		{
+			.n = "audiopll_diviock",
+			.p = "audiopll_fracck",
+			.l = &pll_divio_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &audiopll_characteristics,
+			.eid = PMC_AUDIOIOPLL,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+
+	[PLL_ID_LVDS] = {
+		{
+			.n = "lvdspll_fracck",
+			.p = "main_osc",
+			.l = &pll_frac_layout,
+			.f = CLK_SET_RATE_GATE,
+			.c = &lvdspll_characteristics,
+			.t = PLL_TYPE_FRAC,
+		},
+
+		{
+			.n = "lvdspll_divpmcck",
+			.p = "lvdspll_fracck",
+			.l = &pll_divpmc_layout,
+			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+			     CLK_SET_RATE_PARENT,
+			.c = &lvdspll_characteristics,
+			.eid = PMC_LVDSPLL,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+
+	[PLL_ID_PLLA_DIV2] = {
+		{
+			.n = "plla_div2pmcck",
+			.p = "plla_fracck",
+			.l = &plladiv2_divpmc_layout,
+			/*
+			 * This may feed critical parts of the system like timers.
+			 * It should not be disabled.
+			 */
+			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+			.c = &plladiv2_characteristics,
+			.eid = PMC_PLLADIV2,
+			.t = PLL_TYPE_DIV,
+		},
+	},
+};
+
+static const struct clk_programmable_layout sam9x7_programmable_layout = {
+	.pres_mask = 0xff,
+	.pres_shift = 8,
+	.css_mask = 0x1f,
+	.have_slck_mck = 0,
+	.is_pres_direct = 1,
+};
+
+static const struct clk_pcr_layout sam9x7_pcr_layout = {
+	.offset = 0x88,
+	.cmd = BIT(31),
+	.gckcss_mask = GENMASK(12, 8),
+	.pid_mask = GENMASK(6, 0),
+};
+
+static const struct {
+	char *n;
+	char *p;
+	u8 id;
+	unsigned long flags;
+} sam9x7_systemck[] = {
+	/*
+	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
+	 * to keep it enabled in case there is no Linux consumer for it.
+	 */
+	{ .n = "ddrck",		.p = "masterck_div",	.id = 2,	.flags = CLK_IS_CRITICAL },
+	{ .n = "uhpck",		.p = "usbck",		.id = 6 },
+	{ .n = "pck0",		.p = "prog0",		.id = 8 },
+	{ .n = "pck1",		.p = "prog1",		.id = 9 },
+};
+
+/*
+ * Peripheral clocks description
+ * @n:		clock name
+ * @f:		clock flags
+ * @id:		peripheral id
+ */
+static const struct {
+	char *n;
+	unsigned long f;
+	u8 id;
+} sam9x7_periphck[] = {
+	{ .n = "pioA_clk",	.id = 2, },
+	{ .n = "pioB_clk",	.id = 3, },
+	{ .n = "pioC_clk",	.id = 4, },
+	{ .n = "flex0_clk",	.id = 5, },
+	{ .n = "flex1_clk",	.id = 6, },
+	{ .n = "flex2_clk",	.id = 7, },
+	{ .n = "flex3_clk",	.id = 8, },
+	{ .n = "flex6_clk",	.id = 9, },
+	{ .n = "flex7_clk",	.id = 10, },
+	{ .n = "flex8_clk",	.id = 11, },
+	{ .n = "sdmmc0_clk",	.id = 12, },
+	{ .n = "flex4_clk",	.id = 13, },
+	{ .n = "flex5_clk",	.id = 14, },
+	{ .n = "flex9_clk",	.id = 15, },
+	{ .n = "flex10_clk",	.id = 16, },
+	{ .n = "tcb0_clk",	.id = 17, },
+	{ .n = "pwm_clk",	.id = 18, },
+	{ .n = "adc_clk",	.id = 19, },
+	{ .n = "dma0_clk",	.id = 20, },
+	{ .n = "uhphs_clk",	.id = 22, },
+	{ .n = "udphs_clk",	.id = 23, },
+	{ .n = "macb0_clk",	.id = 24, },
+	{ .n = "lcd_clk",	.id = 25, },
+	{ .n = "sdmmc1_clk",	.id = 26, },
+	{ .n = "ssc_clk",	.id = 28, },
+	{ .n = "can0_clk",	.id = 29, },
+	{ .n = "can1_clk",	.id = 30, },
+	{ .n = "flex11_clk",	.id = 32, },
+	{ .n = "flex12_clk",	.id = 33, },
+	{ .n = "i2s_clk",	.id = 34, },
+	{ .n = "qspi_clk",	.id = 35, },
+	{ .n = "gfx2d_clk",	.id = 36, },
+	{ .n = "pit64b0_clk",	.id = 37, },
+	{ .n = "trng_clk",	.id = 38, },
+	{ .n = "aes_clk",	.id = 39, },
+	{ .n = "tdes_clk",	.id = 40, },
+	{ .n = "sha_clk",	.id = 41, },
+	{ .n = "classd_clk",	.id = 42, },
+	{ .n = "isi_clk",	.id = 43, },
+	{ .n = "pioD_clk",	.id = 44, },
+	{ .n = "tcb1_clk",	.id = 45, },
+	{ .n = "dbgu_clk",	.id = 47, },
+	/*
+	 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
+	 * need to keep it enabled in case there is no Linux consumer for it.
+	 */
+	{ .n = "mpddr_clk",	.id = 49,	.f = CLK_IS_CRITICAL },
+	{ .n = "csi2dc_clk",	.id = 52, },
+	{ .n = "csi4l_clk",	.id = 53, },
+	{ .n = "dsi4l_clk",	.id = 54, },
+	{ .n = "lvdsc_clk",	.id = 56, },
+	{ .n = "pit64b1_clk",	.id = 58, },
+	{ .n = "puf_clk",	.id = 59, },
+	{ .n = "gmactsu_clk",	.id = 67, },
+};
+
+/*
+ * Generic clock description
+ * @n:			clock name
+ * @pp:			PLL parents
+ * @pp_mux_table:	PLL parents mux table
+ * @r:			clock output range
+ * @pp_chg_id:		id in parent array of changeable PLL parent
+ * @pp_count:		PLL parents count
+ * @id:			clock id
+ */
+static const struct {
+	const char *n;
+	const char *pp[8];
+	const char pp_mux_table[8];
+	struct clk_range r;
+	int pp_chg_id;
+	u8 pp_count;
+	u8 id;
+} sam9x7_gck[] = {
+	{
+		.n = "flex0_gclk",
+		.id = 5,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex1_gclk",
+		.id = 6,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex2_gclk",
+		.id = 7,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex3_gclk",
+		.id = 8,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex6_gclk",
+		.id = 9,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex7_gclk",
+		.id = 10,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex8_gclk",
+		.id = 11,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "sdmmc0_gclk",
+		.id = 12,
+		.r = { .max = 105000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex4_gclk",
+		.id = 13,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex5_gclk",
+		.id = 14,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex9_gclk",
+		.id = 15,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex10_gclk",
+		.id = 16,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "tcb0_gclk",
+		.id = 17,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "adc_gclk",
+		.id = 19,
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "lcd_gclk",
+		.id = 25,
+		.r = { .max = 75000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "sdmmc1_gclk",
+		.id = 26,
+		.r = { .max = 105000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mcan0_gclk",
+		.id = 29,
+		.r = { .max = 80000000 },
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mcan1_gclk",
+		.id = 30,
+		.r = { .max = 80000000 },
+		.pp = { "upll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 5, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex11_gclk",
+		.id = 32,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "flex12_gclk",
+		.id = 33,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "i2s_gclk",
+		.id = 34,
+		.r = { .max = 100000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "qspi_gclk",
+		.id = 35,
+		.r = { .max = 200000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "pit64b0_gclk",
+		.id = 37,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "classd_gclk",
+		.id = 42,
+		.r = { .max = 100000000 },
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "tcb1_gclk",
+		.id = 45,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "dbgu_gclk",
+		.id = 47,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "mipiphy_gclk",
+		.id = 55,
+		.r = { .max = 27000000 },
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "pit64b1_gclk",
+		.id = 58,
+		.pp = { "plla_div2pmcck", },
+		.pp_mux_table = { 8, },
+		.pp_count = 1,
+		.pp_chg_id = INT_MIN,
+	},
+
+	{
+		.n = "gmac_gclk",
+		.id = 67,
+		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
+		.pp_mux_table = { 6, 8, },
+		.pp_count = 2,
+		.pp_chg_id = INT_MIN,
+	},
+};
+
+static void __init sam9x7_pmc_setup(struct device_node *np)
+{
+	struct clk_range range = CLK_RANGE(0, 0);
+	const char *td_slck_name, *md_slck_name, *mainxtal_name;
+	struct pmc_data *sam9x7_pmc;
+	const char *parent_names[9];
+	void **clk_mux_buffer = NULL;
+	int clk_mux_buffer_size = 0;
+	struct clk_hw *main_osc_hw;
+	struct regmap *regmap;
+	struct clk_hw *hw;
+	int i, j;
+
+	i = of_property_match_string(np, "clock-names", "td_slck");
+	if (i < 0)
+		return;
+
+	td_slck_name = of_clk_get_parent_name(np, i);
+
+	i = of_property_match_string(np, "clock-names", "md_slck");
+	if (i < 0)
+		return;
+
+	md_slck_name = of_clk_get_parent_name(np, i);
+
+	i = of_property_match_string(np, "clock-names", "main_xtal");
+	if (i < 0)
+		return;
+	mainxtal_name = of_clk_get_parent_name(np, i);
+
+	regmap = device_node_to_regmap(np);
+	if (IS_ERR(regmap))
+		return;
+
+	sam9x7_pmc = pmc_data_allocate(PMC_LVDSPLL + 1,
+				       nck(sam9x7_systemck),
+				       nck(sam9x7_periphck),
+				       nck(sam9x7_gck), 8);
+	if (!sam9x7_pmc)
+		return;
+
+	clk_mux_buffer = kmalloc(sizeof(void *) *
+				 (ARRAY_SIZE(sam9x7_gck)),
+				 GFP_KERNEL);
+	if (!clk_mux_buffer)
+		goto err_free;
+
+	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
+					   50000000);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);
+	if (IS_ERR(hw))
+		goto err_free;
+	main_osc_hw = hw;
+
+	parent_names[0] = "main_rc_osc";
+	parent_names[1] = "main_osc";
+	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	sam9x7_pmc->chws[PMC_MAIN] = hw;
+
+	for (i = 0; i < PLL_ID_MAX; i++) {
+		for (j = 0; j < 3; j++) {
+			struct clk_hw *parent_hw;
+
+			if (!sam9x7_plls[i][j].n)
+				continue;
+
+			switch (sam9x7_plls[i][j].t) {
+			case PLL_TYPE_FRAC:
+				if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
+					parent_hw = sam9x7_pmc->chws[PMC_MAIN];
+				else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
+					parent_hw = main_osc_hw;
+				else
+					parent_hw = __clk_get_hw(of_clk_get_by_name
+								 (np, sam9x7_plls[i][j].p));
+
+				hw = sam9x60_clk_register_frac_pll(regmap,
+								   &pmc_pll_lock,
+								   sam9x7_plls[i][j].n,
+								   sam9x7_plls[i][j].p,
+								   parent_hw, i,
+								   sam9x7_plls[i][j].c,
+								   sam9x7_plls[i][j].l,
+								   sam9x7_plls[i][j].f);
+				break;
+
+			case PLL_TYPE_DIV:
+				hw = sam9x60_clk_register_div_pll(regmap,
+								  &pmc_pll_lock,
+								  sam9x7_plls[i][j].n,
+								  sam9x7_plls[i][j].p, NULL, i,
+								  sam9x7_plls[i][j].c,
+								  sam9x7_plls[i][j].l,
+								  sam9x7_plls[i][j].f, 0);
+				break;
+
+			default:
+				continue;
+			}
+
+			if (IS_ERR(hw))
+				goto err_free;
+
+			if (sam9x7_plls[i][j].eid)
+				sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
+		}
+	}
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = "mainck";
+	parent_names[2] = "plla_divpmcck";
+	parent_names[3] = "upll_divpmcck";
+	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
+					   parent_names, NULL, &sam9x7_master_layout,
+					   &mck_characteristics, &mck_lock);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	hw = at91_clk_register_master_div(regmap, "masterck_div",
+					  "masterck_pres", NULL, &sam9x7_master_layout,
+					  &mck_characteristics, &mck_lock,
+					  CLK_SET_RATE_GATE, 0);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	sam9x7_pmc->chws[PMC_MCK] = hw;
+
+	parent_names[0] = "plla_divpmcck";
+	parent_names[1] = "upll_divpmcck";
+	parent_names[2] = "main_osc";
+	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
+	if (IS_ERR(hw))
+		goto err_free;
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = td_slck_name;
+	parent_names[2] = "mainck";
+	parent_names[3] = "masterck_div";
+	parent_names[4] = "plla_divpmcck";
+	parent_names[5] = "upll_divpmcck";
+	parent_names[6] = "audiopll_divpmcck";
+	for (i = 0; i < 2; i++) {
+		char name[6];
+
+		snprintf(name, sizeof(name), "prog%d", i);
+
+		hw = at91_clk_register_programmable(regmap, name,
+						    parent_names, NULL, 7, i,
+						    &sam9x7_programmable_layout,
+						    NULL);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->pchws[i] = hw;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
+		hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
+					      sam9x7_systemck[i].p, NULL,
+					      sam9x7_systemck[i].id,
+					      sam9x7_systemck[i].flags);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
+		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
+							 &sam9x7_pcr_layout,
+							 sam9x7_periphck[i].n,
+							 "masterck_div", NULL,
+							 sam9x7_periphck[i].id,
+							 &range, INT_MIN,
+							 sam9x7_periphck[i].f);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
+	}
+
+	parent_names[0] = md_slck_name;
+	parent_names[1] = td_slck_name;
+	parent_names[2] = "mainck";
+	parent_names[3] = "masterck_div";
+	for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
+		u8 num_parents = 4 + sam9x7_gck[i].pp_count;
+		u32 *mux_table;
+
+		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
+					  GFP_KERNEL);
+		if (!mux_table)
+			goto err_free;
+
+		PMC_INIT_TABLE(mux_table, 4);
+		PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
+			       sam9x7_gck[i].pp_count);
+		PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
+			       sam9x7_gck[i].pp_count);
+
+		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
+						 &sam9x7_pcr_layout,
+						 sam9x7_gck[i].n,
+						 parent_names, NULL, mux_table,
+						 num_parents,
+						 sam9x7_gck[i].id,
+						 &sam9x7_gck[i].r,
+						 sam9x7_gck[i].pp_chg_id);
+		if (IS_ERR(hw))
+			goto err_free;
+
+		sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
+		clk_mux_buffer[clk_mux_buffer_size++] = mux_table;
+	}
+
+	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
+	kfree(clk_mux_buffer);
+
+	return;
+
+err_free:
+	if (clk_mux_buffer) {
+		for (i = 0; i < clk_mux_buffer_size; i++)
+			kfree(clk_mux_buffer[i]);
+		kfree(clk_mux_buffer);
+	}
+	kfree(sam9x7_pmc);
+}
+
+/* Some clks are used for a clocksource */
+CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);
-- 
2.25.1

Re: [PATCH v5 13/27] clk: at91: sam9x7: add sam9x7 pmc driver

[claudiu beznea]

Hi, Varshini,

On 03.07.2024 13:28, Varshini Rajendran wrote:
> Add a driver for the PMC clocks of sam9x7 Soc family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
>  drivers/clk/at91/Makefile |   1 +
>  drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>  2 files changed, 947 insertions(+)
>  create mode 100644 drivers/clk/at91/sam9x7.c
> 
> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
> index 89061b85e7d2..8e3684ba2c74 100644
> --- a/drivers/clk/at91/Makefile
> +++ b/drivers/clk/at91/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
>  obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
>  obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
>  obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
> +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
>  obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
>  obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
>  obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
> new file mode 100644
> index 000000000000..b031280bbb32
> --- /dev/null
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -0,0 +1,946 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SAM9X7 PMC code.
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + *
> + */
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/clock/at91.h>
> +
> +#include "pmc.h"
> +
> +static DEFINE_SPINLOCK(pmc_pll_lock);
> +static DEFINE_SPINLOCK(mck_lock);
> +
> +/**
> + * enum pll_ids - PLL clocks identifiers
> + * @PLL_ID_PLLA:	PLLA identifier
> + * @PLL_ID_UPLL:	UPLL identifier
> + * @PLL_ID_AUDIO:	Audio PLL identifier
> + * @PLL_ID_LVDS:	LVDS PLL identifier
> + * @PLL_ID_PLLA_DIV2:	PLLA DIV2 identifier
> + * @PLL_ID_MAX:		Max PLL Identifier
> + */
> +enum pll_ids {
> +	PLL_ID_PLLA,
> +	PLL_ID_UPLL,
> +	PLL_ID_AUDIO,
> +	PLL_ID_LVDS,
> +	PLL_ID_PLLA_DIV2,
> +	PLL_ID_MAX,
> +};
> +
> +/**
> + * enum pll_type - PLL type identifiers
> + * @PLL_TYPE_FRAC:	fractional PLL identifier
> + * @PLL_TYPE_DIV:	divider PLL identifier
> + */
> +enum pll_type {
> +	PLL_TYPE_FRAC,
> +	PLL_TYPE_DIV,
> +};
> +
> +static const struct clk_master_characteristics mck_characteristics = {
> +	.output = { .min = 32000000, .max = 266666667 },
> +	.divisors = { 1, 2, 4, 3, 5},
> +	.have_div3_pres = 1,
> +};
> +
> +static const struct clk_master_layout sam9x7_master_layout = {
> +	.mask = 0x373,
> +	.pres_shift = 4,
> +	.offset = 0x28,
> +};
> +
> +/* Fractional PLL core output range. */
> +static const struct clk_range plla_core_outputs[] = {
> +	{ .min = 375000000, .max = 1600000000 },
> +};
> +
> +static const struct clk_range upll_core_outputs[] = {
> +	{ .min = 600000000, .max = 1200000000 },
> +};
> +
> +static const struct clk_range lvdspll_core_outputs[] = {
> +	{ .min = 400000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range audiopll_core_outputs[] = {
> +	{ .min = 400000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range plladiv2_core_outputs[] = {
> +	{ .min = 375000000, .max = 1600000000 },
> +};
> +
> +/* Fractional PLL output range. */
> +static const struct clk_range plla_outputs[] = {
> +	{ .min = 732421, .max = 800000000 },
> +};
> +
> +static const struct clk_range upll_outputs[] = {
> +	{ .min = 300000000, .max = 600000000 },
> +};
> +
> +static const struct clk_range lvdspll_outputs[] = {
> +	{ .min = 10000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range audiopll_outputs[] = {
> +	{ .min = 10000000, .max = 800000000 },
> +};
> +
> +static const struct clk_range plladiv2_outputs[] = {
> +	{ .min = 366210, .max = 400000000 },
> +};
> +
> +/* PLL characteristics. */
> +static const struct clk_pll_characteristics plla_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(plla_outputs),
> +	.output = plla_outputs,
> +	.core_output = plla_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics upll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(upll_outputs),
> +	.output = upll_outputs,
> +	.core_output = upll_core_outputs,
> +	.upll = true,
> +};
> +
> +static const struct clk_pll_characteristics lvdspll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(lvdspll_outputs),
> +	.output = lvdspll_outputs,
> +	.core_output = lvdspll_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics audiopll_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(audiopll_outputs),
> +	.output = audiopll_outputs,
> +	.core_output = audiopll_core_outputs,
> +};
> +
> +static const struct clk_pll_characteristics plladiv2_characteristics = {
> +	.input = { .min = 20000000, .max = 50000000 },
> +	.num_output = ARRAY_SIZE(plladiv2_outputs),
> +	.output = plladiv2_outputs,
> +	.core_output = plladiv2_core_outputs,
> +};
> +
> +/* Layout for fractional PLL ID PLLA. */
> +static const struct clk_pll_layout plla_frac_layout = {
> +	.mul_mask = GENMASK(31, 24),
> +	.frac_mask = GENMASK(21, 0),
> +	.mul_shift = 24,
> +	.frac_shift = 0,
> +	.div2 = 1,
> +};
> +
> +/* Layout for fractional PLLs. */
> +static const struct clk_pll_layout pll_frac_layout = {
> +	.mul_mask = GENMASK(31, 24),
> +	.frac_mask = GENMASK(21, 0),
> +	.mul_shift = 24,
> +	.frac_shift = 0,
> +};
> +
> +/* Layout for DIV PLLs. */
> +static const struct clk_pll_layout pll_divpmc_layout = {
> +	.div_mask = GENMASK(7, 0),
> +	.endiv_mask = BIT(29),
> +	.div_shift = 0,
> +	.endiv_shift = 29,
> +};
> +
> +/* Layout for DIV PLL ID PLLADIV2. */
> +static const struct clk_pll_layout plladiv2_divpmc_layout = {
> +	.div_mask = GENMASK(7, 0),
> +	.endiv_mask = BIT(29),
> +	.div_shift = 0,
> +	.endiv_shift = 29,
> +	.div2 = 1,
> +};
> +
> +/* Layout for DIVIO dividers. */
> +static const struct clk_pll_layout pll_divio_layout = {
> +	.div_mask	= GENMASK(19, 12),
> +	.endiv_mask	= BIT(30),
> +	.div_shift	= 12,
> +	.endiv_shift	= 30,
> +};
> +
> +/*
> + * PLL clocks description
> + * @n:		clock name
> + * @p:		clock parent
> + * @l:		clock layout
> + * @t:		clock type
> + * @c:		pll characteristics
> + * @f:		clock flags
> + * @eid:	export index in sam9x7->chws[] array
> + */
> +static const struct {
> +	const char *n;
> +	const char *p;
> +	const struct clk_pll_layout *l;
> +	u8 t;
> +	const struct clk_pll_characteristics *c;
> +	unsigned long f;
> +	u8 eid;
> +} sam9x7_plls[][PLL_ID_MAX] = {
> +	[PLL_ID_PLLA] = {
> +		{
> +			.n = "plla_fracck",
> +			.p = "mainck",
> +			.l = &plla_frac_layout,
> +			.t = PLL_TYPE_FRAC,
> +			/*
> +			 * This feeds plla_divpmcck which feeds CPU. It should
> +			 * not be disabled.
> +			 */
> +			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
> +			.c = &plla_characteristics,
> +		},
> +
> +		{
> +			.n = "plla_divpmcck",
> +			.p = "plla_fracck",
> +			.l = &pll_divpmc_layout,
> +			.t = PLL_TYPE_DIV,
> +			/* This feeds CPU. It should not be disabled */
> +			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
> +			.eid = PMC_PLLACK,
> +			.c = &plla_characteristics,
> +		},
> +	},
> +
> +	[PLL_ID_UPLL] = {
> +		{
> +			.n = "upll_fracck",
> +			.p = "main_osc",
> +			.l = &pll_frac_layout,
> +			.t = PLL_TYPE_FRAC,
> +			.f = CLK_SET_RATE_GATE,
> +			.c = &upll_characteristics,
> +		},
> +
> +		{
> +			.n = "upll_divpmcck",
> +			.p = "upll_fracck",
> +			.l = &pll_divpmc_layout,
> +			.t = PLL_TYPE_DIV,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.eid = PMC_UTMI,
> +			.c = &upll_characteristics,
> +		},
> +	},
> +
> +	[PLL_ID_AUDIO] = {
> +		{
> +			.n = "audiopll_fracck",
> +			.p = "main_osc",
> +			.l = &pll_frac_layout,
> +			.f = CLK_SET_RATE_GATE,
> +			.c = &audiopll_characteristics,
> +			.t = PLL_TYPE_FRAC,
> +		},
> +
> +		{
> +			.n = "audiopll_divpmcck",
> +			.p = "audiopll_fracck",
> +			.l = &pll_divpmc_layout,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.c = &audiopll_characteristics,
> +			.eid = PMC_AUDIOPMCPLL,
> +			.t = PLL_TYPE_DIV,
> +		},
> +
> +		{
> +			.n = "audiopll_diviock",
> +			.p = "audiopll_fracck",
> +			.l = &pll_divio_layout,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.c = &audiopll_characteristics,
> +			.eid = PMC_AUDIOIOPLL,
> +			.t = PLL_TYPE_DIV,
> +		},
> +	},
> +
> +	[PLL_ID_LVDS] = {
> +		{
> +			.n = "lvdspll_fracck",
> +			.p = "main_osc",
> +			.l = &pll_frac_layout,
> +			.f = CLK_SET_RATE_GATE,
> +			.c = &lvdspll_characteristics,
> +			.t = PLL_TYPE_FRAC,
> +		},
> +
> +		{
> +			.n = "lvdspll_divpmcck",
> +			.p = "lvdspll_fracck",
> +			.l = &pll_divpmc_layout,
> +			.f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
> +			     CLK_SET_RATE_PARENT,
> +			.c = &lvdspll_characteristics,
> +			.eid = PMC_LVDSPLL,
> +			.t = PLL_TYPE_DIV,
> +		},
> +	},
> +
> +	[PLL_ID_PLLA_DIV2] = {
> +		{
> +			.n = "plla_div2pmcck",
> +			.p = "plla_fracck",
> +			.l = &plladiv2_divpmc_layout,
> +			/*
> +			 * This may feed critical parts of the system like timers.
> +			 * It should not be disabled.
> +			 */
> +			.f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
> +			.c = &plladiv2_characteristics,
> +			.eid = PMC_PLLADIV2,
> +			.t = PLL_TYPE_DIV,
> +		},
> +	},
> +};
> +
> +static const struct clk_programmable_layout sam9x7_programmable_layout = {
> +	.pres_mask = 0xff,
> +	.pres_shift = 8,
> +	.css_mask = 0x1f,
> +	.have_slck_mck = 0,
> +	.is_pres_direct = 1,
> +};
> +
> +static const struct clk_pcr_layout sam9x7_pcr_layout = {
> +	.offset = 0x88,
> +	.cmd = BIT(31),
> +	.gckcss_mask = GENMASK(12, 8),
> +	.pid_mask = GENMASK(6, 0),
> +};
> +
> +static const struct {
> +	char *n;
> +	char *p;
> +	u8 id;
> +	unsigned long flags;
> +} sam9x7_systemck[] = {
> +	/*
> +	 * ddrck feeds DDR controller and is enabled by bootloader thus we need
> +	 * to keep it enabled in case there is no Linux consumer for it.
> +	 */
> +	{ .n = "ddrck",		.p = "masterck_div",	.id = 2,	.flags = CLK_IS_CRITICAL },
> +	{ .n = "uhpck",		.p = "usbck",		.id = 6 },
> +	{ .n = "pck0",		.p = "prog0",		.id = 8 },
> +	{ .n = "pck1",		.p = "prog1",		.id = 9 },
> +};
> +
> +/*
> + * Peripheral clocks description
> + * @n:		clock name
> + * @f:		clock flags
> + * @id:		peripheral id
> + */
> +static const struct {
> +	char *n;
> +	unsigned long f;
> +	u8 id;
> +} sam9x7_periphck[] = {
> +	{ .n = "pioA_clk",	.id = 2, },
> +	{ .n = "pioB_clk",	.id = 3, },
> +	{ .n = "pioC_clk",	.id = 4, },
> +	{ .n = "flex0_clk",	.id = 5, },
> +	{ .n = "flex1_clk",	.id = 6, },
> +	{ .n = "flex2_clk",	.id = 7, },
> +	{ .n = "flex3_clk",	.id = 8, },
> +	{ .n = "flex6_clk",	.id = 9, },
> +	{ .n = "flex7_clk",	.id = 10, },
> +	{ .n = "flex8_clk",	.id = 11, },
> +	{ .n = "sdmmc0_clk",	.id = 12, },
> +	{ .n = "flex4_clk",	.id = 13, },
> +	{ .n = "flex5_clk",	.id = 14, },
> +	{ .n = "flex9_clk",	.id = 15, },
> +	{ .n = "flex10_clk",	.id = 16, },
> +	{ .n = "tcb0_clk",	.id = 17, },
> +	{ .n = "pwm_clk",	.id = 18, },
> +	{ .n = "adc_clk",	.id = 19, },
> +	{ .n = "dma0_clk",	.id = 20, },
> +	{ .n = "uhphs_clk",	.id = 22, },
> +	{ .n = "udphs_clk",	.id = 23, },
> +	{ .n = "macb0_clk",	.id = 24, },
> +	{ .n = "lcd_clk",	.id = 25, },
> +	{ .n = "sdmmc1_clk",	.id = 26, },
> +	{ .n = "ssc_clk",	.id = 28, },
> +	{ .n = "can0_clk",	.id = 29, },
> +	{ .n = "can1_clk",	.id = 30, },
> +	{ .n = "flex11_clk",	.id = 32, },
> +	{ .n = "flex12_clk",	.id = 33, },
> +	{ .n = "i2s_clk",	.id = 34, },
> +	{ .n = "qspi_clk",	.id = 35, },
> +	{ .n = "gfx2d_clk",	.id = 36, },
> +	{ .n = "pit64b0_clk",	.id = 37, },
> +	{ .n = "trng_clk",	.id = 38, },
> +	{ .n = "aes_clk",	.id = 39, },
> +	{ .n = "tdes_clk",	.id = 40, },
> +	{ .n = "sha_clk",	.id = 41, },
> +	{ .n = "classd_clk",	.id = 42, },
> +	{ .n = "isi_clk",	.id = 43, },
> +	{ .n = "pioD_clk",	.id = 44, },
> +	{ .n = "tcb1_clk",	.id = 45, },
> +	{ .n = "dbgu_clk",	.id = 47, },
> +	/*
> +	 * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
> +	 * need to keep it enabled in case there is no Linux consumer for it.
> +	 */
> +	{ .n = "mpddr_clk",	.id = 49,	.f = CLK_IS_CRITICAL },
> +	{ .n = "csi2dc_clk",	.id = 52, },
> +	{ .n = "csi4l_clk",	.id = 53, },
> +	{ .n = "dsi4l_clk",	.id = 54, },
> +	{ .n = "lvdsc_clk",	.id = 56, },
> +	{ .n = "pit64b1_clk",	.id = 58, },
> +	{ .n = "puf_clk",	.id = 59, },
> +	{ .n = "gmactsu_clk",	.id = 67, },
> +};
> +
> +/*
> + * Generic clock description
> + * @n:			clock name
> + * @pp:			PLL parents
> + * @pp_mux_table:	PLL parents mux table
> + * @r:			clock output range
> + * @pp_chg_id:		id in parent array of changeable PLL parent
> + * @pp_count:		PLL parents count
> + * @id:			clock id
> + */
> +static const struct {
> +	const char *n;
> +	const char *pp[8];
> +	const char pp_mux_table[8];
> +	struct clk_range r;
> +	int pp_chg_id;
> +	u8 pp_count;
> +	u8 id;
> +} sam9x7_gck[] = {
> +	{
> +		.n = "flex0_gclk",
> +		.id = 5,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex1_gclk",
> +		.id = 6,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex2_gclk",
> +		.id = 7,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex3_gclk",
> +		.id = 8,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex6_gclk",
> +		.id = 9,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex7_gclk",
> +		.id = 10,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex8_gclk",
> +		.id = 11,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "sdmmc0_gclk",
> +		.id = 12,
> +		.r = { .max = 105000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex4_gclk",
> +		.id = 13,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex5_gclk",
> +		.id = 14,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex9_gclk",
> +		.id = 15,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex10_gclk",
> +		.id = 16,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "tcb0_gclk",
> +		.id = 17,
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "adc_gclk",
> +		.id = 19,
> +		.pp = { "upll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 5, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "lcd_gclk",
> +		.id = 25,
> +		.r = { .max = 75000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "sdmmc1_gclk",
> +		.id = 26,
> +		.r = { .max = 105000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "mcan0_gclk",
> +		.id = 29,
> +		.r = { .max = 80000000 },
> +		.pp = { "upll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 5, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "mcan1_gclk",
> +		.id = 30,
> +		.r = { .max = 80000000 },
> +		.pp = { "upll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 5, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex11_gclk",
> +		.id = 32,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "flex12_gclk",
> +		.id = 33,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "i2s_gclk",
> +		.id = 34,
> +		.r = { .max = 100000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "qspi_gclk",
> +		.id = 35,
> +		.r = { .max = 200000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "pit64b0_gclk",
> +		.id = 37,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "classd_gclk",
> +		.id = 42,
> +		.r = { .max = 100000000 },
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "tcb1_gclk",
> +		.id = 45,
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "dbgu_gclk",
> +		.id = 47,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "mipiphy_gclk",
> +		.id = 55,
> +		.r = { .max = 27000000 },
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "pit64b1_gclk",
> +		.id = 58,
> +		.pp = { "plla_div2pmcck", },
> +		.pp_mux_table = { 8, },
> +		.pp_count = 1,
> +		.pp_chg_id = INT_MIN,
> +	},
> +
> +	{
> +		.n = "gmac_gclk",
> +		.id = 67,
> +		.pp = { "audiopll_divpmcck", "plla_div2pmcck", },
> +		.pp_mux_table = { 6, 8, },
> +		.pp_count = 2,
> +		.pp_chg_id = INT_MIN,
> +	},
> +};
> +
> +static void __init sam9x7_pmc_setup(struct device_node *np)
> +{
> +	struct clk_range range = CLK_RANGE(0, 0);
> +	const char *td_slck_name, *md_slck_name, *mainxtal_name;
> +	struct pmc_data *sam9x7_pmc;
> +	const char *parent_names[9];
> +	void **clk_mux_buffer = NULL;
> +	int clk_mux_buffer_size = 0;
> +	struct clk_hw *main_osc_hw;
> +	struct regmap *regmap;
> +	struct clk_hw *hw;
> +	int i, j;
> +
> +	i = of_property_match_string(np, "clock-names", "td_slck");
> +	if (i < 0)
> +		return;
> +
> +	td_slck_name = of_clk_get_parent_name(np, i);
> +
> +	i = of_property_match_string(np, "clock-names", "md_slck");
> +	if (i < 0)
> +		return;
> +
> +	md_slck_name = of_clk_get_parent_name(np, i);
> +
> +	i = of_property_match_string(np, "clock-names", "main_xtal");
> +	if (i < 0)
> +		return;
> +	mainxtal_name = of_clk_get_parent_name(np, i);
> +
> +	regmap = device_node_to_regmap(np);
> +	if (IS_ERR(regmap))
> +		return;
> +
> +	sam9x7_pmc = pmc_data_allocate(PMC_LVDSPLL + 1,
> +				       nck(sam9x7_systemck),
> +				       nck(sam9x7_periphck),
> +				       nck(sam9x7_gck), 8);
> +	if (!sam9x7_pmc)
> +		return;
> +
> +	clk_mux_buffer = kmalloc(sizeof(void *) *
> +				 (ARRAY_SIZE(sam9x7_gck)),
> +				 GFP_KERNEL);
> +	if (!clk_mux_buffer)
> +		goto err_free;
> +
> +	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
> +					   50000000);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +	main_osc_hw = hw;
> +
> +	parent_names[0] = "main_rc_osc";
> +	parent_names[1] = "main_osc";
> +	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	sam9x7_pmc->chws[PMC_MAIN] = hw;
> +
> +	for (i = 0; i < PLL_ID_MAX; i++) {
> +		for (j = 0; j < 3; j++) {

I now realize that we are alocating more than needed memory for each PLL in
sam9x7_plls[][]. The number of columns for the 2d array is PLL_ID_MAX and
it should be 3. I can adjust it when applying but I need you to run a
simple boot test with it.

> +			struct clk_hw *parent_hw;
> +
> +			if (!sam9x7_plls[i][j].n)
> +				continue;
> +
> +			switch (sam9x7_plls[i][j].t) {
> +			case PLL_TYPE_FRAC:
> +				if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
> +					parent_hw = sam9x7_pmc->chws[PMC_MAIN];
> +				else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
> +					parent_hw = main_osc_hw;
> +				else
> +					parent_hw = __clk_get_hw(of_clk_get_by_name
> +								 (np, sam9x7_plls[i][j].p));
> +
> +				hw = sam9x60_clk_register_frac_pll(regmap,
> +								   &pmc_pll_lock,
> +								   sam9x7_plls[i][j].n,
> +								   sam9x7_plls[i][j].p,
> +								   parent_hw, i,
> +								   sam9x7_plls[i][j].c,
> +								   sam9x7_plls[i][j].l,
> +								   sam9x7_plls[i][j].f);
> +				break;
> +
> +			case PLL_TYPE_DIV:
> +				hw = sam9x60_clk_register_div_pll(regmap,
> +								  &pmc_pll_lock,
> +								  sam9x7_plls[i][j].n,
> +								  sam9x7_plls[i][j].p, NULL, i,
> +								  sam9x7_plls[i][j].c,
> +								  sam9x7_plls[i][j].l,
> +								  sam9x7_plls[i][j].f, 0);
> +				break;
> +
> +			default:
> +				continue;
> +			}
> +
> +			if (IS_ERR(hw))
> +				goto err_free;
> +
> +			if (sam9x7_plls[i][j].eid)
> +				sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
> +		}
> +	}
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = "mainck";
> +	parent_names[2] = "plla_divpmcck";
> +	parent_names[3] = "upll_divpmcck";
> +	hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
> +					   parent_names, NULL, &sam9x7_master_layout,
> +					   &mck_characteristics, &mck_lock);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	hw = at91_clk_register_master_div(regmap, "masterck_div",
> +					  "masterck_pres", NULL, &sam9x7_master_layout,
> +					  &mck_characteristics, &mck_lock,
> +					  CLK_SET_RATE_GATE, 0);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	sam9x7_pmc->chws[PMC_MCK] = hw;
> +
> +	parent_names[0] = "plla_divpmcck";
> +	parent_names[1] = "upll_divpmcck";
> +	parent_names[2] = "main_osc";
> +	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
> +	if (IS_ERR(hw))
> +		goto err_free;
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = td_slck_name;
> +	parent_names[2] = "mainck";
> +	parent_names[3] = "masterck_div";
> +	parent_names[4] = "plla_divpmcck";
> +	parent_names[5] = "upll_divpmcck";
> +	parent_names[6] = "audiopll_divpmcck";
> +	for (i = 0; i < 2; i++) {
> +		char name[6];
> +
> +		snprintf(name, sizeof(name), "prog%d", i);
> +
> +		hw = at91_clk_register_programmable(regmap, name,
> +						    parent_names, NULL, 7, i,
> +						    &sam9x7_programmable_layout,
> +						    NULL);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->pchws[i] = hw;
> +	}
> +
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
> +		hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
> +					      sam9x7_systemck[i].p, NULL,
> +					      sam9x7_systemck[i].id,
> +					      sam9x7_systemck[i].flags);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
> +	}
> +
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
> +		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
> +							 &sam9x7_pcr_layout,
> +							 sam9x7_periphck[i].n,
> +							 "masterck_div", NULL,
> +							 sam9x7_periphck[i].id,
> +							 &range, INT_MIN,
> +							 sam9x7_periphck[i].f);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
> +	}
> +
> +	parent_names[0] = md_slck_name;
> +	parent_names[1] = td_slck_name;
> +	parent_names[2] = "mainck";
> +	parent_names[3] = "masterck_div";
> +	for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
> +		u8 num_parents = 4 + sam9x7_gck[i].pp_count;
> +		u32 *mux_table;
> +
> +		mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
> +					  GFP_KERNEL);
> +		if (!mux_table)
> +			goto err_free;
> +
> +		PMC_INIT_TABLE(mux_table, 4);
> +		PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
> +			       sam9x7_gck[i].pp_count);
> +		PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
> +			       sam9x7_gck[i].pp_count);
> +
> +		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
> +						 &sam9x7_pcr_layout,
> +						 sam9x7_gck[i].n,
> +						 parent_names, NULL, mux_table,
> +						 num_parents,
> +						 sam9x7_gck[i].id,
> +						 &sam9x7_gck[i].r,
> +						 sam9x7_gck[i].pp_chg_id);
> +		if (IS_ERR(hw))
> +			goto err_free;
> +
> +		sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
> +		clk_mux_buffer[clk_mux_buffer_size++] = mux_table;
> +	}
> +
> +	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
> +	kfree(clk_mux_buffer);
> +
> +	return;
> +
> +err_free:
> +	if (clk_mux_buffer) {
> +		for (i = 0; i < clk_mux_buffer_size; i++)
> +			kfree(clk_mux_buffer[i]);
> +		kfree(clk_mux_buffer);
> +	}
> +	kfree(sam9x7_pmc);
> +}
> +
> +/* Some clks are used for a clocksource */
> +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);

Re: [PATCH v5 13/27] clk: at91: sam9x7: add sam9x7 pmc driver

[Varshini.Rajendran]

Hi Claudiu,

On 14/07/24 7:25 pm, claudiu beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi, Varshini,
> 
> On 03.07.2024 13:28, Varshini Rajendran wrote:
>> Add a driver for the PMC clocks of sam9x7 Soc family.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>>   drivers/clk/at91/Makefile |   1 +
>>   drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>>   2 files changed, 947 insertions(+)
>>   create mode 100644 drivers/clk/at91/sam9x7.c
>>
>> diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
>> index 89061b85e7d2..8e3684ba2c74 100644
>> --- a/drivers/clk/at91/Makefile
>> +++ b/drivers/clk/at91/Makefile
>> @@ -20,6 +20,7 @@ obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.
>>   obj-$(CONFIG_SOC_AT91SAM9) += at91sam9g45.o dt-compat.o
>>   obj-$(CONFIG_SOC_AT91SAM9) += at91sam9n12.o at91sam9x5.o dt-compat.o
>>   obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
>> +obj-$(CONFIG_SOC_SAM9X7) += sam9x7.o
>>   obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o dt-compat.o
>>   obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o dt-compat.o
>>   obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o dt-compat.o
>> diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
>> new file mode 100644
>> index 000000000000..b031280bbb32
>> --- /dev/null
>> +++ b/drivers/clk/at91/sam9x7.c
>> @@ -0,0 +1,946 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * SAM9X7 PMC code.
>> + *
>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>> + *
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/slab.h>
>> +
>> +#include <dt-bindings/clock/at91.h>
>> +
>> +#include "pmc.h"
>> +
>> +static DEFINE_SPINLOCK(pmc_pll_lock);
>> +static DEFINE_SPINLOCK(mck_lock);
>> +
>> +/**
>> + * enum pll_ids - PLL clocks identifiers
>> + * @PLL_ID_PLLA:     PLLA identifier
>> + * @PLL_ID_UPLL:     UPLL identifier
>> + * @PLL_ID_AUDIO:    Audio PLL identifier
>> + * @PLL_ID_LVDS:     LVDS PLL identifier
>> + * @PLL_ID_PLLA_DIV2:        PLLA DIV2 identifier
>> + * @PLL_ID_MAX:              Max PLL Identifier
>> + */
>> +enum pll_ids {
>> +     PLL_ID_PLLA,
>> +     PLL_ID_UPLL,
>> +     PLL_ID_AUDIO,
>> +     PLL_ID_LVDS,
>> +     PLL_ID_PLLA_DIV2,
>> +     PLL_ID_MAX,
>> +};
>> +
>> +/**
>> + * enum pll_type - PLL type identifiers
>> + * @PLL_TYPE_FRAC:   fractional PLL identifier
>> + * @PLL_TYPE_DIV:    divider PLL identifier
>> + */
>> +enum pll_type {
>> +     PLL_TYPE_FRAC,
>> +     PLL_TYPE_DIV,
>> +};
>> +
>> +static const struct clk_master_characteristics mck_characteristics = {
>> +     .output = { .min = 32000000, .max = 266666667 },
>> +     .divisors = { 1, 2, 4, 3, 5},
>> +     .have_div3_pres = 1,
>> +};
>> +
>> +static const struct clk_master_layout sam9x7_master_layout = {
>> +     .mask = 0x373,
>> +     .pres_shift = 4,
>> +     .offset = 0x28,
>> +};
>> +
>> +/* Fractional PLL core output range. */
>> +static const struct clk_range plla_core_outputs[] = {
>> +     { .min = 375000000, .max = 1600000000 },
>> +};
>> +
>> +static const struct clk_range upll_core_outputs[] = {
>> +     { .min = 600000000, .max = 1200000000 },
>> +};
>> +
>> +static const struct clk_range lvdspll_core_outputs[] = {
>> +     { .min = 400000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range audiopll_core_outputs[] = {
>> +     { .min = 400000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range plladiv2_core_outputs[] = {
>> +     { .min = 375000000, .max = 1600000000 },
>> +};
>> +
>> +/* Fractional PLL output range. */
>> +static const struct clk_range plla_outputs[] = {
>> +     { .min = 732421, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range upll_outputs[] = {
>> +     { .min = 300000000, .max = 600000000 },
>> +};
>> +
>> +static const struct clk_range lvdspll_outputs[] = {
>> +     { .min = 10000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range audiopll_outputs[] = {
>> +     { .min = 10000000, .max = 800000000 },
>> +};
>> +
>> +static const struct clk_range plladiv2_outputs[] = {
>> +     { .min = 366210, .max = 400000000 },
>> +};
>> +
>> +/* PLL characteristics. */
>> +static const struct clk_pll_characteristics plla_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(plla_outputs),
>> +     .output = plla_outputs,
>> +     .core_output = plla_core_outputs,
>> +};
>> +
>> +static const struct clk_pll_characteristics upll_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(upll_outputs),
>> +     .output = upll_outputs,
>> +     .core_output = upll_core_outputs,
>> +     .upll = true,
>> +};
>> +
>> +static const struct clk_pll_characteristics lvdspll_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(lvdspll_outputs),
>> +     .output = lvdspll_outputs,
>> +     .core_output = lvdspll_core_outputs,
>> +};
>> +
>> +static const struct clk_pll_characteristics audiopll_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(audiopll_outputs),
>> +     .output = audiopll_outputs,
>> +     .core_output = audiopll_core_outputs,
>> +};
>> +
>> +static const struct clk_pll_characteristics plladiv2_characteristics = {
>> +     .input = { .min = 20000000, .max = 50000000 },
>> +     .num_output = ARRAY_SIZE(plladiv2_outputs),
>> +     .output = plladiv2_outputs,
>> +     .core_output = plladiv2_core_outputs,
>> +};
>> +
>> +/* Layout for fractional PLL ID PLLA. */
>> +static const struct clk_pll_layout plla_frac_layout = {
>> +     .mul_mask = GENMASK(31, 24),
>> +     .frac_mask = GENMASK(21, 0),
>> +     .mul_shift = 24,
>> +     .frac_shift = 0,
>> +     .div2 = 1,
>> +};
>> +
>> +/* Layout for fractional PLLs. */
>> +static const struct clk_pll_layout pll_frac_layout = {
>> +     .mul_mask = GENMASK(31, 24),
>> +     .frac_mask = GENMASK(21, 0),
>> +     .mul_shift = 24,
>> +     .frac_shift = 0,
>> +};
>> +
>> +/* Layout for DIV PLLs. */
>> +static const struct clk_pll_layout pll_divpmc_layout = {
>> +     .div_mask = GENMASK(7, 0),
>> +     .endiv_mask = BIT(29),
>> +     .div_shift = 0,
>> +     .endiv_shift = 29,
>> +};
>> +
>> +/* Layout for DIV PLL ID PLLADIV2. */
>> +static const struct clk_pll_layout plladiv2_divpmc_layout = {
>> +     .div_mask = GENMASK(7, 0),
>> +     .endiv_mask = BIT(29),
>> +     .div_shift = 0,
>> +     .endiv_shift = 29,
>> +     .div2 = 1,
>> +};
>> +
>> +/* Layout for DIVIO dividers. */
>> +static const struct clk_pll_layout pll_divio_layout = {
>> +     .div_mask       = GENMASK(19, 12),
>> +     .endiv_mask     = BIT(30),
>> +     .div_shift      = 12,
>> +     .endiv_shift    = 30,
>> +};
>> +
>> +/*
>> + * PLL clocks description
>> + * @n:               clock name
>> + * @p:               clock parent
>> + * @l:               clock layout
>> + * @t:               clock type
>> + * @c:               pll characteristics
>> + * @f:               clock flags
>> + * @eid:     export index in sam9x7->chws[] array
>> + */
>> +static const struct {
>> +     const char *n;
>> +     const char *p;
>> +     const struct clk_pll_layout *l;
>> +     u8 t;
>> +     const struct clk_pll_characteristics *c;
>> +     unsigned long f;
>> +     u8 eid;
>> +} sam9x7_plls[][PLL_ID_MAX] = {
>> +     [PLL_ID_PLLA] = {
>> +             {
>> +                     .n = "plla_fracck",
>> +                     .p = "mainck",
>> +                     .l = &plla_frac_layout,
>> +                     .t = PLL_TYPE_FRAC,
>> +                     /*
>> +                      * This feeds plla_divpmcck which feeds CPU. It should
>> +                      * not be disabled.
>> +                      */
>> +                     .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
>> +                     .c = &plla_characteristics,
>> +             },
>> +
>> +             {
>> +                     .n = "plla_divpmcck",
>> +                     .p = "plla_fracck",
>> +                     .l = &pll_divpmc_layout,
>> +                     .t = PLL_TYPE_DIV,
>> +                     /* This feeds CPU. It should not be disabled */
>> +                     .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
>> +                     .eid = PMC_PLLACK,
>> +                     .c = &plla_characteristics,
>> +             },
>> +     },
>> +
>> +     [PLL_ID_UPLL] = {
>> +             {
>> +                     .n = "upll_fracck",
>> +                     .p = "main_osc",
>> +                     .l = &pll_frac_layout,
>> +                     .t = PLL_TYPE_FRAC,
>> +                     .f = CLK_SET_RATE_GATE,
>> +                     .c = &upll_characteristics,
>> +             },
>> +
>> +             {
>> +                     .n = "upll_divpmcck",
>> +                     .p = "upll_fracck",
>> +                     .l = &pll_divpmc_layout,
>> +                     .t = PLL_TYPE_DIV,
>> +                     .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
>> +                          CLK_SET_RATE_PARENT,
>> +                     .eid = PMC_UTMI,
>> +                     .c = &upll_characteristics,
>> +             },
>> +     },
>> +
>> +     [PLL_ID_AUDIO] = {
>> +             {
>> +                     .n = "audiopll_fracck",
>> +                     .p = "main_osc",
>> +                     .l = &pll_frac_layout,
>> +                     .f = CLK_SET_RATE_GATE,
>> +                     .c = &audiopll_characteristics,
>> +                     .t = PLL_TYPE_FRAC,
>> +             },
>> +
>> +             {
>> +                     .n = "audiopll_divpmcck",
>> +                     .p = "audiopll_fracck",
>> +                     .l = &pll_divpmc_layout,
>> +                     .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
>> +                          CLK_SET_RATE_PARENT,
>> +                     .c = &audiopll_characteristics,
>> +                     .eid = PMC_AUDIOPMCPLL,
>> +                     .t = PLL_TYPE_DIV,
>> +             },
>> +
>> +             {
>> +                     .n = "audiopll_diviock",
>> +                     .p = "audiopll_fracck",
>> +                     .l = &pll_divio_layout,
>> +                     .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
>> +                          CLK_SET_RATE_PARENT,
>> +                     .c = &audiopll_characteristics,
>> +                     .eid = PMC_AUDIOIOPLL,
>> +                     .t = PLL_TYPE_DIV,
>> +             },
>> +     },
>> +
>> +     [PLL_ID_LVDS] = {
>> +             {
>> +                     .n = "lvdspll_fracck",
>> +                     .p = "main_osc",
>> +                     .l = &pll_frac_layout,
>> +                     .f = CLK_SET_RATE_GATE,
>> +                     .c = &lvdspll_characteristics,
>> +                     .t = PLL_TYPE_FRAC,
>> +             },
>> +
>> +             {
>> +                     .n = "lvdspll_divpmcck",
>> +                     .p = "lvdspll_fracck",
>> +                     .l = &pll_divpmc_layout,
>> +                     .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
>> +                          CLK_SET_RATE_PARENT,
>> +                     .c = &lvdspll_characteristics,
>> +                     .eid = PMC_LVDSPLL,
>> +                     .t = PLL_TYPE_DIV,
>> +             },
>> +     },
>> +
>> +     [PLL_ID_PLLA_DIV2] = {
>> +             {
>> +                     .n = "plla_div2pmcck",
>> +                     .p = "plla_fracck",
>> +                     .l = &plladiv2_divpmc_layout,
>> +                     /*
>> +                      * This may feed critical parts of the system like timers.
>> +                      * It should not be disabled.
>> +                      */
>> +                     .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
>> +                     .c = &plladiv2_characteristics,
>> +                     .eid = PMC_PLLADIV2,
>> +                     .t = PLL_TYPE_DIV,
>> +             },
>> +     },
>> +};
>> +
>> +static const struct clk_programmable_layout sam9x7_programmable_layout = {
>> +     .pres_mask = 0xff,
>> +     .pres_shift = 8,
>> +     .css_mask = 0x1f,
>> +     .have_slck_mck = 0,
>> +     .is_pres_direct = 1,
>> +};
>> +
>> +static const struct clk_pcr_layout sam9x7_pcr_layout = {
>> +     .offset = 0x88,
>> +     .cmd = BIT(31),
>> +     .gckcss_mask = GENMASK(12, 8),
>> +     .pid_mask = GENMASK(6, 0),
>> +};
>> +
>> +static const struct {
>> +     char *n;
>> +     char *p;
>> +     u8 id;
>> +     unsigned long flags;
>> +} sam9x7_systemck[] = {
>> +     /*
>> +      * ddrck feeds DDR controller and is enabled by bootloader thus we need
>> +      * to keep it enabled in case there is no Linux consumer for it.
>> +      */
>> +     { .n = "ddrck",         .p = "masterck_div",    .id = 2,        .flags = CLK_IS_CRITICAL },
>> +     { .n = "uhpck",         .p = "usbck",           .id = 6 },
>> +     { .n = "pck0",          .p = "prog0",           .id = 8 },
>> +     { .n = "pck1",          .p = "prog1",           .id = 9 },
>> +};
>> +
>> +/*
>> + * Peripheral clocks description
>> + * @n:               clock name
>> + * @f:               clock flags
>> + * @id:              peripheral id
>> + */
>> +static const struct {
>> +     char *n;
>> +     unsigned long f;
>> +     u8 id;
>> +} sam9x7_periphck[] = {
>> +     { .n = "pioA_clk",      .id = 2, },
>> +     { .n = "pioB_clk",      .id = 3, },
>> +     { .n = "pioC_clk",      .id = 4, },
>> +     { .n = "flex0_clk",     .id = 5, },
>> +     { .n = "flex1_clk",     .id = 6, },
>> +     { .n = "flex2_clk",     .id = 7, },
>> +     { .n = "flex3_clk",     .id = 8, },
>> +     { .n = "flex6_clk",     .id = 9, },
>> +     { .n = "flex7_clk",     .id = 10, },
>> +     { .n = "flex8_clk",     .id = 11, },
>> +     { .n = "sdmmc0_clk",    .id = 12, },
>> +     { .n = "flex4_clk",     .id = 13, },
>> +     { .n = "flex5_clk",     .id = 14, },
>> +     { .n = "flex9_clk",     .id = 15, },
>> +     { .n = "flex10_clk",    .id = 16, },
>> +     { .n = "tcb0_clk",      .id = 17, },
>> +     { .n = "pwm_clk",       .id = 18, },
>> +     { .n = "adc_clk",       .id = 19, },
>> +     { .n = "dma0_clk",      .id = 20, },
>> +     { .n = "uhphs_clk",     .id = 22, },
>> +     { .n = "udphs_clk",     .id = 23, },
>> +     { .n = "macb0_clk",     .id = 24, },
>> +     { .n = "lcd_clk",       .id = 25, },
>> +     { .n = "sdmmc1_clk",    .id = 26, },
>> +     { .n = "ssc_clk",       .id = 28, },
>> +     { .n = "can0_clk",      .id = 29, },
>> +     { .n = "can1_clk",      .id = 30, },
>> +     { .n = "flex11_clk",    .id = 32, },
>> +     { .n = "flex12_clk",    .id = 33, },
>> +     { .n = "i2s_clk",       .id = 34, },
>> +     { .n = "qspi_clk",      .id = 35, },
>> +     { .n = "gfx2d_clk",     .id = 36, },
>> +     { .n = "pit64b0_clk",   .id = 37, },
>> +     { .n = "trng_clk",      .id = 38, },
>> +     { .n = "aes_clk",       .id = 39, },
>> +     { .n = "tdes_clk",      .id = 40, },
>> +     { .n = "sha_clk",       .id = 41, },
>> +     { .n = "classd_clk",    .id = 42, },
>> +     { .n = "isi_clk",       .id = 43, },
>> +     { .n = "pioD_clk",      .id = 44, },
>> +     { .n = "tcb1_clk",      .id = 45, },
>> +     { .n = "dbgu_clk",      .id = 47, },
>> +     /*
>> +      * mpddr_clk feeds DDR controller and is enabled by bootloader thus we
>> +      * need to keep it enabled in case there is no Linux consumer for it.
>> +      */
>> +     { .n = "mpddr_clk",     .id = 49,       .f = CLK_IS_CRITICAL },
>> +     { .n = "csi2dc_clk",    .id = 52, },
>> +     { .n = "csi4l_clk",     .id = 53, },
>> +     { .n = "dsi4l_clk",     .id = 54, },
>> +     { .n = "lvdsc_clk",     .id = 56, },
>> +     { .n = "pit64b1_clk",   .id = 58, },
>> +     { .n = "puf_clk",       .id = 59, },
>> +     { .n = "gmactsu_clk",   .id = 67, },
>> +};
>> +
>> +/*
>> + * Generic clock description
>> + * @n:                       clock name
>> + * @pp:                      PLL parents
>> + * @pp_mux_table:    PLL parents mux table
>> + * @r:                       clock output range
>> + * @pp_chg_id:               id in parent array of changeable PLL parent
>> + * @pp_count:                PLL parents count
>> + * @id:                      clock id
>> + */
>> +static const struct {
>> +     const char *n;
>> +     const char *pp[8];
>> +     const char pp_mux_table[8];
>> +     struct clk_range r;
>> +     int pp_chg_id;
>> +     u8 pp_count;
>> +     u8 id;
>> +} sam9x7_gck[] = {
>> +     {
>> +             .n = "flex0_gclk",
>> +             .id = 5,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex1_gclk",
>> +             .id = 6,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex2_gclk",
>> +             .id = 7,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex3_gclk",
>> +             .id = 8,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex6_gclk",
>> +             .id = 9,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex7_gclk",
>> +             .id = 10,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex8_gclk",
>> +             .id = 11,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "sdmmc0_gclk",
>> +             .id = 12,
>> +             .r = { .max = 105000000 },
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex4_gclk",
>> +             .id = 13,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex5_gclk",
>> +             .id = 14,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex9_gclk",
>> +             .id = 15,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex10_gclk",
>> +             .id = 16,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "tcb0_gclk",
>> +             .id = 17,
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "adc_gclk",
>> +             .id = 19,
>> +             .pp = { "upll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 5, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "lcd_gclk",
>> +             .id = 25,
>> +             .r = { .max = 75000000 },
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "sdmmc1_gclk",
>> +             .id = 26,
>> +             .r = { .max = 105000000 },
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "mcan0_gclk",
>> +             .id = 29,
>> +             .r = { .max = 80000000 },
>> +             .pp = { "upll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 5, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "mcan1_gclk",
>> +             .id = 30,
>> +             .r = { .max = 80000000 },
>> +             .pp = { "upll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 5, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex11_gclk",
>> +             .id = 32,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "flex12_gclk",
>> +             .id = 33,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "i2s_gclk",
>> +             .id = 34,
>> +             .r = { .max = 100000000 },
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "qspi_gclk",
>> +             .id = 35,
>> +             .r = { .max = 200000000 },
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "pit64b0_gclk",
>> +             .id = 37,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "classd_gclk",
>> +             .id = 42,
>> +             .r = { .max = 100000000 },
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "tcb1_gclk",
>> +             .id = 45,
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "dbgu_gclk",
>> +             .id = 47,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "mipiphy_gclk",
>> +             .id = 55,
>> +             .r = { .max = 27000000 },
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "pit64b1_gclk",
>> +             .id = 58,
>> +             .pp = { "plla_div2pmcck", },
>> +             .pp_mux_table = { 8, },
>> +             .pp_count = 1,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +
>> +     {
>> +             .n = "gmac_gclk",
>> +             .id = 67,
>> +             .pp = { "audiopll_divpmcck", "plla_div2pmcck", },
>> +             .pp_mux_table = { 6, 8, },
>> +             .pp_count = 2,
>> +             .pp_chg_id = INT_MIN,
>> +     },
>> +};
>> +
>> +static void __init sam9x7_pmc_setup(struct device_node *np)
>> +{
>> +     struct clk_range range = CLK_RANGE(0, 0);
>> +     const char *td_slck_name, *md_slck_name, *mainxtal_name;
>> +     struct pmc_data *sam9x7_pmc;
>> +     const char *parent_names[9];
>> +     void **clk_mux_buffer = NULL;
>> +     int clk_mux_buffer_size = 0;
>> +     struct clk_hw *main_osc_hw;
>> +     struct regmap *regmap;
>> +     struct clk_hw *hw;
>> +     int i, j;
>> +
>> +     i = of_property_match_string(np, "clock-names", "td_slck");
>> +     if (i < 0)
>> +             return;
>> +
>> +     td_slck_name = of_clk_get_parent_name(np, i);
>> +
>> +     i = of_property_match_string(np, "clock-names", "md_slck");
>> +     if (i < 0)
>> +             return;
>> +
>> +     md_slck_name = of_clk_get_parent_name(np, i);
>> +
>> +     i = of_property_match_string(np, "clock-names", "main_xtal");
>> +     if (i < 0)
>> +             return;
>> +     mainxtal_name = of_clk_get_parent_name(np, i);
>> +
>> +     regmap = device_node_to_regmap(np);
>> +     if (IS_ERR(regmap))
>> +             return;
>> +
>> +     sam9x7_pmc = pmc_data_allocate(PMC_LVDSPLL + 1,
>> +                                    nck(sam9x7_systemck),
>> +                                    nck(sam9x7_periphck),
>> +                                    nck(sam9x7_gck), 8);
>> +     if (!sam9x7_pmc)
>> +             return;
>> +
>> +     clk_mux_buffer = kmalloc(sizeof(void *) *
>> +                              (ARRAY_SIZE(sam9x7_gck)),
>> +                              GFP_KERNEL);
>> +     if (!clk_mux_buffer)
>> +             goto err_free;
>> +
>> +     hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
>> +                                        50000000);
>> +     if (IS_ERR(hw))
>> +             goto err_free;
>> +
>> +     hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 0);
>> +     if (IS_ERR(hw))
>> +             goto err_free;
>> +     main_osc_hw = hw;
>> +
>> +     parent_names[0] = "main_rc_osc";
>> +     parent_names[1] = "main_osc";
>> +     hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
>> +     if (IS_ERR(hw))
>> +             goto err_free;
>> +
>> +     sam9x7_pmc->chws[PMC_MAIN] = hw;
>> +
>> +     for (i = 0; i < PLL_ID_MAX; i++) {
>> +             for (j = 0; j < 3; j++) {
> 
> I now realize that we are alocating more than needed memory for each PLL in
> sam9x7_plls[][]. The number of columns for the 2d array is PLL_ID_MAX and
> it should be 3. I can adjust it when applying but I need you to run a
> simple boot test with it.
> 
Yes. It boots and works perfectly with the change suggested. I am 
pasting the snippet below just to be on the same page.

--- a/drivers/clk/at91/sam9x7.c
+++ b/drivers/clk/at91/sam9x7.c
@@ -198,7 +198,7 @@ static const struct {
         const struct clk_pll_characteristics *c;
         unsigned long f;
         u8 eid;
-} sam9x7_plls[][PLL_ID_MAX] = {
+} sam9x7_plls[][3] = {
         [PLL_ID_PLLA] = {
                 {
                         .n = "plla_fracck",

>> +                     struct clk_hw *parent_hw;
>> +
>> +                     if (!sam9x7_plls[i][j].n)
>> +                             continue;
>> +
>> +                     switch (sam9x7_plls[i][j].t) {
>> +                     case PLL_TYPE_FRAC:
>> +                             if (!strcmp(sam9x7_plls[i][j].p, "mainck"))
>> +                                     parent_hw = sam9x7_pmc->chws[PMC_MAIN];
>> +                             else if (!strcmp(sam9x7_plls[i][j].p, "main_osc"))
>> +                                     parent_hw = main_osc_hw;
>> +                             else
>> +                                     parent_hw = __clk_get_hw(of_clk_get_by_name
>> +                                                              (np, sam9x7_plls[i][j].p));
>> +
>> +                             hw = sam9x60_clk_register_frac_pll(regmap,
>> +                                                                &pmc_pll_lock,
>> +                                                                sam9x7_plls[i][j].n,
>> +                                                                sam9x7_plls[i][j].p,
>> +                                                                parent_hw, i,
>> +                                                                sam9x7_plls[i][j].c,
>> +                                                                sam9x7_plls[i][j].l,
>> +                                                                sam9x7_plls[i][j].f);
>> +                             break;
>> +
>> +                     case PLL_TYPE_DIV:
>> +                             hw = sam9x60_clk_register_div_pll(regmap,
>> +                                                               &pmc_pll_lock,
>> +                                                               sam9x7_plls[i][j].n,
>> +                                                               sam9x7_plls[i][j].p, NULL, i,
>> +                                                               sam9x7_plls[i][j].c,
>> +                                                               sam9x7_plls[i][j].l,
>> +                                                               sam9x7_plls[i][j].f, 0);
>> +                             break;
>> +
>> +                     default:
>> +                             continue;
>> +                     }
>> +
>> +                     if (IS_ERR(hw))
>> +                             goto err_free;
>> +
>> +                     if (sam9x7_plls[i][j].eid)
>> +                             sam9x7_pmc->chws[sam9x7_plls[i][j].eid] = hw;
>> +             }
>> +     }
>> +
>> +     parent_names[0] = md_slck_name;
>> +     parent_names[1] = "mainck";
>> +     parent_names[2] = "plla_divpmcck";
>> +     parent_names[3] = "upll_divpmcck";
>> +     hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
>> +                                        parent_names, NULL, &sam9x7_master_layout,
>> +                                        &mck_characteristics, &mck_lock);
>> +     if (IS_ERR(hw))
>> +             goto err_free;
>> +
>> +     hw = at91_clk_register_master_div(regmap, "masterck_div",
>> +                                       "masterck_pres", NULL, &sam9x7_master_layout,
>> +                                       &mck_characteristics, &mck_lock,
>> +                                       CLK_SET_RATE_GATE, 0);
>> +     if (IS_ERR(hw))
>> +             goto err_free;
>> +
>> +     sam9x7_pmc->chws[PMC_MCK] = hw;
>> +
>> +     parent_names[0] = "plla_divpmcck";
>> +     parent_names[1] = "upll_divpmcck";
>> +     parent_names[2] = "main_osc";
>> +     hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
>> +     if (IS_ERR(hw))
>> +             goto err_free;
>> +
>> +     parent_names[0] = md_slck_name;
>> +     parent_names[1] = td_slck_name;
>> +     parent_names[2] = "mainck";
>> +     parent_names[3] = "masterck_div";
>> +     parent_names[4] = "plla_divpmcck";
>> +     parent_names[5] = "upll_divpmcck";
>> +     parent_names[6] = "audiopll_divpmcck";
>> +     for (i = 0; i < 2; i++) {
>> +             char name[6];
>> +
>> +             snprintf(name, sizeof(name), "prog%d", i);
>> +
>> +             hw = at91_clk_register_programmable(regmap, name,
>> +                                                 parent_names, NULL, 7, i,
>> +                                                 &sam9x7_programmable_layout,
>> +                                                 NULL);
>> +             if (IS_ERR(hw))
>> +                     goto err_free;
>> +
>> +             sam9x7_pmc->pchws[i] = hw;
>> +     }
>> +
>> +     for (i = 0; i < ARRAY_SIZE(sam9x7_systemck); i++) {
>> +             hw = at91_clk_register_system(regmap, sam9x7_systemck[i].n,
>> +                                           sam9x7_systemck[i].p, NULL,
>> +                                           sam9x7_systemck[i].id,
>> +                                           sam9x7_systemck[i].flags);
>> +             if (IS_ERR(hw))
>> +                     goto err_free;
>> +
>> +             sam9x7_pmc->shws[sam9x7_systemck[i].id] = hw;
>> +     }
>> +
>> +     for (i = 0; i < ARRAY_SIZE(sam9x7_periphck); i++) {
>> +             hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
>> +                                                      &sam9x7_pcr_layout,
>> +                                                      sam9x7_periphck[i].n,
>> +                                                      "masterck_div", NULL,
>> +                                                      sam9x7_periphck[i].id,
>> +                                                      &range, INT_MIN,
>> +                                                      sam9x7_periphck[i].f);
>> +             if (IS_ERR(hw))
>> +                     goto err_free;
>> +
>> +             sam9x7_pmc->phws[sam9x7_periphck[i].id] = hw;
>> +     }
>> +
>> +     parent_names[0] = md_slck_name;
>> +     parent_names[1] = td_slck_name;
>> +     parent_names[2] = "mainck";
>> +     parent_names[3] = "masterck_div";
>> +     for (i = 0; i < ARRAY_SIZE(sam9x7_gck); i++) {
>> +             u8 num_parents = 4 + sam9x7_gck[i].pp_count;
>> +             u32 *mux_table;
>> +
>> +             mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
>> +                                       GFP_KERNEL);
>> +             if (!mux_table)
>> +                     goto err_free;
>> +
>> +             PMC_INIT_TABLE(mux_table, 4);
>> +             PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table,
>> +                            sam9x7_gck[i].pp_count);
>> +             PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp,
>> +                            sam9x7_gck[i].pp_count);
>> +
>> +             hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
>> +                                              &sam9x7_pcr_layout,
>> +                                              sam9x7_gck[i].n,
>> +                                              parent_names, NULL, mux_table,
>> +                                              num_parents,
>> +                                              sam9x7_gck[i].id,
>> +                                              &sam9x7_gck[i].r,
>> +                                              sam9x7_gck[i].pp_chg_id);
>> +             if (IS_ERR(hw))
>> +                     goto err_free;
>> +
>> +             sam9x7_pmc->ghws[sam9x7_gck[i].id] = hw;
>> +             clk_mux_buffer[clk_mux_buffer_size++] = mux_table;
>> +     }
>> +
>> +     of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x7_pmc);
>> +     kfree(clk_mux_buffer);
>> +
>> +     return;
>> +
>> +err_free:
>> +     if (clk_mux_buffer) {
>> +             for (i = 0; i < clk_mux_buffer_size; i++)
>> +                     kfree(clk_mux_buffer[i]);
>> +             kfree(clk_mux_buffer);
>> +     }
>> +     kfree(sam9x7_pmc);
>> +}
>> +
>> +/* Some clks are used for a clocksource */
>> +CLK_OF_DECLARE(sam9x7_pmc, "microchip,sam9x7-pmc", sam9x7_pmc_setup);

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH v5 13/27] clk: at91: sam9x7: add sam9x7 pmc driver

[claudiu beznea]

Hi, Varshini,

On 15.07.2024 09:46, Varshini.Rajendran@microchip.com wrote:
> Hi Claudiu,
> 
> On 14/07/24 7:25 pm, claudiu beznea wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Hi, Varshini,
>>
>> On 03.07.2024 13:28, Varshini Rajendran wrote:
>>> Add a driver for the PMC clocks of sam9x7 Soc family.
>>>
>>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>>> ---
>>>   drivers/clk/at91/Makefile |   1 +
>>>   drivers/clk/at91/sam9x7.c | 946 ++++++++++++++++++++++++++++++++++++++
>>>   2 files changed, 947 insertions(+)
>>>   create mode 100644 drivers/clk/at91/sam9x7.c
>>>

...

>>> +     for (i = 0; i < PLL_ID_MAX; i++) {
>>> +             for (j = 0; j < 3; j++) {
>>
>> I now realize that we are alocating more than needed memory for each PLL in
>> sam9x7_plls[][]. The number of columns for the 2d array is PLL_ID_MAX and
>> it should be 3. I can adjust it when applying but I need you to run a
>> simple boot test with it.
>>
> Yes. It boots and works perfectly with the change suggested. I am 
> pasting the snippet below just to be on the same page.
> 
> --- a/drivers/clk/at91/sam9x7.c
> +++ b/drivers/clk/at91/sam9x7.c
> @@ -198,7 +198,7 @@ static const struct {
>          const struct clk_pll_characteristics *c;
>          unsigned long f;
>          u8 eid;
> -} sam9x7_plls[][PLL_ID_MAX] = {
> +} sam9x7_plls[][3] = {

Great! Thank you!

[PATCH v5 14/27] dt-bindings: interrupt-controller: Add support for sam9x7 aic

[Varshini Rajendran]

Document the support added for the Advanced interrupt controller(AIC)
chip in the sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Adapted the patch to the new yaml file.
- Removed the Acked-by tag due to the TXT to schema change.
---
 .../bindings/interrupt-controller/atmel,aic.yaml | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
index d4658fe3867c..9c5af9dbcb6e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
@@ -17,12 +17,16 @@ description:
 
 properties:
   compatible:
-    enum:
-      - atmel,at91rm9200-aic
-      - atmel,sama5d2-aic
-      - atmel,sama5d3-aic
-      - atmel,sama5d4-aic
-      - microchip,sam9x60-aic
+    oneOf:
+      - enum:
+          - atmel,at91rm9200-aic
+          - atmel,sama5d2-aic
+          - atmel,sama5d3-aic
+          - atmel,sama5d4-aic
+          - microchip,sam9x60-aic
+      - items:
+          - const: microchip,sam9x7-aic
+          - const: microchip,sam9x60-aic
 
   reg:
     maxItems: 1
-- 
2.25.1

Re: [PATCH v5 14/27] dt-bindings: interrupt-controller: Add support for sam9x7 aic

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 307 bytes --]

On Wed, Jul 03, 2024 at 03:58:06PM +0530, Varshini Rajendran wrote:
> Document the support added for the Advanced interrupt controller(AIC)
> chip in the sam9x7 SoC family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
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[PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Varshini Rajendran]

Add the description and conditions to the device tree documentation
for the property microchip,nr-irqs.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
index 9c5af9dbcb6e..06e5f92e7d53 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
@@ -54,6 +54,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32-array
     description: u32 array of external irqs.
 
+  microchip,nr-irqs:
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    description: u32 array of nr_irqs.
+
 allOf:
   - $ref: /schemas/interrupt-controller.yaml#
   - if:
@@ -71,6 +75,14 @@ allOf:
         atmel,external-irqs:
           minItems: 1
           maxItems: 1
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: microchip,sam9x7-aic
+    then:
+      required:
+        - microchip,nr-irqs
 
 required:
   - compatible
-- 
2.25.1

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1663 bytes --]

On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> Add the description and conditions to the device tree documentation
> for the property microchip,nr-irqs.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

This needs to be part of patch 14.

> ---
>  .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> index 9c5af9dbcb6e..06e5f92e7d53 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> @@ -54,6 +54,10 @@ properties:
>      $ref: /schemas/types.yaml#/definitions/uint32-array
>      description: u32 array of external irqs.
>  
> +  microchip,nr-irqs:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description: u32 array of nr_irqs.

This makes no sense, did you just copy from above? Why would the number
of irqs be an array? Why can't you determine this from the compatble?

Thanks,
Conor.

> +
>  allOf:
>    - $ref: /schemas/interrupt-controller.yaml#
>    - if:
> @@ -71,6 +75,14 @@ allOf:
>          atmel,external-irqs:
>            minItems: 1
>            maxItems: 1
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: microchip,sam9x7-aic
> +    then:
> +      required:
> +        - microchip,nr-irqs
>  
>  required:
>    - compatible
> -- 
> 2.25.1
> 

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Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Varshini.Rajendran]

On 03/07/24 9:11 pm, Conor Dooley wrote:
> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
>> Add the description and conditions to the device tree documentation
>> for the property microchip,nr-irqs.
>>
>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
> This needs to be part of patch 14.
> 
>> ---
>>   .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>> index 9c5af9dbcb6e..06e5f92e7d53 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>> @@ -54,6 +54,10 @@ properties:
>>       $ref: /schemas/types.yaml#/definitions/uint32-array
>>       description: u32 array of external irqs.
>>   
>> +  microchip,nr-irqs:
>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>> +    description: u32 array of nr_irqs.
> This makes no sense, did you just copy from above? Why would the number
> of irqs be an array? Why can't you determine this from the compatble?
> 
Sorry for the bad description. I will correct it in the next version.

For the second part of the question, this change was done as a step to 
resolve having a new compatible while having practically the same IP 
pointed out in the v3 of the series [1]. It is kind of looping back to 
the initial idea now. Even if this is added as a driver data, it 
overrides the expectation from the comment in [1]. Please suggest. I 
also read Rob's concerns on having a device tree property for number of 
irqs.

[1] 
https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/

> Thanks,
> Conor.
> 
>> +
>>   allOf:
>>     - $ref: /schemas/interrupt-controller.yaml#
>>     - if:
>> @@ -71,6 +75,14 @@ allOf:
>>           atmel,external-irqs:
>>             minItems: 1
>>             maxItems: 1
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: microchip,sam9x7-aic
>> +    then:
>> +      required:
>> +        - microchip,nr-irqs
>>   
>>   required:
>>     - compatible
>> -- 
>> 2.25.1
>>

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Nicolas.Ferre]

On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
> On 03/07/24 9:11 pm, Conor Dooley wrote:
>> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
>>> Add the description and conditions to the device tree documentation
>>> for the property microchip,nr-irqs.
>>>
>>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
>> This needs to be part of patch 14.
>>
>>> ---
>>>    .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>>>    1 file changed, 12 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>> index 9c5af9dbcb6e..06e5f92e7d53 100644
>>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>> @@ -54,6 +54,10 @@ properties:
>>>        $ref: /schemas/types.yaml#/definitions/uint32-array
>>>        description: u32 array of external irqs.
>>>    
>>> +  microchip,nr-irqs:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>>> +    description: u32 array of nr_irqs.
>> This makes no sense, did you just copy from above? Why would the number
>> of irqs be an array? Why can't you determine this from the compatble?
>>
> Sorry for the bad description. I will correct it in the next version.
> 
> For the second part of the question, this change was done as a step to
> resolve having a new compatible while having practically the same IP
> pointed out in the v3 of the series [1]. It is kind of looping back to
> the initial idea now. Even if this is added as a driver data, it
> overrides the expectation from the comment in [1]. Please suggest. I

In your v3 patch, indeed you were extracting the number of IRQs from the 
compatibility string (aka, from device tree...). It's my preferred 
solution as well.

So, come back to v3 [1] and address what Conor said in v4 "...having 
specific $soc_aic5_of_init() functions for each SoC seems silly when 
usually only the number of interrupts changes. The number of IRQs could 
be in the match data and you could use aic5_of_init in your 
IRQCHIP_DECLARE directly"

I think that we can convince Marc/Thomas that it's the best option as it 
prevents introducing another non-standard property to the DT, break the 
ABI (and was used happily for years).

Best regards,
   Nicolas

[1]
https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/


> also read Rob's concerns on having a device tree property for number of
> irqs.
> 
> [1]
> https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/
> 
>> Thanks,
>> Conor.
>>
>>> +
>>>    allOf:
>>>      - $ref: /schemas/interrupt-controller.yaml#
>>>      - if:
>>> @@ -71,6 +75,14 @@ allOf:
>>>            atmel,external-irqs:
>>>              minItems: 1
>>>              maxItems: 1
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: microchip,sam9x7-aic
>>> +    then:
>>> +      required:
>>> +        - microchip,nr-irqs
>>>    
>>>    required:
>>>      - compatible
>>> -- 
>>> 2.25.1
>>>
> 

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Nicolas.Ferre]

On 09/07/2024 at 16:06, Nicolas.Ferre@microchip.com wrote:
> On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:

[..]

> I think that we can convince Marc/Thomas that it's the best option as it
> prevents introducing another non-standard property to the DT, break the
> ABI (and was used happily for years).

s/break the/does not break the/

> Best regards,
>     Nicolas
(sorry for the noise)

[..]

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Marc Zyngier]

On Tue, 09 Jul 2024 15:06:29 +0100,
<Nicolas.Ferre@microchip.com> wrote:
> 
> On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
> > On 03/07/24 9:11 pm, Conor Dooley wrote:
> >> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> >>> Add the description and conditions to the device tree documentation
> >>> for the property microchip,nr-irqs.
> >>>
> >>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
> >> This needs to be part of patch 14.
> >>
> >>> ---
> >>>    .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
> >>>    1 file changed, 12 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> >>> index 9c5af9dbcb6e..06e5f92e7d53 100644
> >>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> >>> @@ -54,6 +54,10 @@ properties:
> >>>        $ref: /schemas/types.yaml#/definitions/uint32-array
> >>>        description: u32 array of external irqs.
> >>>    
> >>> +  microchip,nr-irqs:
> >>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> >>> +    description: u32 array of nr_irqs.
> >> This makes no sense, did you just copy from above? Why would the number
> >> of irqs be an array? Why can't you determine this from the compatble?
> >>
> > Sorry for the bad description. I will correct it in the next version.
> > 
> > For the second part of the question, this change was done as a step to
> > resolve having a new compatible while having practically the same IP
> > pointed out in the v3 of the series [1]. It is kind of looping back to
> > the initial idea now. Even if this is added as a driver data, it
> > overrides the expectation from the comment in [1]. Please suggest. I
> 
> In your v3 patch, indeed you were extracting the number of IRQs from the 
> compatibility string (aka, from device tree...). It's my preferred 
> solution as well.
> 
> So, come back to v3 [1] and address what Conor said in v4 "...having 
> specific $soc_aic5_of_init() functions for each SoC seems silly when 
> usually only the number of interrupts changes. The number of IRQs could 
> be in the match data and you could use aic5_of_init in your 
> IRQCHIP_DECLARE directly"
> 
> I think that we can convince Marc/Thomas that it's the best option as it 
> prevents introducing another non-standard property to the DT, break the 
> ABI (and was used happily for years).

In general, the least cruft we add to the DT after the facts, the
better. If the compatible string is good enough to identify the
device, I don't think we need to overthink it, specially as there is
no upside to non-standard properties here -- from what I understand,
the number of available interrupts is a property of the HW, and not
something that can be configured, making it part of the programming
model, just like the layout of registers.

But I'm not in a deciding position anymore, and this is only my
(educated) opinion.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Nicolas Ferre]

Answering to myself (again) and to Conor...

On 09/07/2024 at 16:06, Nicolas.Ferre@microchip.com wrote:
> On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
>> On 03/07/24 9:11 pm, Conor Dooley wrote:
>>> On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
>>>> Add the description and conditions to the device tree documentation
>>>> for the property microchip,nr-irqs.
>>>>
>>>> Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
>>> This needs to be part of patch 14.
>>>
>>>> ---
>>>>     .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
>>>>     1 file changed, 12 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>>> index 9c5af9dbcb6e..06e5f92e7d53 100644
>>>> --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
>>>> @@ -54,6 +54,10 @@ properties:
>>>>         $ref: /schemas/types.yaml#/definitions/uint32-array
>>>>         description: u32 array of external irqs.
>>>>     
>>>> +  microchip,nr-irqs:
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32-array
>>>> +    description: u32 array of nr_irqs.
>>> This makes no sense, did you just copy from above? Why would the number
>>> of irqs be an array? Why can't you determine this from the compatble?
>>>
>> Sorry for the bad description. I will correct it in the next version.
>>
>> For the second part of the question, this change was done as a step to
>> resolve having a new compatible while having practically the same IP
>> pointed out in the v3 of the series [1]. It is kind of looping back to
>> the initial idea now. Even if this is added as a driver data, it
>> overrides the expectation from the comment in [1]. Please suggest. I
> 
> In your v3 patch, indeed you were extracting the number of IRQs from the
> compatibility string (aka, from device tree...). It's my preferred
> solution as well.
> 
> So, come back to v3 [1] and address what Conor said in v4 "...having
> specific $soc_aic5_of_init() functions for each SoC seems silly when
> usually only the number of interrupts changes. The number of IRQs could
> be in the match data and you could use aic5_of_init in your
> IRQCHIP_DECLARE directly"

Well, after a brief talk with Varshini and a review of the code, I'm not 
so sure it's worth re-writing this part anymore Conor...
It'll need changing 3-4 files (2 drivers and the "common" .h/.c files, 
because of the type change of ".data"); handling the special case of 
sama5d2 (smr_cache thing) and touching lot more code than what is done 
in v3 of this patch series.

Original design was probably not optimal, but well, it's simple, 
understandable and except if there is a big benefit in moving, I would 
prefer to keep it like this.
If you agree, we can ask Varshini to re-post a separated IRQ-focused 
series for handling sam9x75 changes.

Best regards,
   Nicolas

> I think that we can convince Marc/Thomas that it's the best option as it
> prevents introducing another non-standard property to the DT, does not break
> the ABI (and was used happily for years).
> 
> Best regards,
>     Nicolas
> 
> [1]
> https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/
> 
> 
>> also read Rob's concerns on having a device tree property for number of
>> irqs.
>>
>> [1]
>> https://lore.kernel.org/lkml/87ee1e3c365686bc60e92ba3972dc1a5@kernel.org/
>>
>>> Thanks,
>>> Conor.
>>>
>>>> +
>>>>     allOf:
>>>>       - $ref: /schemas/interrupt-controller.yaml#
>>>>       - if:
>>>> @@ -71,6 +75,14 @@ allOf:
>>>>             atmel,external-irqs:
>>>>               minItems: 1
>>>>               maxItems: 1
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            const: microchip,sam9x7-aic
>>>> +    then:
>>>> +      required:
>>>> +        - microchip,nr-irqs
>>>>     
>>>>     required:
>>>>       - compatible
>>>> -- 
>>>> 2.25.1
>>>>
>>
> 

Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3564 bytes --]

On Thu, Jul 11, 2024 at 02:42:01PM +0200, Nicolas Ferre wrote:
> Answering to myself (again) and to Conor...
> 
> On 09/07/2024 at 16:06, Nicolas.Ferre@microchip.com wrote:
> > On 09/07/2024 at 08:13, Varshini Rajendran - I67070 wrote:
> > > On 03/07/24 9:11 pm, Conor Dooley wrote:
> > > > On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> > > > > Add the description and conditions to the device tree documentation
> > > > > for the property microchip,nr-irqs.
> > > > > 
> > > > > Signed-off-by: Varshini Rajendran<varshini.rajendran@microchip.com>
> > > > This needs to be part of patch 14.
> > > > 
> > > > > ---
> > > > >     .../bindings/interrupt-controller/atmel,aic.yaml     | 12 ++++++++++++
> > > > >     1 file changed, 12 insertions(+)
> > > > > 
> > > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> > > > > index 9c5af9dbcb6e..06e5f92e7d53 100644
> > > > > --- a/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> > > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.yaml
> > > > > @@ -54,6 +54,10 @@ properties:
> > > > >         $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > >         description: u32 array of external irqs.
> > > > > +  microchip,nr-irqs:
> > > > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > +    description: u32 array of nr_irqs.
> > > > This makes no sense, did you just copy from above? Why would the number
> > > > of irqs be an array? Why can't you determine this from the compatble?
> > > > 
> > > Sorry for the bad description. I will correct it in the next version.
> > > 
> > > For the second part of the question, this change was done as a step to
> > > resolve having a new compatible while having practically the same IP
> > > pointed out in the v3 of the series [1]. It is kind of looping back to
> > > the initial idea now. Even if this is added as a driver data, it
> > > overrides the expectation from the comment in [1]. Please suggest. I
> > 
> > In your v3 patch, indeed you were extracting the number of IRQs from the
> > compatibility string (aka, from device tree...). It's my preferred
> > solution as well.
> > 
> > So, come back to v3 [1] and address what Conor said in v4 "...having
> > specific $soc_aic5_of_init() functions for each SoC seems silly when
> > usually only the number of interrupts changes. The number of IRQs could
> > be in the match data and you could use aic5_of_init in your
> > IRQCHIP_DECLARE directly"
> 
> Well, after a brief talk with Varshini and a review of the code, I'm not so
> sure it's worth re-writing this part anymore Conor...
> It'll need changing 3-4 files (2 drivers and the "common" .h/.c files,
> because of the type change of ".data"); handling the special case of sama5d2
> (smr_cache thing) and touching lot more code than what is done in v3 of this
> patch series.
> 
> Original design was probably not optimal, but well, it's simple,
> understandable and except if there is a big benefit in moving, I would
> prefer to keep it like this.
> If you agree, we can ask Varshini to re-post a separated IRQ-focused series
> for handling sam9x75 changes.

I dunno, it's up to the folks that care about the driver whether they
want to do restructuring, not me. The nr-irqs property stays NAKed though,
since the information is determinable from the compatible.

Thanks,
Conor.

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Re: [PATCH v5 15/27] dt-bindings: interrupt-controller: Document the property microchip,nr-irqs

[Rob Herring]

On Wed, Jul 03, 2024 at 03:58:14PM +0530, Varshini Rajendran wrote:
> Add the description and conditions to the device tree documentation
> for the property microchip,nr-irqs.

Why?

Of *all* the other interrupt controller bindings, do you see a property 
for number of interrupts? No (well, maybe a few slipped in). You 
shouldn't need one either.

Rob

[PATCH v5 16/27] irqchip/atmel-aic5: Add support to get nr_irqs from DT for sam9x60 & sam9x7

[Varshini Rajendran]

Add support to get number of IRQs from the respective DT node for sam9x60
and sam9x7 devices. Since only this factor differs between the two SoCs,
this patch adds support for the same. The macro is still used as a
fallback for the sake of old sam9x60 DTs to work so that there is no ABI
breakage. The property is a enforced as a requirement for sam9x7 alone.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Changed the ABI breaking code.
- Added sam9x60 NR_IRQ as fallback for older DTS to work.
---
 drivers/irqchip/irq-atmel-aic5.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index 145535bd7560..164b5a9b0f9b 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -403,6 +403,12 @@ IRQCHIP_DECLARE(sama5d4_aic5, "atmel,sama5d4-aic", sama5d4_aic5_of_init);
 static int __init sam9x60_aic5_of_init(struct device_node *node,
 				       struct device_node *parent)
 {
-	return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
+	int ret, nr_irqs;
+
+	ret = of_property_read_u32(node, "microchip,nr-irqs", &nr_irqs);
+	if (ret)
+		return aic5_of_init(node, parent, NR_SAM9X60_IRQS);
+
+	return aic5_of_init(node, parent, nr_irqs);
 }
 IRQCHIP_DECLARE(sam9x60_aic5, "microchip,sam9x60-aic", sam9x60_aic5_of_init);
-- 
2.25.1

[PATCH v5 18/27] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[Varshini Rajendran]

Use sam9x7 pmc's compatible to lookup for in the SHDWC driver.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
index 959ce0dbe91d..2121d7e74e12 100644
--- a/drivers/power/reset/at91-sama5d2_shdwc.c
+++ b/drivers/power/reset/at91-sama5d2_shdwc.c
@@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
 	{ .compatible = "atmel,sama5d2-pmc" },
 	{ .compatible = "microchip,sam9x60-pmc" },
 	{ .compatible = "microchip,sama7g5-pmc" },
+	{ .compatible = "microchip,sam9x7-pmc" },
 	{ /* Sentinel. */ }
 };
 
-- 
2.25.1

Re: [PATCH v5 18/27] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7

[claudiu beznea]

On 03.07.2024 13:28, Varshini Rajendran wrote:
> Use sam9x7 pmc's compatible to lookup for in the SHDWC driver.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

The suggestion from v4 still applies to avoid increasing this array.

> ---
>  drivers/power/reset/at91-sama5d2_shdwc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/power/reset/at91-sama5d2_shdwc.c b/drivers/power/reset/at91-sama5d2_shdwc.c
> index 959ce0dbe91d..2121d7e74e12 100644
> --- a/drivers/power/reset/at91-sama5d2_shdwc.c
> +++ b/drivers/power/reset/at91-sama5d2_shdwc.c
> @@ -326,6 +326,7 @@ static const struct of_device_id at91_pmc_ids[] = {
>  	{ .compatible = "atmel,sama5d2-pmc" },
>  	{ .compatible = "microchip,sam9x60-pmc" },
>  	{ .compatible = "microchip,sama7g5-pmc" },
> +	{ .compatible = "microchip,sam9x7-pmc" },
>  	{ /* Sentinel. */ }
>  };
>  

[PATCH v5 21/27] dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7

[Varshini Rajendran]

Add documentation for SAM9X7 reset controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 .../devicetree/bindings/reset/atmel,at91sam9260-reset.yaml    | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
index 98465d26949e..c3b33bbc7319 100644
--- a/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
+++ b/Documentation/devicetree/bindings/reset/atmel,at91sam9260-reset.yaml
@@ -26,6 +26,10 @@ properties:
       - items:
           - const: atmel,sama5d3-rstc
           - const: atmel,at91sam9g45-rstc
+      - items:
+          - enum:
+              - microchip,sam9x7-rstc
+          - const: microchip,sam9x60-rstc
 
   reg:
     minItems: 1
-- 
2.25.1

[PATCH v5 22/27] dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7

[Varshini Rajendran]

Add shutdown controller DT bindings.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 .../devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml   | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
index 8c58e12cdb60..0735ceb7c103 100644
--- a/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
+++ b/Documentation/devicetree/bindings/power/reset/atmel,sama5d2-shdwc.yaml
@@ -22,6 +22,9 @@ properties:
       - enum:
           - atmel,sama5d2-shdwc
           - microchip,sam9x60-shdwc
+      - items:
+          - const: microchip,sam9x7-shdwc
+          - const: microchip,sam9x60-shdwc
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH v5 23/27] ARM: at91: Kconfig: add config flag for SAM9X7 SoC

[Varshini Rajendran]

Add config flag for sam9x7 SoC.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
---
Changes in v5:
- Removed the unused SDRAMC flag
---
 arch/arm/mach-at91/Kconfig | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index a8c022b4c053..344f5305f69a 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -141,11 +141,27 @@ config SOC_SAM9X60
 	help
 	  Select this if you are using Microchip's SAM9X60 SoC
 
+config SOC_SAM9X7
+	bool "SAM9X7"
+	depends on ARCH_MULTI_V5
+	select ATMEL_AIC5_IRQ
+	select ATMEL_PM if PM
+	select CPU_ARM926T
+	select HAVE_AT91_USB_CLK
+	select HAVE_AT91_GENERATED_CLK
+	select HAVE_AT91_SAM9X60_PLL
+	select MEMORY
+	select PINCTRL_AT91
+	select SOC_SAM_V4_V5
+	select SRAM if PM
+	help
+	  Select this if you are using Microchip's SAM9X7 SoC
+
 comment "Clocksource driver selection"
 
 config ATMEL_CLOCKSOURCE_PIT
 	bool "Periodic Interval Timer (PIT) support"
-	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+	depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	default SOC_AT91SAM9 || SOC_SAMA5
 	select ATMEL_PIT
 	help
@@ -155,7 +171,7 @@ config ATMEL_CLOCKSOURCE_PIT
 
 config ATMEL_CLOCKSOURCE_TCB
 	bool "Timer Counter Blocks (TCB) support"
-	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
+	default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA5
 	select ATMEL_TCB_CLKSRC
 	help
 	  Select this to get a high precision clocksource based on a
@@ -166,7 +182,7 @@ config ATMEL_CLOCKSOURCE_TCB
 
 config MICROCHIP_CLOCKSOURCE_PIT64B
 	bool "64-bit Periodic Interval Timer (PIT64B) support"
-	default SOC_SAM9X60 || SOC_SAMA7
+	default SOC_SAM9X60 || SOC_SAM9X7 || SOC_SAMA7
 	select MICROCHIP_PIT64B
 	help
 	  Select this to get a high resolution clockevent (SAM9X60) or
-- 
2.25.1

[PATCH v5 24/27] ARM: configs: at91: enable config flags for sam9x7 SoC family

[Varshini Rajendran]

Enable config flags for SAM9X7 SoC for the sam9x7 SoC family.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
 arch/arm/configs/at91_dt_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 1d53aec4c836..880f0c0f4cc3 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -16,6 +16,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_SOC_AT91RM9200=y
 CONFIG_SOC_AT91SAM9=y
 CONFIG_SOC_SAM9X60=y
+CONFIG_SOC_SAM9X7=y
 # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
 CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
-- 
2.25.1

Re: [PATCH v5 24/27] ARM: configs: at91: enable config flags for sam9x7 SoC family

[claudiu beznea]

On 03.07.2024 13:29, Varshini Rajendran wrote:
> Enable config flags for SAM9X7 SoC for the sam9x7 SoC family.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
>  arch/arm/configs/at91_dt_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
> index 1d53aec4c836..880f0c0f4cc3 100644
> --- a/arch/arm/configs/at91_dt_defconfig
> +++ b/arch/arm/configs/at91_dt_defconfig
> @@ -16,6 +16,7 @@ CONFIG_ARCH_AT91=y
>  CONFIG_SOC_AT91RM9200=y
>  CONFIG_SOC_AT91SAM9=y
>  CONFIG_SOC_SAM9X60=y
> +CONFIG_SOC_SAM9X7=y
>  # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
>  CONFIG_AEABI=y
>  CONFIG_UACCESS_WITH_MEMCPY=y

[PATCH v5 26/27] dt-bindings: arm: add sam9x75 curiosity board

[Varshini Rajendran]

Add documentation for SAM9X75 Curiosity board.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v5:
- Updated Acked-by tag.
---
 Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
index 82f37328cc69..7160ec80ac1b 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
@@ -106,6 +106,12 @@ properties:
           - const: microchip,sam9x60
           - const: atmel,at91sam9
 
+      - description: Microchip SAM9X7 Evaluation Boards
+        items:
+          - const: microchip,sam9x75-curiosity
+          - const: microchip,sam9x7
+          - const: atmel,at91sam9
+
       - description: Nattis v2 board with Natte v2 power board
         items:
           - const: axentia,nattis-2
-- 
2.25.1

Re: [PATCH v5 26/27] dt-bindings: arm: add sam9x75 curiosity board

[claudiu beznea]

On 03.07.2024 13:29, Varshini Rajendran wrote:
> Add documentation for SAM9X75 Curiosity board.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> Acked-by: Rob Herring <robh@kernel.org>

Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

> ---
> Changes in v5:
> - Updated Acked-by tag.
> ---
>  Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> index 82f37328cc69..7160ec80ac1b 100644
> --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml
> @@ -106,6 +106,12 @@ properties:
>            - const: microchip,sam9x60
>            - const: atmel,at91sam9
>  
> +      - description: Microchip SAM9X7 Evaluation Boards
> +        items:
> +          - const: microchip,sam9x75-curiosity
> +          - const: microchip,sam9x7
> +          - const: atmel,at91sam9
> +
>        - description: Nattis v2 board with Natte v2 power board
>          items:
>            - const: axentia,nattis-2

[PATCH v5 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

[Varshini Rajendran]

Add device tree file for sam9x75 curiosity board.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
---
Changes in v5:
- Update commit message to match the directory structure.
- Alphanumerically sorted Makefile entries.
- Corrected VDDCore minimum voltage.
- Enabled the i2s node.
- Removed additional blank lines.
- Enclosed each entry with separate <>.
- Corrected pinctrl names to match Microchip convention.
- Enabled slewrate in sdmmc node.
- Corrected pinmux mask.
- Added phandle to leds for ease of access with upcoming device entries.
- Updated gpio pin number for red led.
---
 arch/arm/boot/dts/microchip/Makefile          |   3 +
 .../dts/microchip/at91-sam9x75_curiosity.dts  | 312 ++++++++++++++++++
 2 files changed, 315 insertions(+)
 create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts

diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
index 0c45c8d17468..470fe46433a9 100644
--- a/arch/arm/boot/dts/microchip/Makefile
+++ b/arch/arm/boot/dts/microchip/Makefile
@@ -2,6 +2,7 @@
 # Enables support for device-tree overlays
 DTC_FLAGS_at91-sam9x60_curiosity := -@
 DTC_FLAGS_at91-sam9x60ek := -@
+DTC_FLAGS_at91-sam9x75_curiosity := -@
 DTC_FLAGS_at91-sama5d27_som1_ek := -@
 DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
 DTC_FLAGS_at91-sama5d29_curiosity := -@
@@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
 dtb-$(CONFIG_SOC_SAM9X60) += \
 	at91-sam9x60_curiosity.dtb \
 	at91-sam9x60ek.dtb
+dtb-$(CONFIG_SOC_SAM9X7) += \
+	at91-sam9x75_curiosity.dtb
 dtb-$(CONFIG_SOC_SAM_V7) += \
 	at91-kizbox2-2.dtb \
 	at91-kizbox3-hs.dtb \
diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
new file mode 100644
index 000000000000..4a4f14f13634
--- /dev/null
+++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
@@ -0,0 +1,312 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
+ *
+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
+ */
+/dts-v1/;
+#include "sam9x7.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "Microchip SAM9X75 Curiosity";
+	compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
+
+	aliases {
+		i2c0 = &i2c6;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+		button-user {
+			label = "USER";
+			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_0>;
+			wakeup-source;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_red: led-red {
+			label = "red";
+			gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&pinctrl_red_led_gpio_default>;
+		};
+
+		led_green: led-green {
+			label = "green";
+			gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&pinctrl_green_led_gpio_default>;
+		};
+
+		led_blue: led-blue {
+			label = "blue";
+			gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
+			pinctrl-0 = <&pinctrl_blue_led_gpio_default>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	memory@20000000 {
+		reg = <0x20000000 0x10000000>;
+		device_type = "memory";
+	};
+};
+
+&classd {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_classd_default>;
+	atmel,pwm-type = "diff";
+	atmel,non-overlap-time = <10>;
+	status = "okay";
+};
+
+&dbgu {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_dbgu_default>;
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
+
+&flx6 {
+	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+	status = "okay";
+};
+
+&i2c6 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flx6_default>;
+	i2c-analog-filter;
+	i2c-digital-filter;
+	i2c-digital-filter-width-ns = <35>;
+	status = "okay";
+
+	pmic@5b {
+		compatible = "microchip,mcp16502";
+		reg = <0x5b>;
+
+		regulators {
+			vdd_3v3: VDD_IO {
+				regulator-name = "VDD_IO";
+				regulator-min-microvolt = <3000000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vddioddr: VDD_DDR {
+				regulator-name = "VDD_DDR";
+				regulator-min-microvolt = <1283000>;
+				regulator-max-microvolt = <1450000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+			};
+
+			vddcore: VDD_CORE {
+				regulator-name = "VDD_CORE";
+				regulator-min-microvolt = <1140000>;
+				regulator-max-microvolt = <1210000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vddcpu: VDD_OTHER {
+				regulator-name = "VDD_OTHER";
+				regulator-min-microvolt = <1700000>;
+				regulator-max-microvolt = <3600000>;
+				regulator-initial-mode = <2>;
+				regulator-allowed-modes = <2>, <4>;
+				regulator-ramp-delay = <3125>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+					regulator-mode = <4>;
+				};
+
+				regulator-state-mem {
+					regulator-mode = <4>;
+				};
+			};
+
+			vldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3700000>;
+				regulator-always-on;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vldo2: LDO2 {
+				regulator-name = "LDO2";
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <3700000>;
+
+				regulator-state-standby {
+					regulator-on-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2s_default>;
+	#sound-dai-cells = <0>;
+	status = "okay";
+};
+
+&main_xtal {
+	clock-frequency = <24000000>;
+};
+
+&pinctrl {
+	classd {
+		pinctrl_classd_default: classd-default {
+			atmel,pins =
+				<AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
+				<AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
+		};
+	};
+
+	dbgu {
+		pinctrl_dbgu_default: dbgu-default {
+			atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+				     <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+		};
+	};
+
+	flexcom {
+		pinctrl_flx6_default: flx6-default {
+			atmel,pins =
+				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+				<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+		};
+	};
+
+	gpio-keys {
+		pinctrl_key_gpio_default: key-gpio-default {
+			atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+
+	i2s {
+		pinctrl_i2s_default: i2s-default {
+			atmel,pins =
+				<AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SCK */
+				<AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SWS */
+				<AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDIN */
+				<AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDOUT */
+				<AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;		/* I2SMCK */
+		};
+	};
+
+	leds {
+		pinctrl_red_led_gpio_default: red-led-gpio-default {
+			atmel,pins = <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+		pinctrl_green_led_gpio_default: green-led-gpio-default {
+			atmel,pins = <AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+		pinctrl_blue_led_gpio_default: blue-led-gpio-default {
+			atmel,pins = <AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+		};
+	};
+
+	sdmmc0 {
+		pinctrl_sdmmc0_default: sdmmc0-default {
+			atmel,pins =
+				<AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,				/* PA2 CK  periph A with pullup */
+				<AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA1 CMD periph A with pullup */
+				<AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA0 DAT0 periph A */
+				<AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA3 DAT1 periph A with pullup */
+				<AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA4 DAT2 periph A with pullup */
+				<AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA5 DAT3 periph A with pullup */
+		};
+	};
+}; /* pinctrl */
+
+&rtt {
+	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sdmmc0_default>;
+	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
+	disable-wp;
+	status = "okay";
+};
+
+&slow_xtal {
+	clock-frequency = <32768>;
+};
+
+&poweroff {
+	debounce-delay-us = <976>;
+	status = "okay";
+
+	input@0 {
+		reg = <0>;
+	};
+};
+
+&trng {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
-- 
2.25.1

Re: [PATCH v5 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

[claudiu beznea]

Hi, Varshini,

On 03.07.2024 13:29, Varshini Rajendran wrote:
> Add device tree file for sam9x75 curiosity board.
> 
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> ---
> Changes in v5:
> - Update commit message to match the directory structure.
> - Alphanumerically sorted Makefile entries.
> - Corrected VDDCore minimum voltage.
> - Enabled the i2s node.
> - Removed additional blank lines.
> - Enclosed each entry with separate <>.
> - Corrected pinctrl names to match Microchip convention.
> - Enabled slewrate in sdmmc node.
> - Corrected pinmux mask.
> - Added phandle to leds for ease of access with upcoming device entries.
> - Updated gpio pin number for red led.
> ---
>  arch/arm/boot/dts/microchip/Makefile          |   3 +
>  .../dts/microchip/at91-sam9x75_curiosity.dts  | 312 ++++++++++++++++++
>  2 files changed, 315 insertions(+)
>  create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> 
> diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
> index 0c45c8d17468..470fe46433a9 100644
> --- a/arch/arm/boot/dts/microchip/Makefile
> +++ b/arch/arm/boot/dts/microchip/Makefile
> @@ -2,6 +2,7 @@
>  # Enables support for device-tree overlays
>  DTC_FLAGS_at91-sam9x60_curiosity := -@
>  DTC_FLAGS_at91-sam9x60ek := -@
> +DTC_FLAGS_at91-sam9x75_curiosity := -@
>  DTC_FLAGS_at91-sama5d27_som1_ek := -@
>  DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
>  DTC_FLAGS_at91-sama5d29_curiosity := -@
> @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>  dtb-$(CONFIG_SOC_SAM9X60) += \
>  	at91-sam9x60_curiosity.dtb \
>  	at91-sam9x60ek.dtb
> +dtb-$(CONFIG_SOC_SAM9X7) += \
> +	at91-sam9x75_curiosity.dtb
>  dtb-$(CONFIG_SOC_SAM_V7) += \
>  	at91-kizbox2-2.dtb \
>  	at91-kizbox3-hs.dtb \
> diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> new file mode 100644
> index 000000000000..4a4f14f13634
> --- /dev/null
> +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
> @@ -0,0 +1,312 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
> + *
> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +/dts-v1/;
> +#include "sam9x7.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	model = "Microchip SAM9X75 Curiosity";
> +	compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
> +
> +	aliases {
> +		i2c0 = &i2c6;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_key_gpio_default>;
> +
> +		button-user {
> +			label = "USER";
> +			gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
> +			linux,code = <KEY_0>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led_red: led-red {
> +			label = "red";
> +			gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
> +			pinctrl-0 = <&pinctrl_red_led_gpio_default>;
> +		};
> +
> +		led_green: led-green {
> +			label = "green";
> +			gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
> +			pinctrl-0 = <&pinctrl_green_led_gpio_default>;
> +		};
> +
> +		led_blue: led-blue {
> +			label = "blue";
> +			gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
> +			pinctrl-0 = <&pinctrl_blue_led_gpio_default>;
> +			linux,default-trigger = "heartbeat";
> +		};
> +	};
> +
> +	memory@20000000 {
> +		reg = <0x20000000 0x10000000>;
> +		device_type = "memory";
> +	};
> +};
> +
> +&classd {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_classd_default>;
> +	atmel,pwm-type = "diff";
> +	atmel,non-overlap-time = <10>;
> +	status = "okay";
> +};
> +
> +&dbgu {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_dbgu_default>;
> +	status = "okay";
> +};
> +
> +&dma0 {
> +	status = "okay";
> +};
> +
> +&flx6 {
> +	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
> +	status = "okay";
> +};
> +
> +&i2c6 {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flx6_default>;
> +	i2c-analog-filter;
> +	i2c-digital-filter;
> +	i2c-digital-filter-width-ns = <35>;
> +	status = "okay";
> +
> +	pmic@5b {
> +		compatible = "microchip,mcp16502";
> +		reg = <0x5b>;
> +
> +		regulators {
> +			vdd_3v3: VDD_IO {
> +				regulator-name = "VDD_IO";
> +				regulator-min-microvolt = <3000000>;
> +				regulator-max-microvolt = <3600000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddioddr: VDD_DDR {
> +				regulator-name = "VDD_DDR";
> +				regulator-min-microvolt = <1283000>;
> +				regulator-max-microvolt = <1450000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddcore: VDD_CORE {
> +				regulator-name = "VDD_CORE";
> +				regulator-min-microvolt = <1140000>;
> +				regulator-max-microvolt = <1210000>;
> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vddcpu: VDD_OTHER {
> +				regulator-name = "VDD_OTHER";
> +				regulator-min-microvolt = <1700000>;
> +				regulator-max-microvolt = <3600000>;

I haven't got any input on question asked in v4 on the regulator values.
Are the values from this version the right ones? Is this board supporting
DVFS or the label name is wrong or maybe the min-max range is still wrong?

> +				regulator-initial-mode = <2>;
> +				regulator-allowed-modes = <2>, <4>;
> +				regulator-ramp-delay = <3125>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +					regulator-mode = <4>;
> +				};
> +
> +				regulator-state-mem {
> +					regulator-mode = <4>;
> +				};
> +			};
> +
> +			vldo1: LDO1 {
> +				regulator-name = "LDO1";
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <3700000>;
> +				regulator-always-on;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +				};
> +			};
> +
> +			vldo2: LDO2 {
> +				regulator-name = "LDO2";
> +				regulator-min-microvolt = <1200000>;
> +				regulator-max-microvolt = <3700000>;
> +
> +				regulator-state-standby {
> +					regulator-on-in-suspend;
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&i2s {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_i2s_default>;
> +	#sound-dai-cells = <0>;
> +	status = "okay";
> +};
> +
> +&main_xtal {
> +	clock-frequency = <24000000>;
> +};
> +
> +&pinctrl {
> +	classd {
> +		pinctrl_classd_default: classd-default {
> +			atmel,pins =
> +				<AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
> +				<AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
> +		};
> +	};
> +
> +	dbgu {
> +		pinctrl_dbgu_default: dbgu-default {
> +			atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
> +				     <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	flexcom {
> +		pinctrl_flx6_default: flx6-default {
> +			atmel,pins =
> +				<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
> +				<AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
> +		};
> +	};
> +
> +	gpio-keys {
> +		pinctrl_key_gpio_default: key-gpio-default {
> +			atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	i2s {
> +		pinctrl_i2s_default: i2s-default {
> +			atmel,pins =
> +				<AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SCK */
> +				<AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SWS */
> +				<AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDIN */
> +				<AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE>,		/* I2SDOUT */
> +				<AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;		/* I2SMCK */
> +		};
> +	};
> +
> +	leds {
> +		pinctrl_red_led_gpio_default: red-led-gpio-default {
> +			atmel,pins = <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +		pinctrl_green_led_gpio_default: green-led-gpio-default {
> +			atmel,pins = <AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +		pinctrl_blue_led_gpio_default: blue-led-gpio-default {
> +			atmel,pins = <AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
> +		};
> +	};
> +
> +	sdmmc0 {
> +		pinctrl_sdmmc0_default: sdmmc0-default {
> +			atmel,pins =
> +				<AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,				/* PA2 CK  periph A with pullup */
> +				<AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA1 CMD periph A with pullup */
> +				<AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA0 DAT0 periph A */
> +				<AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA3 DAT1 periph A with pullup */
> +				<AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,	/* PA4 DAT2 periph A with pullup */
> +				<AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;	/* PA5 DAT3 periph A with pullup */
> +		};
> +	};
> +}; /* pinctrl */
> +
> +&rtt {
> +	atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
> +};
> +
> +&sdmmc0 {
> +	bus-width = <4>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_sdmmc0_default>;
> +	cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
> +	disable-wp;
> +	status = "okay";
> +};
> +
> +&slow_xtal {
> +	clock-frequency = <32768>;
> +};
> +
> +&poweroff {
> +	debounce-delay-us = <976>;
> +	status = "okay";
> +
> +	input@0 {
> +		reg = <0>;
> +	};
> +};
> +
> +&trng {
> +	status = "okay";
> +};
> +
> +&watchdog {
> +	status = "okay";
> +};

Re: [PATCH v5 27/27] ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board

[Varshini.Rajendran]

On 14/07/24 7:16 pm, claudiu beznea wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi, Varshini,
> 
> On 03.07.2024 13:29, Varshini Rajendran wrote:
>> Add device tree file for sam9x75 curiosity board.
>>
>> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
>> ---
>> Changes in v5:
>> - Update commit message to match the directory structure.
>> - Alphanumerically sorted Makefile entries.
>> - Corrected VDDCore minimum voltage.
>> - Enabled the i2s node.
>> - Removed additional blank lines.
>> - Enclosed each entry with separate <>.
>> - Corrected pinctrl names to match Microchip convention.
>> - Enabled slewrate in sdmmc node.
>> - Corrected pinmux mask.
>> - Added phandle to leds for ease of access with upcoming device entries.
>> - Updated gpio pin number for red led.
>> ---
>>   arch/arm/boot/dts/microchip/Makefile          |   3 +
>>   .../dts/microchip/at91-sam9x75_curiosity.dts  | 312 ++++++++++++++++++
>>   2 files changed, 315 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>>
>> diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile
>> index 0c45c8d17468..470fe46433a9 100644
>> --- a/arch/arm/boot/dts/microchip/Makefile
>> +++ b/arch/arm/boot/dts/microchip/Makefile
>> @@ -2,6 +2,7 @@
>>   # Enables support for device-tree overlays
>>   DTC_FLAGS_at91-sam9x60_curiosity := -@
>>   DTC_FLAGS_at91-sam9x60ek := -@
>> +DTC_FLAGS_at91-sam9x75_curiosity := -@
>>   DTC_FLAGS_at91-sama5d27_som1_ek := -@
>>   DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@
>>   DTC_FLAGS_at91-sama5d29_curiosity := -@
>> @@ -60,6 +61,8 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
>>   dtb-$(CONFIG_SOC_SAM9X60) += \
>>        at91-sam9x60_curiosity.dtb \
>>        at91-sam9x60ek.dtb
>> +dtb-$(CONFIG_SOC_SAM9X7) += \
>> +     at91-sam9x75_curiosity.dtb
>>   dtb-$(CONFIG_SOC_SAM_V7) += \
>>        at91-kizbox2-2.dtb \
>>        at91-kizbox3-hs.dtb \
>> diff --git a/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>> new file mode 100644
>> index 000000000000..4a4f14f13634
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>> @@ -0,0 +1,312 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * at91-sam9x75_curiosity.dts - Device Tree file for Microchip SAM9X75 Curiosity board
>> + *
>> + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries
>> + *
>> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
>> + */
>> +/dts-v1/;
>> +#include "sam9x7.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +
>> +/ {
>> +     model = "Microchip SAM9X75 Curiosity";
>> +     compatible = "microchip,sam9x75-curiosity", "microchip,sam9x7", "atmel,at91sam9";
>> +
>> +     aliases {
>> +             i2c0 = &i2c6;
>> +     };
>> +
>> +     chosen {
>> +             stdout-path = "serial0:115200n8";
>> +     };
>> +
>> +     gpio-keys {
>> +             compatible = "gpio-keys";
>> +             pinctrl-names = "default";
>> +             pinctrl-0 = <&pinctrl_key_gpio_default>;
>> +
>> +             button-user {
>> +                     label = "USER";
>> +                     gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
>> +                     linux,code = <KEY_0>;
>> +                     wakeup-source;
>> +             };
>> +     };
>> +
>> +     leds {
>> +             compatible = "gpio-leds";
>> +
>> +             led_red: led-red {
>> +                     label = "red";
>> +                     gpios = <&pioC 14 GPIO_ACTIVE_HIGH>;
>> +                     pinctrl-0 = <&pinctrl_red_led_gpio_default>;
>> +             };
>> +
>> +             led_green: led-green {
>> +                     label = "green";
>> +                     gpios = <&pioC 21 GPIO_ACTIVE_HIGH>;
>> +                     pinctrl-0 = <&pinctrl_green_led_gpio_default>;
>> +             };
>> +
>> +             led_blue: led-blue {
>> +                     label = "blue";
>> +                     gpios = <&pioC 20 GPIO_ACTIVE_HIGH>;
>> +                     pinctrl-0 = <&pinctrl_blue_led_gpio_default>;
>> +                     linux,default-trigger = "heartbeat";
>> +             };
>> +     };
>> +
>> +     memory@20000000 {
>> +             reg = <0x20000000 0x10000000>;
>> +             device_type = "memory";
>> +     };
>> +};
>> +
>> +&classd {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_classd_default>;
>> +     atmel,pwm-type = "diff";
>> +     atmel,non-overlap-time = <10>;
>> +     status = "okay";
>> +};
>> +
>> +&dbgu {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_dbgu_default>;
>> +     status = "okay";
>> +};
>> +
>> +&dma0 {
>> +     status = "okay";
>> +};
>> +
>> +&flx6 {
>> +     atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
>> +     status = "okay";
>> +};
>> +
>> +&i2c6 {
>> +     #address-cells = <1>;
>> +     #size-cells = <0>;
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_flx6_default>;
>> +     i2c-analog-filter;
>> +     i2c-digital-filter;
>> +     i2c-digital-filter-width-ns = <35>;
>> +     status = "okay";
>> +
>> +     pmic@5b {
>> +             compatible = "microchip,mcp16502";
>> +             reg = <0x5b>;
>> +
>> +             regulators {
>> +                     vdd_3v3: VDD_IO {
>> +                             regulator-name = "VDD_IO";
>> +                             regulator-min-microvolt = <3000000>;
>> +                             regulator-max-microvolt = <3600000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddioddr: VDD_DDR {
>> +                             regulator-name = "VDD_DDR";
>> +                             regulator-min-microvolt = <1283000>;
>> +                             regulator-max-microvolt = <1450000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddcore: VDD_CORE {
>> +                             regulator-name = "VDD_CORE";
>> +                             regulator-min-microvolt = <1140000>;
>> +                             regulator-max-microvolt = <1210000>;
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vddcpu: VDD_OTHER {
>> +                             regulator-name = "VDD_OTHER";
>> +                             regulator-min-microvolt = <1700000>;
>> +                             regulator-max-microvolt = <3600000>;
> 
> I haven't got any input on question asked in v4 on the regulator values.
> Are the values from this version the right ones? Is this board supporting
> DVFS or the label name is wrong or maybe the min-max range is still wrong?

Apologies. I misanalysed the comment before. I will fix the regulator 
values/label with the values from the board schematics. And FYI, this 
board does not support DVFS. The values I set are misleading.

> 
>> +                             regulator-initial-mode = <2>;
>> +                             regulator-allowed-modes = <2>, <4>;
>> +                             regulator-ramp-delay = <3125>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                                     regulator-mode = <4>;
>> +                             };
>> +
>> +                             regulator-state-mem {
>> +                                     regulator-mode = <4>;
>> +                             };
>> +                     };
>> +
>> +                     vldo1: LDO1 {
>> +                             regulator-name = "LDO1";
>> +                             regulator-min-microvolt = <1200000>;
>> +                             regulator-max-microvolt = <3700000>;
>> +                             regulator-always-on;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                             };
>> +                     };
>> +
>> +                     vldo2: LDO2 {
>> +                             regulator-name = "LDO2";
>> +                             regulator-min-microvolt = <1200000>;
>> +                             regulator-max-microvolt = <3700000>;
>> +
>> +                             regulator-state-standby {
>> +                                     regulator-on-in-suspend;
>> +                             };
>> +                     };
>> +             };
>> +     };
>> +};
>> +
>> +&i2s {
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_i2s_default>;
>> +     #sound-dai-cells = <0>;
>> +     status = "okay";
>> +};
>> +
>> +&main_xtal {
>> +     clock-frequency = <24000000>;
>> +};
>> +
>> +&pinctrl {
>> +     classd {
>> +             pinctrl_classd_default: classd-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>,
>> +                             <AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_PULL_DOWN>;
>> +             };
>> +     };
>> +
>> +     dbgu {
>> +             pinctrl_dbgu_default: dbgu-default {
>> +                     atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
>> +                                  <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     flexcom {
>> +             pinctrl_flx6_default: flx6-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
>> +                             <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
>> +             };
>> +     };
>> +
>> +     gpio-keys {
>> +             pinctrl_key_gpio_default: key-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     i2s {
>> +             pinctrl_i2s_default: i2s-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOB 26 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SCK */
>> +                             <AT91_PIOB 15 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SWS */
>> +                             <AT91_PIOB 16 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SDIN */
>> +                             <AT91_PIOB 17 AT91_PERIPH_D AT91_PINCTRL_NONE>,         /* I2SDOUT */
>> +                             <AT91_PIOB 25 AT91_PERIPH_D AT91_PINCTRL_NONE>;         /* I2SMCK */
>> +             };
>> +     };
>> +
>> +     leds {
>> +             pinctrl_red_led_gpio_default: red-led-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +             pinctrl_green_led_gpio_default: green-led-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +             pinctrl_blue_led_gpio_default: blue-led-gpio-default {
>> +                     atmel,pins = <AT91_PIOC 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
>> +             };
>> +     };
>> +
>> +     sdmmc0 {
>> +             pinctrl_sdmmc0_default: sdmmc0-default {
>> +                     atmel,pins =
>> +                             <AT91_PIOA 2 AT91_PERIPH_A (AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,                               /* PA2 CK  periph A with pullup */
>> +                             <AT91_PIOA 1 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA1 CMD periph A with pullup */
>> +                             <AT91_PIOA 0 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA0 DAT0 periph A */
>> +                             <AT91_PIOA 3 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA3 DAT1 periph A with pullup */
>> +                             <AT91_PIOA 4 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>,        /* PA4 DAT2 periph A with pullup */
>> +                             <AT91_PIOA 5 AT91_PERIPH_A (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DRIVE_STRENGTH_HI | AT91_PINCTRL_SLEWRATE_ENA)>;        /* PA5 DAT3 periph A with pullup */
>> +             };
>> +     };
>> +}; /* pinctrl */
>> +
>> +&rtt {
>> +     atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
>> +};
>> +
>> +&sdmmc0 {
>> +     bus-width = <4>;
>> +     pinctrl-names = "default";
>> +     pinctrl-0 = <&pinctrl_sdmmc0_default>;
>> +     cd-gpios = <&pioA 23 GPIO_ACTIVE_LOW>;
>> +     disable-wp;
>> +     status = "okay";
>> +};
>> +
>> +&slow_xtal {
>> +     clock-frequency = <32768>;
>> +};
>> +
>> +&poweroff {
>> +     debounce-delay-us = <976>;
>> +     status = "okay";
>> +
>> +     input@0 {
>> +             reg = <0>;
>> +     };
>> +};
>> +
>> +&trng {
>> +     status = "okay";
>> +};
>> +
>> +&watchdog {
>> +     status = "okay";
>> +};

-- 
Thanks and Regards,
Varshini Rajendran.

Re: [PATCH v5 00/27] Add support for sam9x7 SoC family

[Rob Herring (Arm)]

On Wed, 03 Jul 2024 15:50:11 +0530, Varshini Rajendran wrote:
> This patch series adds support for the new SoC family - sam9x7.
>  - The device tree, configs and drivers are added
>  - Clock driver for sam9x7 is added
>  - Support for basic peripherals is added
>  - Target board SAM9X75 Curiosity is added
> 
>  Changes in v5:
>  --------------
> 
>  - Addressed all the review comments in the patches
>  - Picked up all Acked-by and Reviewed-by tags
>  - Dropped applied patches from the series
>  - Addressed the ABI breakage reported in the IRQ patch
>  - All the specific changes are captured in the corresponding patches
> 
>  Changes in v4:
>  --------------
> 
>  - Addressed all the review comments in the patches
>  - Picked up all Acked-by and Reviewed-by tags
>  - Dropped applied patches from the series
>  - Added pwm node and related dt binding documentation
>  - Added support for exporting some clocks to DT
>  - Dropped USB related patches and changes. See NOTE.
>  - All the specific changes are captured in the corresponding patches
> 
>  NOTE: Owing to the discussion here
>  https://lore.kernel.org/linux-devicetree/CAL_JsqJ9PrX6fj-EbffeJce09MXs=B7t+KS_kOinxaRx38=WxA@mail.gmail.com/
>  the USB related changes are dropped from this series in order to enable
>  us to work on the mentioned issues before adding new compatibles as
>  said. The issues/warnings will be addressed in subsequent patches.
>  After which the USB related support for sam9x7 SoCs will be added. Hope
>  this works out fine.
> 
>  Changes in v3:
>  --------------
> 
>  - Fixed the DT documentation errors pointed out in v2.
>  - Dropped Acked-by tag in tcb DT doc patch as it had to be adapted
>    according to sam9x7 correctly.
>  - Picked by the previously missed tags.
>  - Dropped this patch "dt-bindings: usb: generic-ehci: Document clock-names
>    property" as the warning was not found while validating DT-schema for
>    at91-sam9x75_curiosity.dtb.
>  - Dropped redundant words in the commit message.
>  - Fixed the CHECK_DTBS warnings validated against
>    at91-sam9x75_curiosity.dtb.
>  - Renamed dt nodes according to naming convention.
>  - Dropped unwanted status property in dts.
>  - Removed nodes that are not in use from the board dts.
>  - Removed spi DT doc patch from the series as it was already applied
>    and a fix patch was applied subsequently. Added a patch to remove the
>    compatible to adapt sam9x7.
>  - Added sam9x7 compatibles in usb dt documentation.
> 
> 
>  Changes in v2:
>  --------------
> 
>  - Added sam9x7 specific compatibles in DT with fallbacks
>  - Documented all the newly added DT compatible strings
>  - Added device tree for the target board sam9x75 curiosity and
>    documented the same in the DT bindings documentation
>  - Removed the dt nodes that are not supported at the moment
>  - Removed the configs added by previous version that are not supported
>    at the moment
>  - Fixed all the corrections in the commit message
>  - Changed all the instances of copyright year to 2023
>  - Added sam9x7 flag in PIT64B configuration
>  - Moved macro definitions to header file
>  - Added another divider in mck characteristics in the pmc driver
>  - Fixed the memory leak in the pmc driver
>  - Dropped patches that are no longer needed
>  - Picked up Acked-by and Reviewed-by tags
> 
> 
> Varshini Rajendran (27):
>   dt-bindings: atmel-sysreg: add sam9x7
>   dt-bindings: atmel-ssc: add microchip,sam9x7-ssc
>   dt-bindings: serial: atmel,at91-usart: add compatible for sam9x7.
>   ARM: at91: pm: add support for sam9x7 SoC family
>   ARM: at91: pm: add sam9x7 SoC init config
>   ARM: at91: add support in SoC driver for new sam9x7
>   dt-bindings: clocks: atmel,at91sam9x5-sckc
>   dt-bindings: clocks: atmel,at91rm9200-pmc
>   clk: at91: clk-sam9x60-pll: re-factor to support individual core freq
>     outputs
>   clk: at91: sam9x7: add support for HW PLL freq dividers
>   clk: at91: sama7g5: move mux table macros to header file
>   dt-bindings: clock: at91: Allow PLLs to be exported and referenced in
>     DT
>   clk: at91: sam9x7: add sam9x7 pmc driver
>   dt-bindings: interrupt-controller: Add support for sam9x7 aic
>   dt-bindings: interrupt-controller: Document the property
>     microchip,nr-irqs
>   irqchip/atmel-aic5: Add support to get nr_irqs from DT for sam9x60 &
>     sam9x7
>   ARM: dts: at91: sam9x60: Add nirqs property in the dt node
>   power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7
>   power: reset: at91-reset: add reset support for sam9x7 SoC
>   power: reset: at91-reset: add sdhwc support for sam9x7 SoC
>   dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7
>   dt-bindings: power: reset: atmel,sama5d2-shdwc: add sam9x7
>   ARM: at91: Kconfig: add config flag for SAM9X7 SoC
>   ARM: configs: at91: enable config flags for sam9x7 SoC family
>   ARM: dts: at91: sam9x7: add device tree for SoC
>   dt-bindings: arm: add sam9x75 curiosity board
>   ARM: dts: microchip: sam9x75_curiosity: add sam9x75 curiosity board
> 
>  .../devicetree/bindings/arm/atmel-at91.yaml   |    6 +
>  .../devicetree/bindings/arm/atmel-sysregs.txt |    7 +-
>  .../bindings/clock/atmel,at91rm9200-pmc.yaml  |    2 +
>  .../bindings/clock/atmel,at91sam9x5-sckc.yaml |    4 +-
>  .../interrupt-controller/atmel,aic.yaml       |   28 +-
>  .../devicetree/bindings/misc/atmel-ssc.txt    |    1 +
>  .../power/reset/atmel,sama5d2-shdwc.yaml      |    3 +
>  .../reset/atmel,at91sam9260-reset.yaml        |    4 +
>  .../bindings/serial/atmel,at91-usart.yaml     |    9 +-
>  arch/arm/boot/dts/microchip/Makefile          |    3 +
>  .../dts/microchip/at91-sam9x75_curiosity.dts  |  312 +++++
>  arch/arm/boot/dts/microchip/sam9x60.dtsi      |    1 +
>  arch/arm/boot/dts/microchip/sam9x7.dtsi       | 1226 +++++++++++++++++
>  arch/arm/configs/at91_dt_defconfig            |    1 +
>  arch/arm/mach-at91/Kconfig                    |   22 +-
>  arch/arm/mach-at91/Makefile                   |    1 +
>  arch/arm/mach-at91/generic.h                  |    2 +
>  arch/arm/mach-at91/pm.c                       |   29 +
>  arch/arm/mach-at91/sam9x7.c                   |   33 +
>  drivers/clk/at91/Makefile                     |    1 +
>  drivers/clk/at91/clk-sam9x60-pll.c            |   42 +-
>  drivers/clk/at91/pmc.h                        |   18 +
>  drivers/clk/at91/sam9x60.c                    |    7 +
>  drivers/clk/at91/sam9x7.c                     |  946 +++++++++++++
>  drivers/clk/at91/sama7g5.c                    |   42 +-
>  drivers/irqchip/irq-atmel-aic5.c              |    8 +-
>  drivers/power/reset/Kconfig                   |    4 +-
>  drivers/power/reset/at91-sama5d2_shdwc.c      |    1 +
>  drivers/soc/atmel/soc.c                       |   23 +
>  drivers/soc/atmel/soc.h                       |    9 +
>  include/dt-bindings/clock/at91.h              |    4 +
>  31 files changed, 2750 insertions(+), 49 deletions(-)
>  create mode 100644 arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dts
>  create mode 100644 arch/arm/boot/dts/microchip/sam9x7.dtsi
>  create mode 100644 arch/arm/mach-at91/sam9x7.c
>  create mode 100644 drivers/clk/at91/sam9x7.c
> 
> --
> 2.25.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y microchip/at91-sam9x75_curiosity.dtb' for 20240703102011.193343-1-varshini.rajendran@microchip.com:

arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@80000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@80000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@90000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /ahb/mmc@90000000: failed to match any schema with compatible: ['microchip,sam9x7-sdhci', 'microchip,sam9x60-sdhci']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/dma-controller@f0008000: failed to match any schema with compatible: ['microchip,sam9x7-dma', 'atmel,sama5d4-dma']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/dma-controller@f0008000: failed to match any schema with compatible: ['microchip,sam9x7-dma', 'atmel,sama5d4-dma']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ssc@f0010000: failed to match any schema with compatible: ['microchip,sam9x7-ssc', 'atmel,at91sam9g45-ssc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ssc@f0010000: failed to match any schema with compatible: ['microchip,sam9x7-ssc', 'atmel,at91sam9g45-ssc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0028000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0028000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0040000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f0040000: failed to match any schema with compatible: ['microchip,sam9x7-pit64b', 'microchip,sam9x60-pit64b']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible:0: 'microchip,sam9x7-tcb' is not one of ['atmel,at91rm9200-tcb', 'atmel,at91sam9x5-tcb', 'atmel,sama5d2-tcb']
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible:1: 'simple-mfd' was expected
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible:2: 'syscon' was expected
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: timer@f8008000: compatible: ['microchip,sam9x7-tcb', 'atmel,sama5d2-tcb', 'simple-mfd', 'syscon'] is too long
	from schema $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/timer@f8008000: failed to match any schema with compatible: ['microchip,sam9x7-tcb', 'atmel,sama5d2-tcb', 'simple-mfd', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/sfr@f8050000: failed to match any schema with compatible: ['microchip,sam9x7-sfr', 'microchip,sam9x60-sfr', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/sfr@f8050000: failed to match any schema with compatible: ['microchip,sam9x7-sfr', 'microchip,sam9x60-sfr', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/matrix@ffffde00: failed to match any schema with compatible: ['microchip,sam9x7-matrix', 'atmel,at91sam9x5-matrix', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/matrix@ffffde00: failed to match any schema with compatible: ['microchip,sam9x7-matrix', 'atmel,at91sam9x5-matrix', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ecc-engine@ffffe000: failed to match any schema with compatible: ['microchip,sam9x7-pmecc', 'atmel,at91sam9g45-pmecc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/ecc-engine@ffffe000: failed to match any schema with compatible: ['microchip,sam9x7-pmecc', 'atmel,at91sam9g45-pmecc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/mpddrc@ffffe800: failed to match any schema with compatible: ['microchip,sam9x7-ddramc', 'atmel,sama5d3-ddramc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/mpddrc@ffffe800: failed to match any schema with compatible: ['microchip,sam9x7-ddramc', 'atmel,sama5d3-ddramc']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/smc@ffffea00: failed to match any schema with compatible: ['microchip,sam9x7-smc', 'atmel,at91sam9260-smc', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/smc@ffffea00: failed to match any schema with compatible: ['microchip,sam9x7-smc', 'atmel,at91sam9260-smc', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-pinctrl', 'microchip,sam9x60-pinctrl', 'simple-mfd']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-pinctrl', 'microchip,sam9x60-pinctrl', 'simple-mfd']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff400: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff600: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff600: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff600: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff800: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff800: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffff800: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffffa00: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffffa00: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/pinctrl@fffff400/gpio@fffffa00: failed to match any schema with compatible: ['microchip,sam9x7-gpio', 'microchip,sam9x60-gpio', 'atmel,at91rm9200-gpio']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/syscon@fffffe60: failed to match any schema with compatible: ['microchip,sam9x7-gpbr', 'atmel,at91sam9260-gpbr', 'syscon']
arch/arm/boot/dts/microchip/at91-sam9x75_curiosity.dtb: /apb/syscon@fffffe60: failed to match any schema with compatible: ['microchip,sam9x7-gpbr', 'atmel,at91sam9260-gpbr', 'syscon']