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[91.141.74.240]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd6834dasm16939225e9.4.2026.10.14.13.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2026 13:33:20 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: linux-arm-kernel@lists.infradead.org, Navid Ghahremani Cc: arnd@arndb.de, krzk@kernel.org, Navid Ghahremani , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 19/24] dt-bindings: spi: Add ZTE ZX family SPI flash controller binding Date: Wed, 14 Oct 2026 22:33:01 +0200 Message-ID: <0hKeGS29RSCCKJETWWv9dA@gmail.com> In-Reply-To: <20261014072109.1759502-20-ghahramani.navid@gmail.com> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-20-ghahramani.navid@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextParttwTE2U3XQbmQGd0wk4ry0w"; micalg="pgp-sha256"; protocol="application/pgp-signature" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261014_133323_876878_185BF0D3 X-CRM114-Status: GOOD ( 15.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --nextParttwTE2U3XQbmQGd0wk4ry0w Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= Date: Wed, 14 Oct 2026 22:33:01 +0200 Message-ID: <0hKeGS29RSCCKJETWWv9dA@gmail.com> In-Reply-To: <20261014072109.1759502-20-ghahramani.navid@gmail.com> MIME-Version: 1.0 Am Mittwoch, 14. Oktober 2026, 09:20:59 Mitteleurop=C3=A4ische Sommerzeit s= chrieb=20 Navid Ghahremani: > + - zte,zx29-qspi > + - zte,zx279128s-spifc Unless there is a hardware difference that matters to the driver I think on= e=20 compatible should be enough. Probably zte,zx-qspi. Although since this=20 controller is very specific for flash chips zte,zx-spifc or zte,spifc are w= orthy=20 considerations too. As far as I can see this controller only has flash memo= ry=20 ops and can't even send a generic byte stream. Note that at least my board, and probably yours too, has a "normal" SPI=20 controller too. In my case it can talk to SPI displays or a SLIC analog pho= ne=20 controller. It has a different hardware interface and needs a separate driv= er. > + > + clocks: > + items: > + - description: work clock, the source of the SPI clock > + - description: register (APB) clock > + > + clock-names: > + items: > + - const: wclk > + - const: pclk > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names I think the interrupt should be required by the binding too. The driver is= =20 still free to ignore it, but the binding is supposed to describe the hardwa= re,=20 not the driver. My hardware has two DMA lines too. I don't know if they are always there. F= or=20 pragmatic reasons (the DMA controller is its own beast and for usability le= ss=20 important than the flash controller) I'd make the DMA properties optional. --nextParttwTE2U3XQbmQGd0wk4ry0w Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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