* [PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table
@ 2016-10-21 4:03 Xing Zheng
2016-10-21 7:47 ` Heiko Stuebner
0 siblings, 1 reply; 2+ messages in thread
From: Xing Zheng @ 2016-10-21 4:03 UTC (permalink / raw)
To: linux-arm-kernel
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3399.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 2c7cba7..a87cb49 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table
2016-10-21 4:03 [PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table Xing Zheng
@ 2016-10-21 7:47 ` Heiko Stuebner
0 siblings, 0 replies; 2+ messages in thread
From: Heiko Stuebner @ 2016-10-21 7:47 UTC (permalink / raw)
To: linux-arm-kernel
Am Freitag, 21. Oktober 2016, 12:03:40 CEST schrieb Xing Zheng:
> We need to get the accurate 533.25MHz for the DP display.
>
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
applied to my clk-branch for 4.10
Thanks
Heiko
^ permalink raw reply [flat|nested] 2+ messages in thread
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2016-10-21 7:47 ` Heiko Stuebner
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