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Wed, 1 Apr 2026 08:39:48 +0000 Message-ID: <1027afd7-dec6-4ff3-85eb-2d9a1646ada6@linumiz.com> Date: Wed, 1 Apr 2026 10:39:42 +0200 User-Agent: Mozilla Thunderbird Cc: parthiban@linumiz.com, David Airlie , Simona Vetter , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, paulk@sys-base.io Subject: Re: [PATCH v3 0/6] drm/sun4i: Support LVDS on D1s/T113 combo D-PHY To: =?UTF-8?Q?Kuba_Szczodrzy=C5=84ski?= , Maxime Ripard , Samuel Holland , Chen-Yu Tsai , Jernej Skrabec , Maarten Lankhorst , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley References: <20250221161751.1278049-1-kuba@szczodrzynski.pl> <20251116134609.447043-1-kuba@szczodrzynski.pl> Content-Language: en-US From: Parthiban Organization: Linumiz In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-ClientProxiedBy: BM1PR01CA0147.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:68::17) To TYZPR06MB6935.apcprd06.prod.outlook.com (2603:1096:405:3c::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TYZPR06MB6935:EE_|SI2PR06MB5041:EE_ X-MS-Office365-Filtering-Correlation-Id: af6a17a9-e457-4b76-3096-08de8fca3beb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|921020|22082099003|56012099003|18002099003; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dear Kuba, On 2/7/26 2:34 PM, Parthiban wrote: > On 11/16/25 2:46 PM, Kuba Szczodrzyński wrote: >> Some Allwinner chips (notably the D1s/T113 and the A100) have a "combo >> MIPI DSI D-PHY" which is required when using single-link LVDS0. The same >> PD0..PD9 pins are used for either DSI or LVDS. >> >> Other than having to use the combo D-PHY, LVDS output is configured in >> the same way as on older chips. >> >> This series enables the sun6i MIPI D-PHY to also work in LVDS mode. It >> is then configured by the LCD TCON, which allows connecting a >> single-link LVDS display panel. Now I also have the MIPI and LVDS working together on A133. Can I pick your changes and post a combined series for the display support for A133? This will also address D1s/T114 as well. -- Thanks, Parthiban https://linumiz.com https://www.linkedin.com/company/linumiz