From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55AB6C3DA7F for ; Thu, 15 Aug 2024 16:44:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Dq8puxKj0ZeN7IVpwGFCF5x6k5LykH5w1x10HHPN5Sg=; b=FMise/BFdporcnoOQQopZCKVpT esQ7M7IEODtMWCfQxZfP7kGcyKPoF3avUg7Nga0w/uLeSlmQZa7kDZqLOfy5ajCQ6hZh9TNtNKfb6 6mM2IFENs0prVOnOBsomROrRzxDTXufxOmpC7thof/e7WGCc1Jrno8qb32izDSYe3Mq7vkRZt5O0m SFLJ4QPnFxl3oWwC7AijFu6c8gdLozYkXIUZXB1WHQ7rMQLkst9Fg2iEBkXyK16jyzssqm89CjMBm JUD1YZDCghtbcgaO9xdJ8pjy+97a7n+o4J0o11zPKPcmdX8u/K0Kocs8uVNHmR8XRmyyW/OSyjquX tMUX9oBA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sedaK-0000000AYFK-3GxT; Thu, 15 Aug 2024 16:44:24 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sedZc-0000000AY9G-270T; Thu, 15 Aug 2024 16:43:46 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Type:Content-Transfer-Encoding:MIME-Version: References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=Dq8puxKj0ZeN7IVpwGFCF5x6k5LykH5w1x10HHPN5Sg=; b=MBos0nqnRP7dkdT8OBgJI4MLbr 86XxcH61JoKPx3Lh9ripFgnIMZyaYuC2ajT6obDwySQfgVdtnNMqY4Z0hrkfaxWmMBW+r+c0OCMSN 0oHKHHCSm26Y0ZSb93NDXMoy8rC8opEiEyiJjy9nC1f7audLXYD3xgh+raPufldKTHKYSHKH+3WQz /AuiBIEtcgLHBeGQHhvUIclFBmpt2vUG38M/9LJmdA1P3tLPG6ynRObk6ypfXQ7uvIkhzrAdZuj/P lDZPDtBlieidCYjYDG7d06u0uf8YSEcthqNGD8m9KtWVy7SVbgROFbSb7TGXpIPc+HjwtxiDHy26J 6G1ymHlw==; Received: from i53875a9f.versanet.de ([83.135.90.159] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sedZJ-0005XG-K6; Thu, 15 Aug 2024 18:43:21 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Jiri Slaby , Chris Morgan , Jonas Karlman , Tim Lunn , Andy Yan , Muhammed Efe Cetin , Jagan Teki , Dragan Simic , Ondrej Jirman , Yao Zi Cc: Celeste Liu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Yao Zi Subject: Re: [PATCH v3 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC Date: Thu, 15 Aug 2024 18:43:20 +0200 Message-ID: <10324095.IZOipudI63@diego> In-Reply-To: <20240814155014.18097-4-ziyao@disroot.org> References: <20240814155014.18097-1-ziyao@disroot.org> <20240814155014.18097-4-ziyao@disroot.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_094340_720117_38A12B0F X-CRM114-Status: GOOD ( 22.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Am Mittwoch, 14. August 2024, 17:50:13 CEST schrieb Yao Zi: > This initial device tree describes CPU, interrupts and UART on the chip > and is able to boot into basic kernel with only UART. Cache information > is omitted for now as there is no precise documentation. Support for > other features will be added later. > > Signed-off-by: Yao Zi not sure if you have seen Krzysztof's comment yesterday, that he found the soc node getting documented in 2019 [0]. I guess that counts as a strong suggestion. Not sure how you're feeling about that, but I guess we could move to that scheme for new socs. So would you be willing to move the mmio-devices to a soc node? (stuff with mmio addresses in the node name) Thanks Heiko [0] https://lore.kernel.org/all/6320e4f3-e737-4787-8a72-7bd314ba883c@kernel.org/ > --- > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 182 +++++++++++++++++++++++ > 1 file changed, 182 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi > > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > new file mode 100644 > index 000000000000..816573c5fe9d > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > @@ -0,0 +1,182 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. > + * Copyright (c) 2024 Yao Zi > + */ > + > +#include > +#include > + > +/ { > + compatible = "rockchip,rk3528"; > + > + interrupt-parent = <&gic>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + serial6 = &uart6; > + serial7 = &uart7; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a53"; > + reg = <0x0>; > + device_type = "cpu"; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a53"; > + reg = <0x1>; > + device_type = "cpu"; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + compatible = "arm,cortex-a53"; > + reg = <0x2>; > + device_type = "cpu"; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + compatible = "arm,cortex-a53"; > + reg = <0x3>; > + device_type = "cpu"; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > + method = "smc"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + }; > + > + xin24m: clock-xin24m { > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "xin24m"; > + #clock-cells = <0>; > + }; > + > + gic: interrupt-controller@fed01000 { > + compatible = "arm,gic-400"; > + reg = <0x0 0xfed01000 0 0x1000>, > + <0x0 0xfed02000 0 0x2000>, > + <0x0 0xfed04000 0 0x2000>, > + <0x0 0xfed06000 0 0x2000>; > + interrupts = + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <3>; > + }; > + > + uart0: serial@ff9f0000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xff9f0000 0x0 0x100>; > + clock-frequency = <24000000>; > + interrupts = ; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart1: serial@ff9f8000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xff9f8000 0x0 0x100>; > + interrupts = ; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart2: serial@ffa00000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xffa00000 0x0 0x100>; > + interrupts = ; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart3: serial@ffa08000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xffa08000 0x0 0x100>; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart4: serial@ffa10000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xffa10000 0x0 0x100>; > + interrupts = ; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart5: serial@ffa18000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xffa18000 0x0 0x100>; > + interrupts = ; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart6: serial@ffa20000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xffa20000 0x0 0x100>; > + interrupts = ; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + uart7: serial@ffa28000 { > + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; > + reg = <0x0 0xffa28000 0x0 0x100>; > + interrupts = ; > + reg-io-width = <4>; > + reg-shift = <2>; > + status = "disabled"; > + }; > +}; >