From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D87EC4167B for ; Thu, 7 Dec 2023 14:15:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LuXPJFhLtA7tIW+6KU6bqFw4271kvAKb6RicmbBSWOY=; b=vkE3VUIwAFVL5P LVQTuLLrXLVpvhOG8qgOTwy6esPJ0IWAbEorD1LVkRiDjDCFsJXAZXx5ROj92GRsBRrmha/53vYCx pdLSeLHkNT5CQvG+y9A+woYduCiTltni10Ldu/5Vs5ITcDg3GRxMpULixYrlxj7qrnS69jWEee8If nnPcbsLvtAmiEgq3p9C4GniI6TJtYQ+A9YACr08pgXvwQrUMetnqn5imfICX9Y3m++DEAApyQ0iUU RN1a90Kns5UEeYgoPOwymOoYZ/ATAE0Z9gLUvhP+lDsfsMYZ9TbsOIfmUPotRuNEBb2mQcZtauODB m53xNZ/yXQKTGIEzVFaQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rBF9q-00CzbK-1S; Thu, 07 Dec 2023 14:15:18 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rBF9m-00Czad-2L for linux-arm-kernel@lists.infradead.org; Thu, 07 Dec 2023 14:15:16 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1701958514; x=1733494514; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2g0BGb8jIEzmfFqJKa/JvmvhUlA22LhLY7cVrJZW26A=; b=O3qPva0AhJVKzIakKoPFRHtyESLpKggkaam5auMVdOqXnLEK2SKn/926 vgahJsATlmpirQCbGvsGbVovVQPcH9WXSuzRvGqxEzsZbYuC7TIgqMsRq wNXG1me+LwXCsKtg4eQJpXDk4tJ8ZG6rr4LId7Xa8m87hSeQYqnjXMkfc pi1RjrEzOSFgYvjpmaejaJeUziYx505K84GWWpdGamNK1O98DLsTcjY1u xLfid/CWI6dc8oGNHv8F4ciOv4Cye131EOON5j5EnQJc5S8iPAcYsVk5g 2IrESJiJLXms08oVLYMLqx/dIGlCBsT8CEZyEr+KCNbzJS+cS0ly8ih2g A==; X-IronPort-AV: E=Sophos;i="6.04,256,1695679200"; d="scan'208";a="34385625" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 07 Dec 2023 15:15:10 +0100 Received: from steina-w.localnet (steina-w.tq-net.de [10.123.53.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id BBEFE280075; Thu, 7 Dec 2023 15:15:09 +0100 (CET) From: Alexander Stein To: Laurent Pinchart Cc: Mauro Carvalho Chehab , Shawn Guo , Sascha Hauer , Fabio Estevam , Pengutronix Kernel Team , NXP Linux Team , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 1/1] media: nxp: imx8-isi-debug: Add missing 36-Bit DMA registers to debugfs output Date: Thu, 07 Dec 2023 15:15:10 +0100 Message-ID: <10383921.nUPlyArG6x@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20231207135539.GJ9675@pendragon.ideasonboard.com> References: <20231207110918.1338524-1-alexander.stein@ew.tq-group.com> <20231207135539.GJ9675@pendragon.ideasonboard.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231207_061515_145109_26A8C53B X-CRM114-Status: GOOD ( 27.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Am Donnerstag, 7. Dezember 2023, 14:55:39 CET schrieb Laurent Pinchart: > Hi Alexander, > = > Thank you for the patch. > = > On Thu, Dec 07, 2023 at 12:09:18PM +0100, Alexander Stein wrote: > > The extended address registers are missing in the debug output register > > list. These are only available on 36-Bit DMA platforms. Due to the > > prolonged name, the output width has to be adjusted as well. > > = > > Signed-off-by: Alexander Stein > > --- > > Changes in v2: > > * Split register set into regular and 36-Bit DMA only > > * Adjust output width to address longer register names > > = > > Currently only tested on TQMa8MPxL (imx8mp-tqma8mpql-mba8mpxl.dts) > > = > > .../platform/nxp/imx8-isi/imx8-isi-debug.c | 28 +++++++++++++++++-- > > 1 file changed, 25 insertions(+), 3 deletions(-) > > = > > diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c > > b/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c index > > 6709ab7ea1f3..398864b5e506 100644 > > --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c > > +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c > > @@ -22,10 +22,11 @@ static inline u32 mxc_isi_read(struct mxc_isi_pipe > > *pipe, u32 reg)> = > > static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p) > > { > > #define MXC_ISI_DEBUG_REG(name) { name, #name } > > = > > - static const struct { > > + struct debug_regs { > > = > > u32 offset; > > const char * const name; > > = > > - } registers[] =3D { > > + }; > > + static const struct debug_regs registers[] =3D { > > = > > MXC_ISI_DEBUG_REG(CHNL_CTRL), > > MXC_ISI_DEBUG_REG(CHNL_IMG_CTRL), > > MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_CTRL), > > = > > @@ -67,6 +68,16 @@ static int mxc_isi_debug_dump_regs_show(struct seq_f= ile > > *m, void *p)> = > > MXC_ISI_DEBUG_REG(CHNL_SCL_IMG_CFG), > > MXC_ISI_DEBUG_REG(CHNL_FLOW_CTRL), > > = > > }; > > = > > + /* There registers contain the upper 4Bits of 36-Bit DMA addresses = */ > = > s/There/These/ > = > > + static const struct debug_regs registers_36bit_dma[] =3D { > > + MXC_ISI_DEBUG_REG(CHNL_Y_BUF1_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_U_BUF1_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_V_BUF1_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_Y_BUF2_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_U_BUF2_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_V_BUF2_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_IN_BUF_XTND_ADDR), > > + }; > > = > > struct mxc_isi_pipe *pipe =3D m->private; > > unsigned int i; > > = > > @@ -77,10 +88,21 @@ static int mxc_isi_debug_dump_regs_show(struct > > seq_file *m, void *p)> = > > seq_printf(m, "--- ISI pipe %u registers ---\n", pipe->id); > > = > > for (i =3D 0; i < ARRAY_SIZE(registers); ++i) > > = > > - seq_printf(m, "%20s[0x%02x]: 0x%08x\n", > > + seq_printf(m, "%21s[0x%02x]: 0x%08x\n", > > = > > registers[i].name, registers[i].offset, > > mxc_isi_read(pipe, registers[i].offset)); > > = > > + if (pipe->isi->pdata->has_36bit_dma) { > > + for (i =3D 0; i < ARRAY_SIZE(registers_36bit_dma); ++i) { > > + const struct debug_regs *reg =3D = ®isters_36bit_dma[i]; > > + > > + seq_printf(m, "%21s[0x%02x]: 0x%08x\n", > > + reg->name, > > + reg->offset, > > + mxc_isi_read(pipe, reg->offset)); > = > Lines should be aligned under the "m" of the first line. > = > I'll fix these small issues when applying, no need to send a v3. > = > Reviewed-by: Laurent Pinchart For the records: Also tested on TQMa8MxNL (imx8mn-tqma8mqnl-mba8mx.dts). As = expected it prints only the same registers as before. Thanks Alexander > = > > + } > > + } > > + > > = > > pm_runtime_put(pipe->isi->dev); > > = > > return 0; -- = TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/ _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel