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M=C3=A4rz 2025, 07:20:16 MEZ schrieb Simon Xue: > clock_set_rate should be executed after devm_clk_get_enabled. >=20 > Fixes: 97ad10bb2901 ("iio: adc: rockchip_saradc: Make use of devm_clk_get= _enabled") > Signed-off-by: Simon Xue Reviewed-by: Heiko Stuebner > --- > drivers/iio/adc/rockchip_saradc.c | 17 ++++++++--------- > 1 file changed, 8 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip= _saradc.c > index a29e54754c8f..ab4de67fb135 100644 > --- a/drivers/iio/adc/rockchip_saradc.c > +++ b/drivers/iio/adc/rockchip_saradc.c > @@ -480,15 +480,6 @@ static int rockchip_saradc_probe(struct platform_dev= ice *pdev) > if (info->reset) > rockchip_saradc_reset_controller(info->reset); > =20 > - /* > - * Use a default value for the converter clock. > - * This may become user-configurable in the future. > - */ > - ret =3D clk_set_rate(info->clk, info->data->clk_rate); > - if (ret < 0) > - return dev_err_probe(&pdev->dev, ret, > - "failed to set adc clk rate\n"); > - > ret =3D regulator_enable(info->vref); > if (ret < 0) > return dev_err_probe(&pdev->dev, ret, > @@ -515,6 +506,14 @@ static int rockchip_saradc_probe(struct platform_dev= ice *pdev) > if (IS_ERR(info->clk)) > return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), > "failed to get adc clock\n"); > + /* > + * Use a default value for the converter clock. > + * This may become user-configurable in the future. > + */ > + ret =3D clk_set_rate(info->clk, info->data->clk_rate); > + if (ret < 0) > + return dev_err_probe(&pdev->dev, ret, > + "failed to set adc clk rate\n"); > =20 > platform_set_drvdata(pdev, indio_dev); > =20 >=20