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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fad48dcsm826174066b.25.2025.11.16.04.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Nov 2025 04:00:48 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Krzysztof Kozlowski Cc: wens@csie.org, samuel@sholland.org, mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 6/7] dt-bindings: display: allwinner: Update H616 DE33 binding Date: Sun, 16 Nov 2025 13:00:47 +0100 Message-ID: <10753322.nUPlyArG6x@jernej-laptop> In-Reply-To: <4b4ebcc2-491a-42d3-9758-60de80ce5eb6@kernel.org> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> <20251116-pigeon-of-optimal-blizzard-2cb3b3@kuoka> <4b4ebcc2-491a-42d3-9758-60de80ce5eb6@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251116_040050_944991_2D1627C2 X-CRM114-Status: GOOD ( 21.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi! Dne nedelja, 16. november 2025 ob 12:33:55 Srednjeevropski standardni =C4= =8Das je Krzysztof Kozlowski napisal(a): > On 16/11/2025 12:33, Krzysztof Kozlowski wrote: > > On Sat, Nov 15, 2025 at 03:13:46PM +0100, Jernej Skrabec wrote: > >> As it turns out, current H616 DE33 binding was written based on > >> incomplete understanding of DE33 design. Namely, planes are shared > >> resource and not tied to specific mixer, which was the case for previo= us > >> generations of Display Engine (DE3 and earlier). > >> > >> This means that current DE33 binding doesn't properly reflect HW and > >> using it would mean that second mixer (used for second display output) > >> can't be supported. > >> > >> Update DE33 mixer binding so instead of referencing planes register > >> space, it contains phandle to newly introduced DE33 planes node. > >> > >> There is no user of this binding yet, so changes can be made safely, > >> without breaking any backward compatibility. > >=20 > > And why would you configure statically - per soc - always the same plane > > as per mixer? If you do that, it means it is really fixed and internal > > to display engine thus should not be exposed in DT. Not sure I understand what you mean. H616 SoC has 6 planes which are represented with single DE33 planes node (see previous DT binding).=20 Driver has to decide initial allocation. For example, 3 planes for each mixer. However, nothing prevents to allocate 1 plane to first mixer and 5 to other. You can even allocate all 6 planes to one mixer and none to the other, if board has only one output enabled. In any case, plane allocation is runtime decision and has nothing to do with DT. Since planes are shared resource, their register space can't be assigned to only one mixer. See [1] for example how this would look like. > >=20 > > Describing each IP block resource in DT is way too granular. > >=20 >=20 > BTW, everything is update, thus subject is really non-informative. I guess "fix" would be more descriptive. Best regards, Jernej [1] https://github.com/jernejsk/linux-1/blob/d93d56d92db52c7ff228c0532a1045= de02e0662c/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi#L181-L235