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Fri, 20 Jun 2025 15:09:58 +0800 (AWST) Message-ID: <10d493cb37748aeb1f4c97856929845727c4c3bc.camel@codeconstruct.com.au> Subject: Re: [PATCH 6/7] pinctrl: aspeed-g6: Add PCIe RC PERST pin group From: Andrew Jeffery To: Jacky Chou , bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, vkoul@kernel.org, kishon@kernel.org, linus.walleij@linaro.org, p.zabel@pengutronix.de, linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org Cc: elbadrym@google.com, romlem@google.com, anhphan@google.com, wak@google.com, yuxiaozhang@google.com, BMC-SW@aspeedtech.com Date: Fri, 20 Jun 2025 16:39:57 +0930 In-Reply-To: <20250613033001.3153637-7-jacky_chou@aspeedtech.com> References: <20250613033001.3153637-1-jacky_chou@aspeedtech.com> <20250613033001.3153637-7-jacky_chou@aspeedtech.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4-2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250620_001003_432153_67B4BAD0 X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2025-06-13 at 11:30 +0800, Jacky Chou wrote: > The PCIe RC PERST uses SSPRST# as PERST#=C2=A0 and enable this pin > to output. >=20 > Signed-off-by: Jacky Chou > --- > =C2=A0drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 12 +++++++++++- > =C2=A01 file changed, 11 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl= /aspeed/pinctrl-aspeed-g6.c > index 5a7cd0a88687..c751703acdb9 100644 > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c > @@ -17,6 +17,7 @@ > =C2=A0#include "../pinctrl-utils.h" > =C2=A0#include "pinctrl-aspeed.h" > =C2=A0 > +#define SCU040=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A00x04= 0 /* Reset Control Set 1=C2=A0 */ > =C2=A0#define SCU400=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A00x400 /* Multi-function Pin Control #1=C2=A0 */ > =C2=A0#define SCU404=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A00x404 /* Multi-function Pin Control #2=C2=A0 */ > =C2=A0#define SCU40C=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A00x40C /* Multi-function Pin Control #3=C2=A0 */ > @@ -52,7 +53,7 @@ > =C2=A0#define SCU6D0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A00x6D0 /* Multi-function Pin Control #29 */ > =C2=A0#define SCUC20=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A00xC20 /* PCIE configuration Setting Control */ > =C2=A0 > -#define ASPEED_G6_NR_PINS 256 > +#define ASPEED_G6_NR_PINS 258 > =C2=A0 > =C2=A0#define M24 0 > =C2=A0SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); > @@ -1636,6 +1637,12 @@ FUNC_DECL_1(USB11BHID, USBB); > =C2=A0FUNC_DECL_1(USB2BD, USBB); > =C2=A0FUNC_DECL_1(USB2BH, USBB); > =C2=A0 > +#define D7 257 > +SIG_EXPR_LIST_DECL_SESG(D7, RCRST, PCIERC1, SIG_DESC_SET(SCU040, 19), The documentation for SCU040[19] says it will assert the reset. I expect that's not what's desired. > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0SIG_DESC_= SET(SCU500, 24)); SCU500[24] seems okay. > +PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, RCRST)); > +FUNC_GROUP_DECL(PCIERC1, D7); It only makes sense to describe pins with multiple functions. The other function this pin has is the reset line for the secondary service processor. Can we describe that too? Andrew