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Thu, 08 Oct 2026 04:25:11 -0700 (PDT) X-Received: by 2002:a17:903:2acb:b0:2e5:36a9:400e with SMTP id d9443c01a7336-2e600500cd9mr40857685ad.39.1791458711093; Thu, 08 Oct 2026 04:25:11 -0700 (PDT) Received: from [10.218.18.193] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e6047201e6sm22775505ad.37.2026.10.08.04.25.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Oct 2026 04:25:10 -0700 (PDT) Message-ID: <10fe8480-21ec-4e44-ab21-d88bf2ef03e0@oss.qualcomm.com> Date: Thu, 8 Oct 2026 16:55:03 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 03/14] ASoC: mediatek: mt8195: Fix register access clock error handling To: phucduc.bui@gmail.com, Mark Brown , AngeloGioacchino Del Regno , Trevor Wu Cc: Liam Girdwood , Matthias Brugger , Jaroslav Kysela , Takashi Iwai , Kuninori Morimoto , cassiogabrielcontato@gmail.com, Mukesh Ojha , Liviu Dudau , Haotian Zhang , HariKrishna Sagala , linux-sound@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, ajay.nandam@oss.qualcomm.com References: <20261005110257.50145-1-phucduc.bui@gmail.com> <20261005110257.50145-4-phucduc.bui@gmail.com> Content-Language: en-US From: Ajay Kumar Nandam In-Reply-To: <20261005110257.50145-4-phucduc.bui@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA4MDA0NSBTYWx0ZWRfX6HhxwkxzI9iN bfcXzoFOcnFjRkA7GbfUQcxx1sh62UMi4gceUF35Icwft/9g7hEpEwvzt1F2JG4F12/PFM20oSx nkQoE1uvPIkU/stJBNkw0OhF/qNpiFBZ0tTJ4tQL4BY33OSs0DVVdC6tIxp0ys34IodTr/kCoU2 Ub/1tXQF3aFXsPwwoXWPydij97GqnQXLFYUcUWRTcoV6VE0/hCQJQ5Pz3cjnDjVSabPWSpCKOZp 7dkZoH914SOaZjFdLUfw2lF9fX0ouRuCVuAF5r8Iud+jR38VzGyTMIve593gstzGiaPcTSb0fBo MaT9Os/VP7RDJn5mFjUbhTHcE3H6aJPF6WodophfMYFsOZFR30irdAcyyH+EPH/t91UwqmpeMGp Q+1W7Frj4jAFlNgCydKOHokMZPGW5bIAhk8t4q1lnt1Kl121VOBIrpCfRe5piqIOPSuD2jCy79S u72tNQMb9jpY/AYCuyw== X-Proofpoint-ORIG-GUID: DkPCUkqHE3ykfXVso86MkuOdUToFAUjs X-Proofpoint-GUID: DkPCUkqHE3ykfXVso86MkuOdUToFAUjs X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA4MDA0NSBTYWx0ZWRfXwij3k/d0lBmy t5qOhO1/vdT56AK2cOeA65FUYUlmSPJx5xWJ/oeMjA8BzgE7sLN6kwD5fJOoIFyAxOMMxOIazwA IHXDKmKNYzYtOM9GAYQ0Mf3MGQO54fo= X-Authority-Analysis: v=2.4 cv=KcdHIgYD c=1 sm=1 tr=0 ts=6ac77d98 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=rZdDH30vr1OGgawLJCYA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-08_04,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610080045 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261008_122518_480396_8A647A06 X-CRM114-Status: GOOD ( 25.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/5/2026 4:32 PM, phucduc.bui@gmail.com wrote: > From: bui duc phuc > > Check the return value of mt8195_afe_enable_clk() when enabling the > register access clocks. > > If enabling a clock fails, disable the clocks that were already > enabled and propagate the error to the caller > > Fixes: 6746cc858259 ("ASoC: mediatek: mt8195: add platform driver") > Signed-off-by: bui duc phuc Reviewed-by: Ajay Kumar Nandam > --- > sound/soc/mediatek/mt8195/mt8195-afe-clk.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c > index 12d8159338be..34c828fdea29 100644 > --- a/sound/soc/mediatek/mt8195/mt8195-afe-clk.c > +++ b/sound/soc/mediatek/mt8195/mt8195-afe-clk.c > @@ -599,7 +599,7 @@ static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_t > int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) > { > struct mt8195_afe_private *afe_priv = afe->platform_priv; > - int i; > + int i, ret; > static const unsigned int clk_array[] = { > MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */ > MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */ > @@ -611,10 +611,19 @@ int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) > MT8195_CLK_AUD_A1SYS, /* AFE HW clock */ > }; > > - for (i = 0; i < ARRAY_SIZE(clk_array); i++) > - mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); > + for (i = 0; i < ARRAY_SIZE(clk_array); i++) { > + ret = mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); > + if (ret) > + goto err_disable_clk; > + } > > return 0; > + > +err_disable_clk: > + while (--i >= 0) > + mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); > + > + return ret; > } > > int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe)