[PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960

[PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960

[Manivannan Sadhasivam]

Enable SPI0 and SPI4 exposed on the Low and High speed expansion
connectors of Rock960.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
index 12285c51cceb..7498344d4a73 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
@@ -114,6 +114,18 @@
 	};
 };
 
+&spi0 {
+	/* On Low speed expansion */
+	label = "LS-SPI0";
+	status = "okay";
+};
+
+&spi4 {
+	/* On High speed expansion */
+	label = "HS-SPI1";
+	status = "okay";
+};
+
 &usbdrd_dwc3_0 {
 	dr_mode = "otg";
 };
-- 
2.17.1


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[PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus

[Manivannan Sadhasivam]

Enable SPI1 exposed on both Low and High speed expansion connectors
of Ficus. SPI1 has 3 different chip selects wired as below:

CS0 - Serial Flash (unpopulated)
CS1 - Low Speed expansion
CS2 - High Speed expansion

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
index 027d428917b8..9baa378fc770 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
@@ -146,6 +146,12 @@
 	};
 };
 
+&spi1 {
+	/* On both Low speed and High speed expansion */
+	cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
+	status = "okay";
+};
+
 &usbdrd_dwc3_0 {
 	dr_mode = "host";
 };
-- 
2.17.1


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Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus

[Heiko Stuebner]

Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> Enable SPI1 exposed on both Low and High speed expansion connectors
> of Ficus. SPI1 has 3 different chip selects wired as below:
> 
> CS0 - Serial Flash (unpopulated)
> CS1 - Low Speed expansion
> CS2 - High Speed expansion
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> index 027d428917b8..9baa378fc770 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> @@ -146,6 +146,12 @@
>  	};
>  };
>  
> +&spi1 {
> +	/* On both Low speed and High speed expansion */
> +	cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;

cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
The flash is part of the schematics, so there might be board with
it pre-populated or people might put a flash chip on it.

Also please use the constants for pin specification (RK_PA6, RK_PA7 above)


Heiko

> +	status = "okay";
> +};
> +
>  &usbdrd_dwc3_0 {
>  	dr_mode = "host";
>  };
> 





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Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus

[Manivannan Sadhasivam]

On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote:
> Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> > Enable SPI1 exposed on both Low and High speed expansion connectors
> > of Ficus. SPI1 has 3 different chip selects wired as below:
> > 
> > CS0 - Serial Flash (unpopulated)
> > CS1 - Low Speed expansion
> > CS2 - High Speed expansion
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > index 027d428917b8..9baa378fc770 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > @@ -146,6 +146,12 @@
> >  	};
> >  };
> >  
> > +&spi1 {
> > +	/* On both Low speed and High speed expansion */
> > +	cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
> 
> cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
> The flash is part of the schematics, so there might be board with
> it pre-populated or people might put a flash chip on it.
> 

Why? CS0 is owned by the SPI controller itself, so we can't use it as
a GPIO. Otherwise, we need to change the pinctrl definition of it, which
doesn't look good to me.

> Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
> 

Sure.

Thanks,
Mani

> 
> Heiko
> 
> > +	status = "okay";
> > +};
> > +
> >  &usbdrd_dwc3_0 {
> >  	dr_mode = "host";
> >  };
> > 
> 
> 
> 
> 

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Re: [PATCH 2/2] arm64: dts: rockchip: Enable SPI1 on Ficus

[Heiko Stuebner]

Am Dienstag, 7. Mai 2019, 13:36:35 CEST schrieb Manivannan Sadhasivam:
> On Tue, May 07, 2019 at 01:22:03PM +0200, Heiko Stuebner wrote:
> > Am Montag, 6. Mai 2019, 14:04:58 CEST schrieb Manivannan Sadhasivam:
> > > Enable SPI1 exposed on both Low and High speed expansion connectors
> > > of Ficus. SPI1 has 3 different chip selects wired as below:
> > > 
> > > CS0 - Serial Flash (unpopulated)
> > > CS1 - Low Speed expansion
> > > CS2 - High Speed expansion
> > > 
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/rk3399-ficus.dts | 6 ++++++
> > >  1 file changed, 6 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > index 027d428917b8..9baa378fc770 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-ficus.dts
> > > @@ -146,6 +146,12 @@
> > >  	};
> > >  };
> > >  
> > > +&spi1 {
> > > +	/* On both Low speed and High speed expansion */
> > > +	cs-gpios = <0>, <&gpio4 6 0>, <&gpio4 7 0>;
> > 
> > cs0 should still be part of the cs-gpios though (gpio1 RK_PB2).
> > The flash is part of the schematics, so there might be board with
> > it pre-populated or people might put a flash chip on it.
> > 
> 
> Why? CS0 is owned by the SPI controller itself, so we can't use it as
> a GPIO. Otherwise, we need to change the pinctrl definition of it, which
> doesn't look good to me.

Ok, but are you sure mixing both pinctrl-based chip-select with gpio-based
chip-select will actually work when the spi-flash is populated?

But it looks like you're right in that spi_set_cs() checks for a gpio-cs
first and falls back to the controller-based chip-select.

So I guess this can stay as it is.

> 
> > Also please use the constants for pin specification (RK_PA6, RK_PA7 above)
> > 
> 
> Sure.

Thanks
Heiko

> 
> Thanks,
> Mani
> 
> > 
> > Heiko
> > 
> > > +	status = "okay";
> > > +};
> > > +
> > >  &usbdrd_dwc3_0 {
> > >  	dr_mode = "host";
> > >  };
> > > 
> > 
> > 
> > 
> > 
> 





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Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960

[Heiko Stuebner]

Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> connectors of Rock960.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> index 12285c51cceb..7498344d4a73 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> @@ -114,6 +114,18 @@
>  	};
>  };
>  
> +&spi0 {
> +	/* On Low speed expansion */
> +	label = "LS-SPI0";

where does the label property come from and what does it do?
It's not part of the rockchip-spi / general-spi binding.


Heiko

> +	status = "okay";
> +};
> +
> +&spi4 {
> +	/* On High speed expansion */
> +	label = "HS-SPI1";
> +	status = "okay";
> +};
> +
>  &usbdrd_dwc3_0 {
>  	dr_mode = "otg";
>  };
> 





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Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960

[Manivannan Sadhasivam]

Hi Heiko,

On Tue, May 07, 2019 at 01:17:10PM +0200, Heiko Stuebner wrote:
> Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> > Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> > connectors of Rock960.
> > 
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > index 12285c51cceb..7498344d4a73 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > @@ -114,6 +114,18 @@
> >  	};
> >  };
> >  
> > +&spi0 {
> > +	/* On Low speed expansion */
> > +	label = "LS-SPI0";
> 
> where does the label property come from and what does it do?
> It's not part of the rockchip-spi / general-spi binding.
> 

It is not part of the binding but I thought it will provide the users
the information of the SPI bus as per the specification when they
look into devicetree.

If it doesn't makes sense, I can remove that!

Thanks,
Mani

> 
> Heiko
> 
> > +	status = "okay";
> > +};
> > +
> > +&spi4 {
> > +	/* On High speed expansion */
> > +	label = "HS-SPI1";
> > +	status = "okay";
> > +};
> > +
> >  &usbdrd_dwc3_0 {
> >  	dr_mode = "otg";
> >  };
> > 
> 
> 
> 
> 

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Re: [PATCH 1/2] arm64: dts: rockchip: Enable SPI0 and SPI4 on Rock960

[Heiko Stuebner]

Am Dienstag, 7. Mai 2019, 13:33:39 CEST schrieb Manivannan Sadhasivam:
> Hi Heiko,
> 
> On Tue, May 07, 2019 at 01:17:10PM +0200, Heiko Stuebner wrote:
> > Am Montag, 6. Mai 2019, 14:04:57 CEST schrieb Manivannan Sadhasivam:
> > > Enable SPI0 and SPI4 exposed on the Low and High speed expansion
> > > connectors of Rock960.
> > > 
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/rk3399-rock960.dts | 12 ++++++++++++
> > >  1 file changed, 12 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > index 12285c51cceb..7498344d4a73 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dts
> > > @@ -114,6 +114,18 @@
> > >  	};
> > >  };
> > >  
> > > +&spi0 {
> > > +	/* On Low speed expansion */
> > > +	label = "LS-SPI0";
> > 
> > where does the label property come from and what does it do?
> > It's not part of the rockchip-spi / general-spi binding.
> > 
> 
> It is not part of the binding but I thought it will provide the users
> the information of the SPI bus as per the specification when they
> look into devicetree.
> 
> If it doesn't makes sense, I can remove that!

please do :-) ... dt-bindings are supposed to be verifyable at some
point, so we shouldn't add undocumented properties.

Heiko

> 
> Thanks,
> Mani
> 
> > 
> > Heiko
> > 
> > > +	status = "okay";
> > > +};
> > > +
> > > +&spi4 {
> > > +	/* On High speed expansion */
> > > +	label = "HS-SPI1";
> > > +	status = "okay";
> > > +};
> > > +
> > >  &usbdrd_dwc3_0 {
> > >  	dr_mode = "otg";
> > >  };
> > > 
> > 
> > 
> > 
> > 
> 





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