From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F14FAC48BC4 for ; Fri, 16 Feb 2024 02:18:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To: References:Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+jkV3vZmxsyvL79dqTG35ReYoiwVlPC5GysJBokLWb0=; b=45PI7/+d1yNY24 zYTW9cd0jXYUnPuLQ0He/NwC6YkNxJhhIcYECSSzjIgJxEpbg/aU7MDxFTuwbkgp2VIAOufFA5oY5 qgx2Ae66SqGuFhaZtx5RBOWEYx1Q/W2uX73uQljeHSDRjjHXRMNegKl3qwCqOPuhs2B+S32nde4ZL bSHP9G8vVwMGw9mkETw4EkAMJsYCx/KdSqObKfTOo0yZ4tB2xpFTsyQkJ/RpA6Ajt1llLWkrKGDcC MODhfp+NZmgq1S5LSzSnzRAho9OJLCw/wEo2ZA/GAC/VoXK2em/mr8QYs1oFofPdTiZoa+xPr/Pdh 65kD5Z6vmhqzsf3SoPhA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rannf-00000000p4M-1WmU; Fri, 16 Feb 2024 02:18:03 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rannc-00000000p3R-1TBT; Fri, 16 Feb 2024 02:18:01 +0000 X-UUID: 97c348f6cc7111eea0bf134e88e6c2dc-20240215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=MIME-Version:Content-Transfer-Encoding:Content-ID:Content-Type:In-Reply-To:References:Message-ID:Date:Subject:CC:To:From; bh=Q3zqRSbGL88ZQAKnAWGaNm4JCUNopPk+KLDFLz4MXWg=; b=XnnrgnptWDllnDcN1DxQxYl73+MjRnaqOy4IW7MKYvA64zkx8Y0Bo2uURc8vEdlPVsHcyd7LYkjphFR1NI8EnInR/tr+Iqnod8SWClPDFAji2cA8EhTa0kPGePuxohRVDzgWy0I3L5s8XsMRfvMHl9wKeWbxUyvv5mHvSGiArm4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:0650acab-37be-4e24-b8b5-0a104e0a8a87,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6f543d0,CLOUDID:5d08f183-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 97c348f6cc7111eea0bf134e88e6c2dc-20240215 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 460111991; Thu, 15 Feb 2024 19:17:54 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Fri, 16 Feb 2024 10:17:51 +0800 Received: from APC01-PSA-obe.outbound.protection.outlook.com (172.21.101.237) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Fri, 16 Feb 2024 10:17:51 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CVbIvsQ5sT57QnRDeIk9TtKE8Wb9k8I4xOhxKkF02nbZTH+72IO9meOB+UNX5iJcdd27GI+q+Rr8NZ4VVRRW2m2J9v23UA4nKtNUiWU5beToN3TJ3rtl5D5cwMwaX7tqJ15um0DDPgqUO8x8KnowBkph4r4iS9LVTae15IB+15naY3n9fJ4NyV1VkPWle4BB9TTT5br9Y/v23jwcYIlUUK8WEYmRB2NbHQOV1Hxq6W8pVKVg17AW4gXSNpKzpPdUz+/HnwOpUTK/cdfVqr/5BQ/AiyqwP0QOTKbCfsCs7De7XlnZ7yrCTJDDkplaLQhU8Pt1gOCAjQpmR2r4j6S17Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Q3zqRSbGL88ZQAKnAWGaNm4JCUNopPk+KLDFLz4MXWg=; b=N/QhVD4Ekz45SDce0f2kUWZ4/gEw7Bo79vaENX2KyNOH28A1WkveVoNTzOe/pOOPAQO4G6rz9Me9h6PAieUhE6Fv47usMdo04ZHPqFCYkbE09DzIeEXtEWcRhiPu0OiSNe/oAUSZ4GFqLfk55I1Bmff/x3N8b5RWWLYgCXUz0p5kswWESnu0mXVevjuaXQeiMEQPJOsgWsdT8G1dS2T+ukUbwTn37kgjNBRooTCP/yuZiCy0iGSl8pvDK4DFyV1GBzV2A7q+r1x5auSajeM1zRinrvpFM7h7XTy4rzErYsJim1P0mKnBaFh6ctrw3U7O0op0xmflGfGaVk3Zus/AnA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=mediatek.com; dmarc=pass action=none header.from=mediatek.com; dkim=pass header.d=mediatek.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mediateko365.onmicrosoft.com; s=selector2-mediateko365-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Q3zqRSbGL88ZQAKnAWGaNm4JCUNopPk+KLDFLz4MXWg=; b=WTehXM4Gpu0FqtBm/U+cb2tUoP0iWuUuB+zZucPNJxk1RlsD16iHlnBWnIIFD/lZ/Svmn/90HygLEZFQgm7DndcW5/iEnJaxWhh8it54MKh1/2cKkfwjWOSE1akKBt80kun0vg7DnVecymYzvH0FsBtvG/A6eFnkInYA2RwVWwQ= Received: from TYZPR03MB6623.apcprd03.prod.outlook.com (2603:1096:400:1f5::13) by SG2PR03MB6729.apcprd03.prod.outlook.com (2603:1096:4:1d0::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.29; Fri, 16 Feb 2024 02:17:49 +0000 Received: from TYZPR03MB6623.apcprd03.prod.outlook.com ([fe80::a93d:863e:c0fd:109b]) by TYZPR03MB6623.apcprd03.prod.outlook.com ([fe80::a93d:863e:c0fd:109b%6]) with mapi id 15.20.7292.026; Fri, 16 Feb 2024 02:17:49 +0000 From: =?utf-8?B?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= To: "angelogioacchino.delregno@collabora.com" , "chunkuang.hu@kernel.org" CC: "linux-mediatek@lists.infradead.org" , "linux-kernel@vger.kernel.org" , =?utf-8?B?QmliYnkgSHNpZWggKOisnea/n+mBoCk=?= , "jason-ch.chen@mediatek.corp-partner.google.com" , =?utf-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?= , "daniel@ffwll.ch" , "p.zabel@pengutronix.de" , =?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?= , "seanpaul@chromium.org" , "dri-devel@lists.freedesktop.org" , "airlied@gmail.com" , "linux-arm-kernel@lists.infradead.org" , "matthias.bgg@gmail.com" , "fshao@chromium.org" Subject: Re: [PATCH v5 08/13] drm/mediatek: Support alpha blending in OVL Thread-Topic: [PATCH v5 08/13] drm/mediatek: Support alpha blending in OVL Thread-Index: AQHaX/dwe9hdcqVJEEqYchVXw9Rxv7ELPPcAgAD/xQA= Date: Fri, 16 Feb 2024 02:17:48 +0000 Message-ID: <111ddf7030051aa71d1283bd2eb4f23718eb8a9c.camel@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> <20240215101119.12629-9-shawn.sung@mediatek.com> <7664fece-c29a-4374-a59c-4ce8fe831494@collabora.com> In-Reply-To: <7664fece-c29a-4374-a59c-4ce8fe831494@collabora.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=mediatek.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR03MB6623:EE_|SG2PR03MB6729:EE_ x-ms-office365-filtering-correlation-id: c4a395cf-9d2b-475b-387a-08dc2e9578bb x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: B2u3DmtvOr8E+RPJwpt+0cgBNddl3KEX6JafTJqiB1np7+DARroIiVEhcSAXwOlg/IC30Ia437b2W0CzCjjwe2mhQAtt3tKnVBTzoZqxyaAWrjG3DMUKEK3DGwm6PbUAdRLPYwNZbypgSMMHOTju86MAusSG0uanxqxJ+nsc2ZtKj83AOyYA1Q62BXOUdco3mrTtr13M/FLr7JFMhc+UxuYx+2eOSu20Wo6P17bjDND0PMDTr4Y6Yynz/KYt+74iFkixAQ+Y1uT57etlxX6SB84wk6lSqmULPjMonoEt4lK2167VhETW0zMswZl3j7Eaj9EwLDK6q2q0IzqgpdNalOaQkMzpu6R0Lz77Ps+oZmyqC3CILB+3f4TSBXXD58qVok4o0aDqptDD2GECrq5XHvPqCxD4dK6op8vIh4NIzkzVLATMqupU5oeB4sVaNxuZmQXQdN3rIcChJFCgLjga/8R/zIh8dSoNehSsD1p/2IEiGbLL0CSQxW9RtWb2wriKglniGS+xNHdZqx/pzFCSFfPBpem/rx1cLrLZvpOFueZOnhMKiAR9z8yZEWaFA8krWeecN4IVsr/rT2no5yoYKfIZ3lufHpZLel2/z5QsNJmSh/vN4y641x9ZgI2DZysN x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:TYZPR03MB6623.apcprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(136003)(366004)(376002)(39860400002)(396003)(346002)(230922051799003)(451199024)(186009)(1800799012)(64100799003)(5660300002)(66556008)(64756008)(66946007)(76116006)(8676002)(66476007)(66446008)(4326008)(7416002)(8936002)(2906002)(38100700002)(85182001)(36756003)(122000001)(86362001)(83380400001)(6512007)(38070700009)(110136005)(316002)(478600001)(54906003)(6486002)(6506007)(41300700001)(26005)(2616005)(71200400001);DIR:OUT;SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?B?bGFwMzhxaXNLK2dkTytCYkR4a0VFZlR2YXF5ZlVJVWF2U3JkVFYwUEhiYm9s?= =?utf-8?B?VmhpNlZzWSt1U3o0MEViNUhRemlQSEhtM0dDYm9SaWRPL1NYd0psUDNYTmtV?= =?utf-8?B?TnhGUFpCcVZaL3dPVWkxeXhWdTRHY1d6YlozaVd4dUZWaG9iQUxPVDIxUW54?= =?utf-8?B?azdwMjFScGk3Y0d3WUJ2UWRSU3ljeG1pOFo1MWhlWmJpT3dndmFyYWdubVBm?= =?utf-8?B?Z2tWTTd1RVhaRnQ5cVFHajNlYjRNZGd0dVJINUYvTzV5WHZZY29ROTBUaHp0?= =?utf-8?B?b01YKzJ0cDlnVENhZ3Fhd2JVMXZjWHdmcmdHM1JVOE1lSTlvL3dVRHpVM1c4?= =?utf-8?B?YS92NnU0V3NJR2VKR003dHRIRDJMZDAwc0c3ajBYVFBzQkVFWjBuNFpXUUIw?= =?utf-8?B?QnZtc1RYbE40Qm9CWnkzSUtCbFozK1VocERhS1dLOE9pRzYvYTFySVFYNnBa?= =?utf-8?B?NktKS3piTjFud1ZkUEd5OWdnODJMSzM1WWk2Vlo4R1F3QUJwS0VUeG9rL255?= =?utf-8?B?b2gwY2R5U0kwYWRVYVFmTGJyWWVuNjcxOGpNQ3hRazYwSGVSdjZtQlNxVW4z?= =?utf-8?B?Yzd4ZGlSemY1dmtBTjBJbFVzak5FTk41TWVMcVVtamtsVEZncUpZNWpIMFl6?= =?utf-8?B?REhFK1F4N0lURjZxRGJDYWFDcnFDR3dUbFg5NjRPSzlMWlJlVnA3bXNTTUo1?= =?utf-8?B?VFVTRnRxOWI5dHlubFI3cXNpNHFqb0pmTWxpNHVTd3poeURBTk8raFZmVThW?= =?utf-8?B?M24wWXp0VlErV1k4czkrR1l6bnVzbXRDZkhWNVYwMGNpSndjbzNWWnZoemFV?= =?utf-8?B?WFg0WVYxbmFQYU1rcU1HYmE3NEM0N0x5eEVUWk1FKzZCczl1YWI2ejRtc2dJ?= =?utf-8?B?YVgwUWRJa1Zvc2ROKzZ6Z1NKSlVSK0ZDZGc3SmJmSmZPdFRYbzcwR0hMSUF1?= =?utf-8?B?TmhSTlNydEVRclozZ01OanlGb0sxWHNpVDVONjR5YnJhOXNnMGZ0cFdZTHh1?= =?utf-8?B?Z1JUWG9vZ05UOTVwNWFlQTBjSk10YnFwaXN1dWI2VDI5d0thcTNhL2NVTXFk?= =?utf-8?B?SGdaQTEyMGRYRE8xRFExYUJPSFpFbXlQU0J1akpnMUlmNHpUNi9rQnUzL2o0?= =?utf-8?B?SmlPZnRxbmRqci90VGlpZWZmZUFwdHB2d2lackJlMVNlNEExK3VFNGpwS0Qy?= =?utf-8?B?REhMeFBJdnNKSjZYNFFVb1hlWWJDcXB5ZURnM0JYUHh3d2dha3ZzYjJibWNh?= =?utf-8?B?bGJEOHo5NzdQbldZUU85REFIUEJPaFFTYy9vRzd5OHhFazJzR3RoWU9ua00x?= =?utf-8?B?azhacFIwZ2Jxc0Z4WHhFMDhVQjJuU0lkcVZsdWRQRnY1RnZxU2VUV3ZnTVND?= =?utf-8?B?aTJybHZ4TUliUDA4WUtoYXJ5NE1QZmh0b1d4RDhxR01NcU9vMWhsYWlYa3Rn?= =?utf-8?B?c2tVVkpPdUJiNU9iSW5ncTFpQkdrTTJqWFo4S25TVnRUT2IzRVIveUpORnZK?= =?utf-8?B?ZnpjSWdLUGdMd2dPWDJxN0daa2t6YUwrdGNuL0d4OEhmUTBSU1RuOHdjTnYy?= =?utf-8?B?VmtDVDN5WE5adEpHWmU5Z1ZIdlQ3aVYyd3JEVTRMWUR1UmV1eHlPeFZlUWUx?= =?utf-8?B?RVVqU1U5WmN1L3JXSWZxVUxGMmdtOENmRDJVZDFRMW1rSkdrWWdNdWJiVExi?= =?utf-8?B?QTZha0RhVStucUFuSEZjR2dLcndhZXBPOWQ3OEJiTzI3QWVtSlkvM1QxQXFl?= =?utf-8?B?c1dZVk1oUlpZUWZPeUc1b1Q0TUgybWtrVndTS29EUU9rcll3OEZsNEgwOFAy?= =?utf-8?B?enFmNy9oU3NDd1kyaG01QnZTbDBTOW9EM2xoVC8rY0JwWXl5YzZqZUdXZXBh?= =?utf-8?B?SStJY2hLZHFRaDBCRFl1eXpHMkpMQXNWTnh0OXhrb3htQ3RnRVlSUVBkZitl?= =?utf-8?B?NnUvNVRUVGphQkVGS3d4WG9KMzNrb3JvQU1qVVBrZ1JvbGtMVUNyTUR1NHRE?= =?utf-8?B?bzRtMHRUSUd6a0NFQWRKdHFheFBUTlNQOWxVUVEzRXJYcWl5U0xsb0N5dytr?= =?utf-8?B?ZmtrNHdPT2ZSNjdjVUpOOHhsTzJHRm1aQXQvSVJZWlQxZmU3aWVydVh3b2cy?= =?utf-8?B?R0MrR2R5RmwrZ0dpNFJUNFE3VlpDUTh4ald5aHRlN2ZscWo1L2oyZjEzNkxO?= =?utf-8?B?Z2c9PQ==?= Content-ID: <291783745AD9E647B58C56D70C5E6C22@apcprd03.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYZPR03MB6623.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c4a395cf-9d2b-475b-387a-08dc2e9578bb X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Feb 2024 02:17:48.9562 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a7687ede-7a6b-4ef6-bace-642f677fbe31 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3HQEi3uyhd/ur1G2JHsdy4PDoBHP8m1dhui8CDuNhCHasA8DixPpTza0nadVNqwBVA94JrI6EgsNEraLw/szyA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR03MB6729 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--23.652700-8.000000 X-TMASE-MatchedRID: dc8Jy61QoRrUL3YCMmnG4kD6z8N1m1ALjLOy13Cgb49qSjxROy+AU/wt lOVHF2NRUmsNbSHn8eD5qR7J2CotBpz3nEP4SjjAbBu6+EIezdwxmlBLt0TR1rFRmrhHzmfvwSc 2bbTUBMmjmrD+IUq29gG2ORx9Eyap5W9n1Vmnd4QdxBAG5/hkWwreImldQ5BDv8D7QPW2jo93Cp W7baJzYFfpQg84b6ItRtmamHCmvybSV+Xuk4c29rYUrknUqEL7QKuv8uQBDjp9WQH9y/pSXXLOJ Owcwkpm5HqxcSv17rhfDKKVLAxShRgHZ8655DOP0gVVXNgaM0pZDL1gLmoa/PoA9r2LThYYKrau Xd3MZDUD/dHyT/Xh7Q== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--23.652700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: D08287FE8943C1DC329152FC9BD12559857DD47B058327BF8F0CD43661BD39722000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240215_181800_431469_92D2CE71 X-CRM114-Status: GOOD ( 17.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Angelo, On Thu, 2024-02-15 at 12:02 +0100, AngeloGioacchino Del Regno wrote: > Il 15/02/24 11:11, Hsiao Chien Sung ha scritto: > > Support "Pre-multiplied" and "None" blend mode on MediaTek's chips. > > Before this patch, only the "Coverage" mode is supported. > > > > Please refer to the description of the commit > > "drm/mediatek: Support alpha blending in display driver" > > for more information. > > > > Signed-off-by: Hsiao Chien Sung > > --- > > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 83 > > +++++++++++++++++++++---- > > 1 file changed, 72 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > index c42fce38a35eb..98c989fddcc08 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > > @@ -39,6 +39,7 @@ > > #define DISP_REG_OVL_PITCH_MSB(n) (0x0040 + 0x20 * (n)) > > #define OVL_PITCH_MSB_2ND_SUBBUF BIT(16) > > #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 > > * (n)) > > +#define OVL_CONST_BLEND BIT(28) > > #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n)) > > #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n)) > > #define DISP_REG_OVL_ADDR_MT2701 0x0040 > > @@ -52,13 +53,16 @@ > > #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4) > > #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8) > > > > +#define OVL_CON_CLRFMT_MAN BIT(23) > > #define OVL_CON_BYTE_SWAP BIT(24) > > -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > > +#define OVL_CON_RGB_SWAP BIT(25) > > #define OVL_CON_CLRFMT_RGB (1 << 12) > > #define OVL_CON_CLRFMT_RGBA8888 (2 << 12) > > #define OVL_CON_CLRFMT_ARGB8888 (3 << 12) > > #define OVL_CON_CLRFMT_UYVY (4 << 12) > > #define OVL_CON_CLRFMT_YUYV (5 << 12) > > +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) > > +#define OVL_CON_CLRFMT_PARGB8888 (OVL_CON_CLRFMT_ARGB8888 | > > OVL_CON_CLRFMT_MAN) > > #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data- > > >fmt_rgb565_is_0 ? \ > > 0 : OVL_CON_CLRFMT_RGB) > > #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data- > > >fmt_rgb565_is_0 ? \ > > @@ -72,6 +76,22 @@ > > #define OVL_CON_VIRT_FLIP BIT(9) > > #define OVL_CON_HORZ_FLIP BIT(10) > > > > +static inline bool is_10bit_rgb(u32 fmt) > > +{ > > + switch (fmt) { > > + case DRM_FORMAT_XRGB2101010: > > + case DRM_FORMAT_ARGB2101010: > > + case DRM_FORMAT_RGBX1010102: > > + case DRM_FORMAT_RGBA1010102: > > + case DRM_FORMAT_XBGR2101010: > > + case DRM_FORMAT_ABGR2101010: > > + case DRM_FORMAT_BGRX1010102: > > + case DRM_FORMAT_BGRA1010102: > > + return true; > > + } > > + return false; > > +} > > + > > static const u32 mt8173_formats[] = { > > DRM_FORMAT_XRGB8888, > > DRM_FORMAT_ARGB8888, > > @@ -89,12 +109,20 @@ static const u32 mt8173_formats[] = { > > static const u32 mt8195_formats[] = { > > DRM_FORMAT_XRGB8888, > > DRM_FORMAT_ARGB8888, > > + DRM_FORMAT_XRGB2101010, > > DRM_FORMAT_ARGB2101010, > > DRM_FORMAT_BGRX8888, > > DRM_FORMAT_BGRA8888, > > + DRM_FORMAT_BGRX1010102, > > DRM_FORMAT_BGRA1010102, > > DRM_FORMAT_ABGR8888, > > DRM_FORMAT_XBGR8888, > > + DRM_FORMAT_XBGR2101010, > > + DRM_FORMAT_ABGR2101010, > > + DRM_FORMAT_RGBX8888, > > + DRM_FORMAT_RGBA8888, > > + DRM_FORMAT_RGBX1010102, > > + DRM_FORMAT_RGBA1010102, > > DRM_FORMAT_RGB888, > > DRM_FORMAT_BGR888, > > DRM_FORMAT_RGB565, > > @@ -254,9 +282,7 @@ static void mtk_ovl_set_bit_depth(struct device > > *dev, int idx, u32 format, > > reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); > > reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); > > > > - if (format == DRM_FORMAT_RGBA1010102 || > > - format == DRM_FORMAT_BGRA1010102 || > > - format == DRM_FORMAT_ARGB2101010) > > + if (is_10bit_rgb(format)) > > bit_depth = OVL_CON_CLRFMT_10_BIT; > > > > reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); > > @@ -274,7 +300,13 @@ void mtk_ovl_config(struct device *dev, > > unsigned int w, > > if (w != 0 && h != 0) > > mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl- > > >cmdq_reg, ovl->regs, > > DISP_REG_OVL_ROI_SIZE); > > - mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, > > DISP_REG_OVL_ROI_BGCLR); > > + > > + /* > > + * The background color should be opaque black (ARGB), > > + * otherwise there will be no effect with alpha blend > > + */ > > + mtk_ddp_write_relaxed(cmdq_pkt, 0xff000000, &ovl->cmdq_reg, > > + ovl->regs, DISP_REG_OVL_ROI_BGCLR); > > Multiple (all of?) OVL color registers, like{L0-3,EL0- > 2}_YUV1BIT_COLOR(x), > ROI_BGCLR, L{0-3}_CLR and others do follow this exact layout: > > #define OVL_COLOR_ALPHA GENMASK(31, 24) > #define OVL_COLOR_GREEN GENMASK(23, 16) > #define OVL_COLOR_RED GENMASK(15, 8) > #define OVL_COLOR_BLUE GENMASK(7, 0) > > ...so we can define those as they're valid for multiple registers, > and then > we can use the definition instead of an apparently random value. Got it. Will modify it in the next version. > > /* > * The background color should be opaque black (ARGB), > * otherwise there will be no effect with alpha blend > */ > mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, > ovl->regs, DISP_REG_OVL_ROI_BGCLR); > > Everything else looks ok. > > Regards, > Angelo > Thanks, Shawn _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel