From: arnd@arndb.de (Arnd Bergmann)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05
Date: Tue, 13 Oct 2015 17:00:49 +0200 [thread overview]
Message-ID: <11677087.JbqAo0FWJE@wuerfel> (raw)
In-Reply-To: <EE11001F9E5DDD47B7634E2F8A612F2E16242C92@lhreml503-mbs>
On Tuesday 13 October 2015 14:49:07 Gabriele Paoloni wrote:
> > On Monday 12 October 2015 16:35:45 Bjorn Helgaas wrote:
> > >
> > > > +{
> > > > + u64 addr;
> > > > + struct device_node *msi_node;
> > > > + struct resource res;
> > > > + struct device_node *np = pp->dev->of_node;
> > > > + struct hisi_pcie *pcie = to_hisi_pcie(pp);
> > > > +
> > > > + msi_node = of_parse_phandle(np, "msi-parent", 0);
> > > > + if (!msi_node) {
> > > > + dev_err(pp->dev, "failed to find msi-parent\n");
> > > > + return -EINVAL;
> > > > + }
> > > > + of_address_to_resource(msi_node, 0, &res);
> > >
> > > Does this use the "msi-parent" node in the same way as other drivers
> > > do? I'm sure there must be other places where we extract struct
> > > resource information from an "msi-parent" node, but I don't see them.
> > >
> > > I'm trying to verify that this isn't some kind of incompatible
> > > extension of the "msi-parent" property. I cc'd Arnd and Rob (DT
> > > experts).
> >
> > This is not ok, what this does is that it relies on a particular
> > implementation of the MSI controller and directly accesses its
> > registers.
>
> Hi Arnd, thanks for reviewing.
>
> What we do is to retrieve the msi-parent physical address and we store it
> in our internal PCIe register locations...
Ah, thanks for the clarification, I missed that part.
> So we do not operate directly on the msi controller registers...
>
> So I wonder if the current implementation is Ok to retrieve the
> msi-parent address....
Not sure. Why do you do this? Normally the PCI host does not know
or care about the address of the MSI controller, because the messages
are just passed up to the parent bus as DMA transfers.
I don't think what you do here is safe because the 'reg' property
of the MSI controller might point to the address that is used for
the message directly.
Arnd
next prev parent reply other threads:[~2015-10-13 15:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-10 2:59 [PATCH v10 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
2015-10-10 2:59 ` [PATCH v10 1/6] PCI: designware: move calculation of bus addresses to DRA7xx Zhou Wang
2015-10-10 2:59 ` [PATCH v10 2/6] ARM/PCI: remove align_resource in pci_sys_data Zhou Wang
2015-10-10 2:59 ` [PATCH v10 3/6] PCI: designware: Add ARM64 support Zhou Wang
2015-10-10 2:59 ` [PATCH v10 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
2015-10-12 21:35 ` Bjorn Helgaas
2015-10-13 6:33 ` Zhou Wang
2015-10-13 6:58 ` Gabriele Paoloni
2015-10-13 11:18 ` Arnd Bergmann
2015-10-14 8:34 ` Gabriele Paoloni
2015-10-14 9:04 ` Arnd Bergmann
2015-10-14 9:31 ` Gabriele Paoloni
2015-10-14 9:42 ` Arnd Bergmann
2015-10-14 9:56 ` Gabriele Paoloni
2015-10-13 11:12 ` Arnd Bergmann
2015-10-13 14:49 ` Gabriele Paoloni
2015-10-13 15:00 ` Arnd Bergmann [this message]
2015-10-14 8:59 ` Zhou Wang
2015-10-14 9:06 ` Arnd Bergmann
2015-10-14 9:44 ` Zhou Wang
2015-10-14 21:56 ` Arnd Bergmann
2015-10-15 8:33 ` Zhou Wang
2015-10-10 2:59 ` [PATCH v10 5/6] Documentation: DT: Add HiSilicon PCIe host binding Zhou Wang
2015-10-10 2:59 ` [PATCH v10 6/6] MAINTAINERS: Add pcie-hisi maintainer Zhou Wang
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