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Wed, 11 Dec 2024 03:08:24 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BB38NcM021221 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 03:08:23 GMT Received: from [10.216.62.17] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 10 Dec 2024 19:08:18 -0800 Message-ID: <1219b46d-2aea-4377-a8ca-024039ee1499@quicinc.com> Date: Wed, 11 Dec 2024 08:38:15 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/msm/a6xx: Skip gpu secure fw load in EL2 mode To: Bjorn Andersson CC: Rob Clark , Pavan Kondeti , Sean Paul , Konrad Dybcio , Abhinav Kumar , "Dmitry Baryshkov" , Marijn Suijten , David Airlie , "Simona Vetter" , Elliot Berman , , , , , References: <20241209-drm-msm-kvm-support-v1-1-1c983a8a8087@quicinc.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0m9eFUcuyq9Ye7zYc1eZ8aC2lb1PuFwm X-Proofpoint-ORIG-GUID: 0m9eFUcuyq9Ye7zYc1eZ8aC2lb1PuFwm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 suspectscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110022 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241210_190830_987289_764D1EF8 X-CRM114-Status: GOOD ( 17.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/11/2024 6:43 AM, Bjorn Andersson wrote: > On Tue, Dec 10, 2024 at 02:22:27AM +0530, Akhil P Oommen wrote: >> On 12/10/2024 1:24 AM, Rob Clark wrote: >>> On Mon, Dec 9, 2024 at 12:20 AM Akhil P Oommen wrote: >>>> >>>> When kernel is booted in EL2, SECVID registers are accessible to the >>>> KMD. So we can use that to switch GPU's secure mode to avoid dependency >>>> on Zap firmware. Also, we can't load a secure firmware without a >>>> hypervisor that supports it. >>> >>> Shouldn't we do this based on whether zap node is in dtb (and not disabled)? >> >> This is better, isn't it? Otherwise, multiple overlays should be >> maintained for each soc/board since EL2 can be toggled from bootloader. >> And this feature is likely going to be more widely available. >> > > The DeviceTree passed to the OS needs to describe the world that said OS > is going to operate in. If you change the world you need to change the > description. > There are several other examples where this would be necessary > (remoteproc and watchdog to name two examples from the Qualcomm upstream > world). But basic things work without those changes, right? For eg: Desktop UI > > So, if we can cover this by zap-shader being enabled or disabled, that > sounds like a clean and scaleable solution. I think we are focusing too much on zap shader. If the driver can determine itself about access to its register, shouldn't it be allowed to use that? -Akhil > > Regards, > Bjorn