linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/5] arm: use the spinlocked, generic atomic64 support
Date: Tue, 15 Dec 2009 10:24:48 +0000	[thread overview]
Message-ID: <1260872688.1569.19.camel@pc1117.cambridge.arm.com> (raw)
In-Reply-To: <alpine.LFD.2.00.0912141443010.23173@xanadu.home>

On Mon, 2009-12-14 at 19:52 +0000, Nicolas Pitre wrote:
> On Mon, 14 Dec 2009, Will Deacon wrote:
> > *Nicolas Pitre wrote:
> >
> > > Can't a variant of include/linux/cnt32_to_63.h be used here?>
> > > typedef struct {
> > >     atomic_t low;
> > >     u32 high;
> > > } atomic64_t;
> > >
> > > static inline void atomic64_set(atomic64_t *ptr, u64 new_val)
> > > {
> > >     u32 low = new_val;
> > >     u32 high = new_val >> 32;
> > >     BUG_ON(high & 0x80000000);
> > >     atomic_set(&ptr->low, low);
> > >     ptr->high = (high & 0x7fffffff) | (low & 0x80000000);
> > > }
> >
> > How do you ensure that this is atomic? To me it looks like one CPU
> > could write the lower 32-bits and another could write the upper 32,
> > leaving the memory location in an inconsistent state.
> 
> This one is indeed not exactly atomic.  It isn't the interesting case
> either though.  Probably a strd could fix that.

STRD is not guaranteed to be atomic either (it may be implemented as a
succession of two word stores like an STM), especially when the low
latency interrupt mode is enabled.

-- 
Catalin

  reply	other threads:[~2009-12-15 10:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-12-14 14:04 ARMv6 performance counters v2 Jamie Iles
2009-12-14 14:04 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-14 14:04   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2009-12-14 14:04     ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2009-12-14 14:04       ` [PATCH 4/5] arm: enable support for software perf events Jamie Iles
2009-12-14 14:04         ` [PATCH 5/5] arm/perfevents: implement perf event support for ARMv6 Jamie Iles
2009-12-14 16:12           ` Jean Pihet
2009-12-14 16:33             ` Jamie Iles
2009-12-14 16:57               ` Jean Pihet
2009-12-14 17:09             ` Will Deacon
2009-12-14 16:13           ` Will Deacon
2009-12-14 16:20             ` Jamie Iles
2009-12-14 16:24               ` Will Deacon
2009-12-14 17:38       ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Nicolas Pitre
2009-12-14 19:36         ` Will Deacon
     [not found]         ` <001301ca7cf4$c04481a0$40cd84e0$%deacon@arm.com>
2009-12-14 19:52           ` Nicolas Pitre
2009-12-15 10:24             ` Catalin Marinas [this message]
2009-12-14 16:01     ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jean Pihet
2009-12-14 16:04     ` Will Deacon
2009-12-14 16:10       ` Jamie Iles
2009-12-14 14:39   ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Will Deacon
2009-12-14 15:03     ` Jamie Iles
2009-12-14 16:01   ` Jean Pihet
  -- strict thread matches above, loose matches on Subject: below --
2009-12-15 11:15 ARMv6 performance counters v3 Jamie Iles
2009-12-15 11:15 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2009-12-15 11:15   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2009-12-15 11:15     ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2010-01-04 10:48 ARM perf events support v4 Jamie Iles
2010-01-04 10:48 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-04 10:48   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2010-01-04 10:48     ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles
2010-01-05 18:57       ` Jamie Lokier
2010-01-05 19:08         ` Jamie Iles
2010-01-14 12:14 ARM perf events support v5 Jamie Iles
2010-01-14 12:14 ` [PATCH 1/5] arm: provide a mechanism to reserve performance counters Jamie Iles
2010-01-14 12:14   ` [PATCH 2/5] arm/oprofile: reserve the PMU when starting Jamie Iles
2010-01-14 12:14     ` [PATCH 3/5] arm: use the spinlocked, generic atomic64 support Jamie Iles

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1260872688.1569.19.camel@pc1117.cambridge.arm.com \
    --to=catalin.marinas@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).