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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4398148f4fcsm72046035e9.7.2025.02.18.09.09.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Feb 2025 09:09:10 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 5/8] pinctrl: sunxi: allow reading mux values from DT Date: Tue, 18 Feb 2025 18:09:09 +0100 Message-ID: <12609538.O9o76ZdvQC@jernej-laptop> In-Reply-To: <20250214003734.14944-6-andre.przywara@arm.com> References: <20250214003734.14944-1-andre.przywara@arm.com> <20250214003734.14944-6-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250218_090913_316507_D3735CEE X-CRM114-Status: GOOD ( 21.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Dne petek, 14. februar 2025 ob 01:37:31 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > So far every Allwinner SoC needs a large table in the kernel code, to > describe the mapping between the pinctrl function names ("uart") and > the actual pincontroller mux value to be written into the registers. > This adds a lot of data into a single image kernel, and also looks > somewhat weird, as the DT can easily store the mux value. >=20 > Add some code that allows to avoid that table: the struct that describes > the existing pins will be build at *runtime*, based on very basic > information provided by the respective SoC's pinctrl driver. This > consists of the number of pins per bank, plus information which bank > provides IRQ support, along with the mux value to use for that. > The code will then iterate over all children of the pincontroller DT > node (which describe each pin group), and populate that struct with the > mapping between function names and mux values. The only thing that needs > adding in the DT is a property with that value, per pin group. >=20 > When this table is built, it will be handed over to the existing sunxi > pinctrl driver, which cannot tell a difference between a hardcoded > struct and this new one built at runtime. It will take care of > registering the pinctrl device with the pinctrl subsystem. >=20 > All a new SoC driver would need to do is to provide two arrays, and then > call the sunxi_pinctrl_dt_table_init() function. >=20 > Signed-off-by: Andre Przywara I went through the code and it makes sense. I wonder if we really need to build whole table instead of having on demand lookups into DT. However, for now, this will do. So: Reviewed-by: Jernej Skrabec Thanks! Best regards, Jernej