From mboxrd@z Thu Jan  1 00:00:00 1970
From: catalin.marinas@arm.com (Catalin Marinas)
Date: Thu, 07 Jan 2010 09:59:08 +0000
Subject: [PATCH] ARM: Add SWP/SWPB emulation for ARMv7 processors (v3)
In-Reply-To: <20100106181705.GD11773@shareable.org>
References: <20100106181705.GD11773@shareable.org>
Message-ID: <1262858349.2695.7.camel@pc1117.cambridge.arm.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

On Wed, 2010-01-06 at 18:17 +0000, Jamie Lokier wrote:
> Catalin Marinas wrote:
> > > Is there any reason why this wasn't always like that?
> >
> > On ARMv6 onwards (where this user RO, kernel RO is supported) we cannot
> > easily differentiate between the vectors page and a normal kernel page
> > unless we use another L_PTE_ bit. We need the vectors page to be
> > writable if there is no TLS register in hardware (I guess we could use
> > domain switching to override this though). But on ARMv7 we always have a
> > TLS register, so no need to write to the vectors page.
> 
> Could you map the TLS page writable (kernel access only) at another
> address at the same time, carefully choosing an aliasing address so
> that no cache flush is needed after writing?

It could be but I'm not sure it's worth. Leif's patch is intended for
ARMv7 where we always have a hardware TLS register. The FIQ handler
installation could probably be done by first calling set_fs(KERNEL_DS).

-- 
Catalin