From mboxrd@z Thu Jan 1 00:00:00 1970 From: adharmap@codeaurora.org (adharmap at codeaurora.org) Date: Wed, 27 Jan 2010 11:32:27 -0800 Subject: [PATCH 3/5] gic: Add set_type callback In-Reply-To: <1264620749-24527-1-git-send-email-adharmap@codeaurora.org> References: <1264620749-24527-1-git-send-email-adharmap@codeaurora.org> Message-ID: <1264620749-24527-4-git-send-email-adharmap@codeaurora.org> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Abhijeet Dharmapurikar Add gic_set_type callback to set an irq as level or edge triggered type Signed-off-by: Abhijeet Dharmapurikar --- arch/arm/common/gic.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 43 insertions(+), 0 deletions(-) diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 00172c4..709cf53 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c @@ -165,6 +165,48 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) chip->unmask(irq); } +static int gic_set_type(unsigned int irq, unsigned int flow_type) +{ + unsigned int register_index; + unsigned int bit_index; + unsigned int reg_value; + + if (irq > 1020) + return -1; + + /* + * Two bits each, calc the register and bit, 16 per 32 bit register + * accessible long word only + * But the field is NxN 1xN and rising/falling + */ + register_index = (irq/16)<<2; + bit_index = (irq & 0xF)<<1; + + spin_lock(&irq_controller_lock); + reg_value = readl(gic_dist_base(irq) + GIC_DIST_CONFIG + + register_index); + /* + * keep the nxn and 1xn , mask the edge level + * Edge is 1, level 0 + */ + reg_value = (reg_value & ~(2<