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* LPC32XX arch updates from developer comments
       [not found] <LPC32XX architecture files (updated)>
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata wellsk40 at gmail.com
                   ` (15 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel


This patch series fixes (mostly) non-technical issues with sparse,
type checking, and naming conventions. This patchset builds on
the previously send patchset.

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata
       [not found] <LPC32XX architecture files (updated)>
  2010-02-02 23:59 ` LPC32XX arch updates from developer comments wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-03 10:08   ` Russell King - ARM Linux
  2010-02-02 23:59 ` [PATCH 02/16] ARM: LPC32XX: removed extra include statement wellsk40 at gmail.com
                   ` (14 subsequent siblings)
  16 siblings, 1 reply; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

struct clk looksup[] should not be tagged with the __initdata
attribute so system functions after bootup can use the clkdev
support.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/clock.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 615c091..d404b67 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -959,7 +959,7 @@ EXPORT_SYMBOL(clk_get_parent);
 		.clk = &(c), \
 	},
 
-static struct clk_lookup lookups[] __initdata = {
+static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
 	_REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
 	_REGISTER_CLOCK(NULL, "osc_main", osc_main)
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 02/16] ARM: LPC32XX: removed extra include statement
       [not found] <LPC32XX architecture files (updated)>
  2010-02-02 23:59 ` LPC32XX arch updates from developer comments wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-03 10:08   ` Russell King - ARM Linux
  2010-02-02 23:59 ` [PATCH 03/16] ARM: LPC32XX: Added LPC32XX identifier to high level macro names wellsk40 at gmail.com
                   ` (13 subsequent siblings)
  16 siblings, 1 reply; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

The include of <mach/irqs.h> isn't needed in the entry-macro.S
file.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/include/mach/entry-macro.S |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index c0313ae..ba1bdd6 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -22,7 +22,6 @@
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
-#include <mach/irqs.h>
 
 	.macro	disable_fiq
 	.endm
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 03/16] ARM: LPC32XX: Added LPC32XX identifier to high level macro names
       [not found] <LPC32XX architecture files (updated)>
                   ` (2 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 02/16] ARM: LPC32XX: removed extra include statement wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 04/16] ARM: LPC32XX: Added LXP32XX identified to CLKPWR register field macros wellsk40 at gmail.com
                   ` (12 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Arch specific macro names used for system base addresses, clock
rates, and sizing have been updated to include the LPC32XX
identifier. This may help prevent potential conflicts with Linux
identifiers in the future.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/clock.c                    |   18 ++--
 arch/arm/mach-lpc32xx/common.c                   |   34 +++---
 arch/arm/mach-lpc32xx/common.h                   |    2 +-
 arch/arm/mach-lpc32xx/gpiolib.c                  |    2 +-
 arch/arm/mach-lpc32xx/include/mach/debug-macro.S |    8 +-
 arch/arm/mach-lpc32xx/include/mach/entry-macro.S |    6 +-
 arch/arm/mach-lpc32xx/include/mach/platform.h    |  140 +++++++++++-----------
 arch/arm/mach-lpc32xx/include/mach/uncompress.h  |   14 +-
 arch/arm/mach-lpc32xx/irq.c                      |   31 +++---
 arch/arm/mach-lpc32xx/phy3250.c                  |   22 ++--
 arch/arm/mach-lpc32xx/pm.c                       |    6 +-
 arch/arm/mach-lpc32xx/serial.c                   |   34 +++---
 arch/arm/mach-lpc32xx/suspend.S                  |    4 +-
 arch/arm/mach-lpc32xx/timer.c                    |    8 +-
 14 files changed, 163 insertions(+), 166 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index d404b67..eb522a5 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -110,11 +110,11 @@ static struct clk clk_usbpll;
  */
 const u32 pll_postdivs[4] = {1, 2, 4, 8};
 
-#define USB_OTG_IOBASE io_p2v(USB_BASE)
+#define USB_OTG_IOBASE io_p2v(LPC32XX_USB_BASE)
 
 /* 32KHz clock has a fixed rate and is not stoppable */
 static struct clk osc_32KHz = {
-	.rate		= CLOCK_OSC_FREQ,
+	.rate		= LPC32XX_CLOCK_OSC_FREQ,
 };
 
 static int local_pll397_enable(struct clk *clk, int enable)
@@ -132,7 +132,7 @@ static int local_pll397_enable(struct clk *clk, int enable)
 		/* Enable PLL397 */
 		reg &= ~CLKPWR_SYSCTRL_PLL397_DIS;
 		writel(reg, CLKPWR_PLL397_CTRL(CLKPWR_IOBASE));
-		clk->rate = CLOCK_OSC_FREQ * 397;
+		clk->rate = LPC32XX_CLOCK_OSC_FREQ * 397;
 
 		/* Wait for PLL397 lock */
 		while (((readl(CLKPWR_PLL397_CTRL(CLKPWR_IOBASE)) &
@@ -163,7 +163,7 @@ static int local_oscmain_enable(struct clk *clk, int enable)
 		/* Enable main oscillator */
 		reg &= ~CLKPWR_MOSC_DISABLE;
 		writel(reg, CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE));
-		clk->rate = MAIN_OSC_FREQ;
+		clk->rate = LPC32XX_MAIN_OSC_FREQ;
 
 		/* Wait for main oscillator to start */
 		while (((readl(CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE)) &
@@ -182,12 +182,12 @@ static int local_oscmain_enable(struct clk *clk, int enable)
 static struct clk osc_pll397 = {
 	.parent		= &osc_32KHz,
 	.enable		= &local_pll397_enable,
-	.rate		= CLOCK_OSC_FREQ * 397,
+	.rate		= LPC32XX_CLOCK_OSC_FREQ * 397,
 };
 
 static struct clk osc_main = {
 	.enable		= &local_oscmain_enable,
-	.rate		= MAIN_OSC_FREQ,
+	.rate		= LPC32XX_MAIN_OSC_FREQ,
 };
 
 static struct clk clk_sys;
@@ -757,7 +757,7 @@ static u32 clcd_get_rate(struct clk *clk)
 		return 0;
 
 	rate = clk_get_rate(clk->parent);
-	tmp = readl((io_p2v(LCD_BASE)) + CLCD_TIM2);
+	tmp = readl((io_p2v(LPC32XX_LCD_BASE)) + CLCD_TIM2);
 
 	/* Only supports internal clocking */
 	if (tmp & TIM2_BCD)
@@ -773,7 +773,7 @@ static int clcd_set_rate(struct clk *clk, u32 rate)
 {
 	u32 tmp, prate, div;
 
-	tmp = readl((io_p2v(LCD_BASE)) + CLCD_TIM2);
+	tmp = readl((io_p2v(LPC32XX_LCD_BASE)) + CLCD_TIM2);
 	prate = clk_get_rate(clk->parent);
 
 	if (rate == prate) {
@@ -791,7 +791,7 @@ static int clcd_set_rate(struct clk *clk, u32 rate)
 		tmp &= ~TIM2_BCD;
 		tmp |= (div & 0x1F);
 		tmp |= (((div >> 5) & 0x1F) << 27);
-		writel(tmp, ((io_p2v(LCD_BASE)) + CLCD_TIM2));
+		writel(tmp, ((io_p2v(LPC32XX_LCD_BASE)) + CLCD_TIM2));
 		local_onoff_enable(clk, 1);
 	}
 
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 77c98b4..f4e2113 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -36,15 +36,15 @@
 #include <mach/platform.h>
 #include "common.h"
 
-#define WDT_IOBASE io_p2v(WDTIM_BASE)
+#define WDT_IOBASE io_p2v(LPC32XX_WDTIM_BASE)
 
 /*
  * Watchdog timer
  */
 static struct resource watchdog_resources[] = {
 	[0] = {
-		.start = WDTIM_BASE,
-		.end = WDTIM_BASE + SZ_4K - 1,
+		.start = LPC32XX_WDTIM_BASE,
+		.end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
 		.flags = IORESOURCE_MEM,
 	},
 };
@@ -61,19 +61,19 @@ struct platform_device watchdog_device = {
  */
 static struct i2c_pnx_data i2c0_data = {
 	.name = I2C_CHIP_NAME "0",
-	.base = I2C1_BASE,
+	.base = LPC32XX_I2C1_BASE,
 	.irq = IRQ_I2C_1,
 };
 
 static struct i2c_pnx_data i2c1_data = {
 	.name = I2C_CHIP_NAME "1",
-	.base = I2C2_BASE,
+	.base = LPC32XX_I2C2_BASE,
 	.irq = IRQ_I2C_2,
 };
 
 static struct i2c_pnx_data i2c2_data = {
 	.name = "USB-I2C",
-	.base = OTG_I2C_BASE,
+	.base = LPC32XX_OTG_I2C_BASE,
 	.irq = IRQ_USB_I2C,
 };
 
@@ -238,26 +238,26 @@ u32 clk_get_pclk_div(void)
 
 static struct map_desc lpc32xx_io_desc[] __initdata = {
 	{
-		.virtual	= io_p2v(AHB0_START),
-		.pfn		= __phys_to_pfn(AHB0_START),
-		.length		= AHB0_SIZE,
+		.virtual	= io_p2v(LPC32XX_AHB0_START),
+		.pfn		= __phys_to_pfn(LPC32XX_AHB0_START),
+		.length		= LPC32XX_AHB0_SIZE,
 		.type		= MT_DEVICE
 	},
 	{
-		.virtual	= io_p2v(AHB1_START),
-		.pfn		= __phys_to_pfn(AHB1_START),
-		.length		= AHB1_SIZE,
+		.virtual	= io_p2v(LPC32XX_AHB1_START),
+		.pfn		= __phys_to_pfn(LPC32XX_AHB1_START),
+		.length		= LPC32XX_AHB1_SIZE,
 		.type		= MT_DEVICE
 	},
 	{
-		.virtual	= io_p2v(FABAPB_START),
-		.pfn		= __phys_to_pfn(FABAPB_START),
-		.length		= FABAPB_SIZE,
+		.virtual	= io_p2v(LPC32XX_FABAPB_START),
+		.pfn		= __phys_to_pfn(LPC32XX_FABAPB_START),
+		.length		= LPC32XX_FABAPB_SIZE,
 		.type		= MT_DEVICE
 	},
 	{
-		.virtual	= io_p2v(IRAM_BASE),
-		.pfn		= __phys_to_pfn(IRAM_BASE),
+		.virtual	= io_p2v(LPC32XX_IRAM_BASE),
+		.pfn		= __phys_to_pfn(LPC32XX_IRAM_BASE),
 		.length		= CONFIG_ARCH_LPC32XX_IRAM_SIZE,
 		.type		= MT_DEVICE
 	},
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index ab8d2b2..08fdfba 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -25,7 +25,7 @@
 
 #include <linux/platform_device.h>
 
-#define CLKPWR_IOBASE io_p2v(CLK_PM_BASE)
+#define CLKPWR_IOBASE io_p2v(LPC32XX_CLK_PM_BASE)
 
 /*
  * Arch specific platform device structures
diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
index 30cf252..803c48f 100644
--- a/arch/arm/mach-lpc32xx/gpiolib.c
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -29,7 +29,7 @@
 #include <mach/hardware.h>
 #include <mach/platform.h>
 
-#define GPIOBASE io_p2v(GPIO_BASE)
+#define GPIOBASE io_p2v(LPC32XX_GPIO_BASE)
 
 struct gpio_regs {
 	void __iomem *inp_state;
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 641daba..e03a1b7 100644
--- a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -29,19 +29,19 @@
 */
 
 #ifdef CONFIG_ARCH_LPC32XX_DEBUGO_U3
-#define UARTDB_BASE UART3_BASE
+#define UARTDB_BASE LPC32XX_UART3_BASE
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_DEBUGO_U4
-#define UARTDB_BASE UART4_BASE
+#define UARTDB_BASE LPC32XX_UART4_BASE
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_DEBUGO_U5
-#define UARTDB_BASE UART5_BASE
+#define UARTDB_BASE LPC32XX_UART5_BASE
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_DEBUGO_U6
-#define UARTDB_BASE UART6_BASE
+#define UARTDB_BASE LPC32XX_UART6_BASE
 #endif
 
 	.macro	addruart,rx
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index ba1bdd6..01331f1 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -38,7 +38,7 @@
  */
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	/* Get MIC status first */
-	ldr	\base, =IO_ADDRESS(MIC_BASE)
+	ldr	\base, =IO_ADDRESS(LPC32XX_MIC_BASE)
 	ldr	\irqstat, [\base, #INTC_STAT]
 	and	\irqstat, \irqstat, #0xFFFFFFFC
 	mov	\tmp, #0
@@ -48,7 +48,7 @@
 	bne	1000f
 
 	/* SIC1 interrupts start at offset 32 */
-	ldr	\base, =IO_ADDRESS(SIC1_BASE)
+	ldr	\base, =IO_ADDRESS(LPC32XX_SIC1_BASE)
 	ldr	\irqstat, [\base, #INTC_STAT]
 	mov	\tmp, #32
 
@@ -57,7 +57,7 @@
 	bne	1000f
 
 	/* SIC2 interrupts start at offset 64 */
-	ldr	\base, =IO_ADDRESS(SIC2_BASE)
+	ldr	\base, =IO_ADDRESS(LPC32XX_SIC2_BASE)
 	ldr	\irqstat, [\base, #INTC_STAT]
 	mov	\tmp, #64
 
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 48305a5..42fe08d 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -29,110 +29,108 @@
 /*
  * AHB 0 physical base addresses
  */
-#define SLC_BASE			0x20020000
-#define SSP0_BASE			0x20084000
-#define SPI1_BASE			0x20088000
-#define SSP1_BASE			0x2008C000
-#define SPI2_BASE			0x20090000
-#define I2S0_BASE			0x20094000
-#define SD_BASE				0x20098000
-#define I2S1_BASE			0x2009C000
-#define MLC_BASE			0x200A8000
-#define AHB0_START			SLC_BASE
-#define AHB0_SIZE			((MLC_BASE - SLC_BASE) + SZ_4K)
+#define LPC32XX_SLC_BASE			0x20020000
+#define LPC32XX_SSP0_BASE			0x20084000
+#define LPC32XX_SPI1_BASE			0x20088000
+#define LPC32XX_SSP1_BASE			0x2008C000
+#define LPC32XX_SPI2_BASE			0x20090000
+#define LPC32XX_I2S0_BASE			0x20094000
+#define LPC32XX_SD_BASE				0x20098000
+#define LPC32XX_I2S1_BASE			0x2009C000
+#define LPC32XX_MLC_BASE			0x200A8000
+#define LPC32XX_AHB0_START			LPC32XX_SLC_BASE
+#define LPC32XX_AHB0_SIZE			((LPC32XX_MLC_BASE -\
+						LPC32XX_SLC_BASE) + SZ_4K)
 
 /*
  * AHB 1 physical base addresses
  */
-#define DMA_BASE			0x31000000
-#define USB_BASE			0x31020000
-#define USBH_BASE			0x31020000
-#define USB_OTG_BASE			0x31020000
-#define OTG_I2C_BASE			0x31020300
-#define LCD_BASE			0x31040000
-#define ETHERNET_BASE			0x31060000
-#define EMC_BASE			0x31080000
-#define ETB_CFG_BASE			0x310C0000
-#define ETB_DATA_BASE			0x310E0000
-#define AHB1_START			DMA_BASE
-#define AHB1_SIZE			((EMC_BASE - DMA_BASE) + SZ_4K)
+#define LPC32XX_DMA_BASE			0x31000000
+#define LPC32XX_USB_BASE			0x31020000
+#define LPC32XX_USBH_BASE			0x31020000
+#define LPC32XX_USB_OTG_BASE			0x31020000
+#define LPC32XX_OTG_I2C_BASE			0x31020300
+#define LPC32XX_LCD_BASE			0x31040000
+#define LPC32XX_ETHERNET_BASE			0x31060000
+#define LPC32XX_EMC_BASE			0x31080000
+#define LPC32XX_ETB_CFG_BASE			0x310C0000
+#define LPC32XX_ETB_DATA_BASE			0x310E0000
+#define LPC32XX_AHB1_START			LPC32XX_DMA_BASE
+#define LPC32XX_AHB1_SIZE			((LPC32XX_EMC_BASE -\
+						LPC32XX_DMA_BASE) + SZ_4K)
 
 /*
  * FAB physical base addresses
  */
-#define CLK_PM_BASE			0x40004000
-#define MIC_BASE			0x40008000
-#define SIC1_BASE			0x4000C000
-#define SIC2_BASE			0x40010000
-#define HS_UART1_BASE			0x40014000
-#define HS_UART2_BASE			0x40018000
-#define HS_UART7_BASE			0x4001C000
-#define RTC_BASE			0x40024000
-#define RTC_RAM_BASE			0x40024080
-#define GPIO_BASE			0x40028000
-#define PWM3_BASE			0x4002C000
-#define PWM4_BASE			0x40030000
-#define MSTIM_BASE			0x40034000
-#define HSTIM_BASE			0x40038000
-#define WDTIM_BASE			0x4003C000
-#define DEBUG_CTRL_BASE			0x40040000
-#define TIMER0_BASE			0x40044000
-#define ADC_BASE			0x40048000
-#define TIMER1_BASE			0x4004C000
-#define KSCAN_BASE			0x40050000
-#define UART_CTRL_BASE			0x40054000
-#define TIMER2_BASE			0x40058000
-#define PWM1_BASE			0x4005C000
-#define PWM2_BASE			0x4005C004
-#define TIMER3_BASE			0x40060000
+#define LPC32XX_CLK_PM_BASE			0x40004000
+#define LPC32XX_MIC_BASE			0x40008000
+#define LPC32XX_SIC1_BASE			0x4000C000
+#define LPC32XX_SIC2_BASE			0x40010000
+#define LPC32XX_HS_UART1_BASE			0x40014000
+#define LPC32XX_HS_UART2_BASE			0x40018000
+#define LPC32XX_HS_UART7_BASE			0x4001C000
+#define LPC32XX_RTC_BASE			0x40024000
+#define LPC32XX_RTC_RAM_BASE			0x40024080
+#define LPC32XX_GPIO_BASE			0x40028000
+#define LPC32XX_PWM3_BASE			0x4002C000
+#define LPC32XX_PWM4_BASE			0x40030000
+#define LPC32XX_MSTIM_BASE			0x40034000
+#define LPC32XX_HSTIM_BASE			0x40038000
+#define LPC32XX_WDTIM_BASE			0x4003C000
+#define LPC32XX_DEBUG_CTRL_BASE			0x40040000
+#define LPC32XX_TIMER0_BASE			0x40044000
+#define LPC32XX_ADC_BASE			0x40048000
+#define LPC32XX_TIMER1_BASE			0x4004C000
+#define LPC32XX_KSCAN_BASE			0x40050000
+#define LPC32XX_UART_CTRL_BASE			0x40054000
+#define LPC32XX_TIMER2_BASE			0x40058000
+#define LPC32XX_PWM1_BASE			0x4005C000
+#define LPC32XX_PWM2_BASE			0x4005C004
+#define LPC32XX_TIMER3_BASE			0x40060000
 
 /*
  * APB physical base addresses
  */
 
-#define UART3_BASE			0x40080000
-#define UART4_BASE			0x40088000
-#define UART5_BASE			0x40090000
-#define UART6_BASE			0x40098000
-#define I2C1_BASE			0x400A0000
-#define I2C2_BASE			0x400A8000
+#define LPC32XX_UART3_BASE			0x40080000
+#define LPC32XX_UART4_BASE			0x40088000
+#define LPC32XX_UART5_BASE			0x40090000
+#define LPC32XX_UART6_BASE			0x40098000
+#define LPC32XX_I2C1_BASE			0x400A0000
+#define LPC32XX_I2C2_BASE			0x400A8000
 
 /*
  * FAB and APB base and sizing
  */
-#define FABAPB_START			CLK_PM_BASE
-#define FABAPB_SIZE			((I2C2_BASE - CLK_PM_BASE) + SZ_4K)
+#define LPC32XX_FABAPB_START			LPC32XX_CLK_PM_BASE
+#define LPC32XX_FABAPB_SIZE			((LPC32XX_I2C2_BASE -\
+						LPC32XX_CLK_PM_BASE) + SZ_4K)
 
 /*
  * Internal memory Bases
  */
-#define IRAM_BASE			0x08000000
-#define IROM_BASE			0x0C000000
+#define LPC32XX_IRAM_BASE			0x08000000
+#define LPC32XX_IROM_BASE			0x0C000000
 
 /*
  * External Static Memory Bank Address Space Bases
  */
-#define EMC_CS0_BASE			0xE0000000
-#define EMC_CS1_BASE			0xE1000000
-#define EMC_CS2_BASE			0xE2000000
-#define EMC_CS3_BASE			0xE3000000
+#define LPC32XX_EMC_CS0_BASE			0xE0000000
+#define LPC32XX_EMC_CS1_BASE			0xE1000000
+#define LPC32XX_EMC_CS2_BASE			0xE2000000
+#define LPC32XX_EMC_CS3_BASE			0xE3000000
 
 /*
  * External SDRAM Memory Bank Address Space Bases
  */
-#define EMC_DYCS0_BASE			0x80000000
-#define EMC_DYCS1_BASE			0xA0000000
+#define LPC32XX_EMC_DYCS0_BASE			0x80000000
+#define LPC32XX_EMC_DYCS1_BASE			0xA0000000
 
 /*
  * Clock and crystal information
  */
-#define MAIN_OSC_FREQ			13000000
-#define CLOCK_OSC_FREQ			32768
-
-/*
- * IRAM size
-*/
-#define LPC32XX_IRAM_SIZE 		CONFIG_ARCH_LPC32XX_IRAM_SIZE
+#define LPC32XX_MAIN_OSC_FREQ			13000000
+#define LPC32XX_CLOCK_OSC_FREQ			32768
 
 /*
  * Clock and Power control register offsets
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
index a00ecc5..94c29a8 100644
--- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -34,15 +34,15 @@
  * High speed UART uncompress output support
 */
 #ifdef CONFIG_ARCH_LPC32XX_UNCOMP_HSU1
-#define HS_UARTX_BASE	(HS_UART1_BASE)
+#define HS_UARTX_BASE	(LPC32XX_HS_UART1_BASE)
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_UNCOMP_HSU2
-#define HS_UARTX_BASE	(HS_UART2_BASE)
+#define HS_UARTX_BASE	(LPC32XX_HS_UART2_BASE)
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_UNCOMP_HSU7
-#define HS_UARTX_BASE	(HS_UART7_BASE)
+#define HS_UARTX_BASE	(LPC32XX_HS_UART7_BASE)
 #endif
 
 #define HSUART_FIFO	(HS_UARTX_BASE + 0x00)
@@ -72,19 +72,19 @@ static inline void flush(void)
 #define UART_STATUS_TX_MT	(1 << 6)
 
 #ifdef CONFIG_ARCH_LPC32XX_UNCOMP_U3
-#define UARTX_BASE	(UART3_BASE)
+#define UARTX_BASE	(LPC32XX_UART3_BASE)
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_UNCOMP_U4
-#define UARTX_BASE	(UART4_BASE)
+#define UARTX_BASE	(LPC32XX_UART4_BASE)
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_UNCOMP_U5
-#define UARTX_BASE	(UART5_BASE)
+#define UARTX_BASE	(LPC32XX_UART5_BASE)
 #endif
 
 #ifdef CONFIG_ARCH_LPC32XX_UNCOMP_U6
-#define UARTX_BASE	(UART6_BASE)
+#define UARTX_BASE	(LPC32XX_UART6_BASE)
 #endif
 
 #define UART_DATA	(UARTX_BASE + 0x00)
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 8a1b57d..3e45d32 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -51,13 +51,13 @@ static void get_controller(unsigned int irq, unsigned int *base,
 	unsigned int *irqbit)
 {
 	if (irq < 32) {
-		*base = io_p2v(MIC_BASE);
+		*base = io_p2v(LPC32XX_MIC_BASE);
 		*irqbit = 1 << irq;
 	} else if (irq < 64) {
-		*base = io_p2v(SIC1_BASE);
+		*base = io_p2v(LPC32XX_SIC1_BASE);
 		*irqbit = 1 << (irq - 32);
 	} else {
-		*base = io_p2v(SIC2_BASE);
+		*base = io_p2v(LPC32XX_SIC2_BASE);
 		*irqbit = 1 << (irq - 64);
 	}
 }
@@ -197,19 +197,19 @@ void __init lpc32xx_init_irq(void)
 	unsigned int i, vloc;
 
 	/* Setup MIC */
-	vloc = io_p2v(MIC_BASE);
+	vloc = io_p2v(LPC32XX_MIC_BASE);
 	writel(0, (vloc + INTC_MASK));
 	writel(MIC_APR_DEFAULT, (vloc + INTC_POLAR));
 	writel(MIC_ATR_DEFAULT, (vloc + INTC_ACT_TYPE));
 
 	/* Setup SIC1 */
-	vloc = io_p2v(SIC1_BASE);
+	vloc = io_p2v(LPC32XX_SIC1_BASE);
 	writel(0, (vloc + INTC_MASK));
 	writel(SIC1_APR_DEFAULT, (vloc + INTC_POLAR));
 	writel(SIC1_ATR_DEFAULT, (vloc + INTC_ACT_TYPE));
 
 	/* Setup SIC2 */
-	vloc = io_p2v(SIC2_BASE);
+	vloc = io_p2v(LPC32XX_SIC2_BASE);
 	writel(0, (vloc + INTC_MASK));
 	writel(SIC2_APR_DEFAULT, (vloc + INTC_POLAR));
 	writel(SIC2_ATR_DEFAULT, (vloc + INTC_ACT_TYPE));
@@ -221,17 +221,16 @@ void __init lpc32xx_init_irq(void)
 	}
 
 	/* Set default mappings */
-	lpc32xx_set_default_mappings(io_p2v(MIC_BASE), MIC_APR_DEFAULT,
+	lpc32xx_set_default_mappings(io_p2v(LPC32XX_MIC_BASE), MIC_APR_DEFAULT,
 		MIC_ATR_DEFAULT, 0);
-	lpc32xx_set_default_mappings(io_p2v(SIC1_BASE), SIC1_APR_DEFAULT,
-		SIC1_ATR_DEFAULT, 32);
-	lpc32xx_set_default_mappings(io_p2v(SIC2_BASE), SIC2_APR_DEFAULT,
-		SIC2_ATR_DEFAULT, 64);
+	lpc32xx_set_default_mappings(io_p2v(LPC32XX_SIC1_BASE),
+		SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
+	lpc32xx_set_default_mappings(io_p2v(LPC32XX_SIC2_BASE),
+		SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
 
 	/* mask all interrupts except SUBIRQA and SUBFIQ */
-	writel((1 << IRQ_SUB1IRQ) | (1 << IRQ_SUB2IRQ) |
-			(1 << IRQ_SUB1FIQ) | (1 << IRQ_SUB2FIQ),
-		(io_p2v(MIC_BASE) + INTC_MASK));
-	writel(0, (io_p2v(SIC1_BASE) + INTC_MASK));
-	writel(0, (io_p2v(SIC2_BASE) + INTC_MASK));
+	writel((1 << IRQ_SUB1IRQ) | (1 << IRQ_SUB2IRQ) | (1 << IRQ_SUB1FIQ) |
+		(1 << IRQ_SUB2FIQ), (io_p2v(LPC32XX_MIC_BASE) + INTC_MASK));
+	writel(0, (io_p2v(LPC32XX_SIC1_BASE) + INTC_MASK));
+	writel(0, (io_p2v(LPC32XX_SIC2_BASE) + INTC_MASK));
 }
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index aa29aa6..4ee9714 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -87,9 +87,9 @@ static int lpc32xx_clcd_setup(struct clcd_fb *fb)
 
 	fb->fb.screen_base = (void *) NULL;
 #ifdef CONFIG_MACH_LPC32XX_IRAM_FOR_CLCD
-	if (PANEL_SIZE <= LPC32XX_IRAM_SIZE) {
-		fb->fb.screen_base = (void *) io_p2v(IRAM_BASE);
-		fb->fb.fix.smem_start = (dma_addr_t) IRAM_BASE;
+	if (PANEL_SIZE <= CONFIG_ARCH_LPC32XX_IRAM_SIZE) {
+		fb->fb.screen_base = (void *) io_p2v(LPC32XX_IRAM_BASE);
+		fb->fb.fix.smem_start = (dma_addr_t) LPC32XX_IRAM_BASE;
 	}
 #endif
 
@@ -118,7 +118,7 @@ static int lpc32xx_clcd_setup(struct clcd_fb *fb)
 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 {
 #ifdef CONFIG_MACH_LPC32XX_IRAM_FOR_CLCD
-	if (PANEL_SIZE <= LPC32XX_IRAM_SIZE) {
+	if (PANEL_SIZE <= CONFIG_ARCH_LPC32XX_IRAM_SIZE) {
 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 		if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 			(vma->vm_end - vma->vm_start), vma->vm_page_prot)) {
@@ -138,7 +138,7 @@ static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
 {
 #ifdef CONFIG_MACH_LPC32XX_IRAM_FOR_CLCD
-	if (PANEL_SIZE > LPC32XX_IRAM_SIZE)
+	if (PANEL_SIZE > CONFIG_ARCH_LPC32XX_IRAM_SIZE)
 		dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 			fb->fb.screen_base, fb->fb.fix.smem_start);
 
@@ -186,8 +186,8 @@ static struct amba_device clcd_device = {
 		.platform_data		= &lpc32xx_clcd_data,
 	},
 	.res				= {
-		.start			= LCD_BASE,
-		.end			= (LCD_BASE + SZ_4K - 1),
+		.start			= LPC32XX_LCD_BASE,
+		.end			= (LPC32XX_LCD_BASE + SZ_4K - 1),
 		.flags			= IORESOURCE_MEM,
 	},
 	.dma_mask			= ~0,
@@ -234,8 +234,8 @@ static struct amba_device ssp0_device = {
 		.platform_data		= &lpc32xx_ssp0_data,
 	},
 	.res				= {
-		.start			= SSP0_BASE,
-		.end			= (SSP0_BASE + SZ_4K - 1),
+		.start			= LPC32XX_SSP0_BASE,
+		.end			= (LPC32XX_SSP0_BASE + SZ_4K - 1),
 		.flags			= IORESOURCE_MEM,
 	},
 	.dma_mask			= ~0,
@@ -414,8 +414,8 @@ arch_initcall(lpc32xx_display_uid);
 
 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
 	/* Maintainer: Kevin Wells, NXP Semiconductors */
-	.phys_io	= UART5_BASE,
-	.io_pg_offst	= ((io_p2v(UART5_BASE))>>18) & 0xfffc,
+	.phys_io	= LPC32XX_UART5_BASE,
+	.io_pg_offst	= ((io_p2v(LPC32XX_UART5_BASE))>>18) & 0xfffc,
 	.boot_params	= 0x80000100,
 	.map_io		= lpc32xx_map_io,
 	.init_irq	= lpc32xx_init_irq,
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index 8535e99..5f0a805 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -90,7 +90,7 @@
 #include "clock.h"
 #include "pm.h"
 
-#define TEMP_IRAM_AREA  io_p2v(IRAM_BASE)
+#define TEMP_IRAM_AREA  io_p2v(LPC32XX_IRAM_BASE)
 
 static void *iram_swap_area;
 
@@ -151,8 +151,8 @@ static int __init lpc32xx_pm_init(void)
 {
 	/* Setup SDRAM self-refresh clock to automatically
 	   disable on start of self-refresh */
-	writel(readl(io_p2v(EMC_BASE) + EMC_DYN_MEM_CTRL_OFS) | EMC_SRMMC,
-		io_p2v(EMC_BASE) + EMC_DYN_MEM_CTRL_OFS);
+	writel(readl(io_p2v(LPC32XX_EMC_BASE) + EMC_DYN_MEM_CTRL_OFS) |
+		EMC_SRMMC, io_p2v(LPC32XX_EMC_BASE) + EMC_DYN_MEM_CTRL_OFS);
 
 	/* Allocate some space for temporary IRAM storage */
 	iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_ATOMIC);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 1c15121..e4479ba 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -38,10 +38,10 @@
 static struct plat_serial8250_port serial_std_platform_data[] = {
 #ifdef CONFIG_ARCH_LPC32XX_UART5_ENABLE
 	{
-		.membase        = (void *) io_p2v(UART5_BASE),
-		.mapbase        = UART5_BASE,
+		.membase        = (void *) io_p2v(LPC32XX_UART5_BASE),
+		.mapbase        = LPC32XX_UART5_BASE,
 		.irq		= IRQ_UART_IIR5,
-		.uartclk	= MAIN_OSC_FREQ,
+		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
@@ -50,10 +50,10 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART3_ENABLE
 	{
-		.membase	= (void *) io_p2v(UART3_BASE),
-		.mapbase        = UART3_BASE,
+		.membase	= (void *) io_p2v(LPC32XX_UART3_BASE),
+		.mapbase        = LPC32XX_UART3_BASE,
 		.irq		= IRQ_UART_IIR3,
-		.uartclk	= MAIN_OSC_FREQ,
+		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
@@ -62,10 +62,10 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART4_ENABLE
 	{
-		.membase	= (void *) io_p2v(UART4_BASE),
-		.mapbase        = UART4_BASE,
+		.membase	= (void *) io_p2v(LPC32XX_UART4_BASE),
+		.mapbase        = LPC32XX_UART4_BASE,
 		.irq		= IRQ_UART_IIR4,
-		.uartclk	= MAIN_OSC_FREQ,
+		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
@@ -74,10 +74,10 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART6_ENABLE
 	{
-		.membase	= (void *) io_p2v(UART6_BASE),
-		.mapbase        = UART6_BASE,
+		.membase	= (void *) io_p2v(LPC32XX_UART6_BASE),
+		.mapbase        = LPC32XX_UART6_BASE,
 		.irq		= IRQ_UART_IIR6,
-		.uartclk	= MAIN_OSC_FREQ,
+		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
 		.flags		= UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
@@ -169,7 +169,7 @@ void __init lpc32xx_serial_init(void)
 	}
 
 	/* This needs to be done after all UART clocks are setup */
-	writel(clkmodes, UARTCTL_CLKMODE(io_p2v(UART_CTRL_BASE)));
+	writel(clkmodes, UARTCTL_CLKMODE(io_p2v(LPC32XX_UART_CTRL_BASE)));
 	for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
 		/* Force a flush of the RX FIFOs to work around a HW bug */
 		puart = serial_std_platform_data[i].membase;
@@ -182,18 +182,18 @@ void __init lpc32xx_serial_init(void)
 	}
 
 	/* IrDA pulsing support on UART6. This only enables the IrDA mux */
-	tmp = readl(UARTCTL_CTRL(io_p2v(UART_CTRL_BASE)));
+	tmp = readl(UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
 #ifdef CONFIG_ARCH_LPC32XX_UART6_IRDAMODE
 	tmp &= ~UART_UART6_IRDAMOD_BYPASS;
 #else
 	tmp |= UART_UART6_IRDAMOD_BYPASS;
 #endif
-	writel(tmp, UARTCTL_CTRL(io_p2v(UART_CTRL_BASE)));
+	writel(tmp, UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
 
 	/* Disable UART5->USB transparent mode or USB won't work */
-	tmp = readl(UARTCTL_CTRL(io_p2v(UART_CTRL_BASE)));
+	tmp = readl(UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
 	tmp &= ~UART_U5_ROUTE_TO_USB;
-	writel(tmp, UARTCTL_CTRL(io_p2v(UART_CTRL_BASE)));
+	writel(tmp, UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
 
 	platform_add_devices(lpc32xx_serial_devs,
 		ARRAY_SIZE(lpc32xx_serial_devs));
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
index 075708b..aa06be8 100644
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -143,8 +143,8 @@ ENTRY(lpc32xx_sys_suspend)
 	ldmfd	r0!, {r1 - r7, sp, pc}
 
 reg_bases:
-	.long	IO_ADDRESS(CLK_PM_BASE)
-	.long	IO_ADDRESS(EMC_BASE)
+	.long	IO_ADDRESS(LPC32XX_CLK_PM_BASE)
+	.long	IO_ADDRESS(LPC32XX_EMC_BASE)
 
 tmp_stack:
 	.long	0, 0, 0, 0, 0, 0, 0, 0, 0
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 9c06346..c5fa62d 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -35,8 +35,8 @@
 #include <mach/platform.h>
 #include "common.h"
 
-#define TIMER0_IOBASE io_p2v(TIMER0_BASE)
-#define TIMER1_IOBASE io_p2v(TIMER1_BASE)
+#define TIMER0_IOBASE io_p2v(LPC32XX_TIMER0_BASE)
+#define TIMER1_IOBASE io_p2v(LPC32XX_TIMER1_BASE)
 
 static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
 {
@@ -141,9 +141,9 @@ static void __init lpc32xx_timer_init(void)
 	   it to compute the PLL frequency and the PCLK divider to get the base
 	   timer rates. This rate is needed to compute the tick rate. */
 	if (clk_is_sysclk_mainosc() != 0)
-		clkrate = MAIN_OSC_FREQ;
+		clkrate = LPC32XX_MAIN_OSC_FREQ;
 	else
-		clkrate = 397 * CLOCK_OSC_FREQ;
+		clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
 
 	/* Get ARM HCLKPLL register and convert it into a frequency*/
 	pllreg = readl(CLKPWR_HCLKPLL_CTRL(CLKPWR_IOBASE)) & 0x1FFFF;
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 04/16] ARM: LPC32XX: Added LXP32XX identified to CLKPWR register field macros
       [not found] <LPC32XX architecture files (updated)>
                   ` (3 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 03/16] ARM: LPC32XX: Added LPC32XX identifier to high level macro names wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 05/16] ARM: LPC32XX: Added LPC32XX identifier to INTC " wellsk40 at gmail.com
                   ` (11 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

The CLKPWR macros and associated code have been updated with the
LPC32XX identifier.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/clock.c                 |  222 +++++-----
 arch/arm/mach-lpc32xx/common.c                |   18 +-
 arch/arm/mach-lpc32xx/include/mach/platform.h |  612 ++++++++++++------------
 arch/arm/mach-lpc32xx/phy3250.c               |   51 ++-
 arch/arm/mach-lpc32xx/pm_events.c             |  340 +++++++-------
 arch/arm/mach-lpc32xx/serial.c                |   10 +-
 arch/arm/mach-lpc32xx/suspend.S               |   56 ++-
 arch/arm/mach-lpc32xx/timer.c                 |    8 +-
 8 files changed, 668 insertions(+), 649 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index eb522a5..befe6fa 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -122,26 +122,26 @@ static int local_pll397_enable(struct clk *clk, int enable)
 	u32 reg;
 	unsigned long timeout = 1 + msecs_to_jiffies(10);
 
-	reg = readl(CLKPWR_PLL397_CTRL(CLKPWR_IOBASE));
+	reg = readl(LPC32XX_CLKPWR_PLL397_CTRL(CLKPWR_IOBASE));
 
 	if (enable == 0) 	{
-		reg |= CLKPWR_SYSCTRL_PLL397_DIS;
-		writel(reg, CLKPWR_PLL397_CTRL(CLKPWR_IOBASE));
+		reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+		writel(reg, LPC32XX_CLKPWR_PLL397_CTRL(CLKPWR_IOBASE));
 		clk->rate = 0;
 	} else {
 		/* Enable PLL397 */
-		reg &= ~CLKPWR_SYSCTRL_PLL397_DIS;
-		writel(reg, CLKPWR_PLL397_CTRL(CLKPWR_IOBASE));
+		reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+		writel(reg, LPC32XX_CLKPWR_PLL397_CTRL(CLKPWR_IOBASE));
 		clk->rate = LPC32XX_CLOCK_OSC_FREQ * 397;
 
 		/* Wait for PLL397 lock */
-		while (((readl(CLKPWR_PLL397_CTRL(CLKPWR_IOBASE)) &
-			CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
+		while (((readl(LPC32XX_CLKPWR_PLL397_CTRL(CLKPWR_IOBASE)) &
+			LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
 			(timeout > jiffies))
 			cpu_relax();
 
-		if ((readl(CLKPWR_PLL397_CTRL(CLKPWR_IOBASE)) &
-			CLKPWR_SYSCTRL_PLL397_STS) == 0)
+		if ((readl(LPC32XX_CLKPWR_PLL397_CTRL(CLKPWR_IOBASE)) &
+			LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
 			return -ENODEV;
 	}
 
@@ -153,26 +153,26 @@ static int local_oscmain_enable(struct clk *clk, int enable)
 	u32 reg;
 	unsigned long timeout = 1 + msecs_to_jiffies(10);
 
-	reg = readl(CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE));
+	reg = readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE));
 
 	if (enable == 0) {
-		reg |= CLKPWR_MOSC_DISABLE;
-		writel(reg, CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE));
+		reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
+		writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE));
 		clk->rate = 0;
 	} else {
 		/* Enable main oscillator */
-		reg &= ~CLKPWR_MOSC_DISABLE;
-		writel(reg, CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE));
+		reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
+		writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE));
 		clk->rate = LPC32XX_MAIN_OSC_FREQ;
 
 		/* Wait for main oscillator to start */
-		while (((readl(CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE)) &
-			CLKPWR_MOSC_DISABLE) != 0) &&
+		while (((readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE)) &
+			LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
 			(timeout > jiffies))
 			cpu_relax();
 
-		if ((readl(CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE)) &
-			CLKPWR_MOSC_DISABLE) != 0)
+		if ((readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL(CLKPWR_IOBASE)) &
+			LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
 			return -ENODEV;
 	}
 
@@ -200,13 +200,13 @@ static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
 	u32 tv, tmp = 0;
 
 	if (PllSetup->analog_on != 0)
-		tmp |= CLKPWR_HCLKPLL_POWER_UP;
+		tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
 	if (PllSetup->cco_bypass_b15 != 0)
-		tmp |= CLKPWR_HCLKPLL_CCO_BYPASS;
+		tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
 	if (PllSetup->direct_output_b14 != 0)
-		tmp |= CLKPWR_HCLKPLL_POSTDIV_BYPASS;
+		tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
 	if (PllSetup->fdbk_div_ctrl_b13 != 0)
-		tmp |= CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
+		tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
 
 	switch (PllSetup->pll_p) {
 	case 1:
@@ -229,9 +229,9 @@ static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
 		return 0;
 	}
 
-	tmp |= CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
-	tmp |= CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
-	tmp |= CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
+	tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
+	tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
+	tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
 
 	return tmp;
 }
@@ -244,7 +244,7 @@ static void local_update_armpll_rate(void)
 	u32 clkin, pllreg;
 
 	clkin = clk_armpll.parent->rate;
-	pllreg = readl(CLKPWR_HCLKPLL_CTRL(CLKPWR_IOBASE)) & 0x1FFFF;
+	pllreg = readl(LPC32XX_CLKPWR_HCLKPLL_CTRL(CLKPWR_IOBASE)) & 0x1FFFF;
 
 	clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
 }
@@ -381,9 +381,9 @@ static void local_update_usbpll_rate(void)
 	u32 clkin, pllreg;
 
 	clkin = (u32) clk_get_rate(&clk_usbpll);
-	pllreg = readl(CLKPWR_USB_CTRL(CLKPWR_IOBASE)) & 0x1FFFF;
+	pllreg = readl(LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE)) & 0x1FFFF;
 
-	if ((pllreg & CLKPWR_USBCTRL_PLL_PWRUP) == 0)
+	if ((pllreg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) == 0)
 		clk_usbpll.rate = 0;
 	else
 		clk_usbpll.rate = clk_get_pllrate_from_reg(clkin,
@@ -397,9 +397,9 @@ static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
 {
 	u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
 
-	reg = readl(CLKPWR_USB_CTRL(CLKPWR_IOBASE)) & ~0x1FFFF;
+	reg = readl(LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE)) & ~0x1FFFF;
 	reg |= tmp;
-	writel(reg, CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+	writel(reg, LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
 
 	return clk_check_pll_setup(clk_usbpll.parent->rate,
 		pHCLKPllSetup);
@@ -410,25 +410,26 @@ static int local_usbpll_enable(struct clk *clk, int enable)
 	u32 reg;
 	int ret = -ENODEV, qj = (jiffies / 4);
 
-	reg = readl(CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+	reg = readl(LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
 
 	if (enable == 0) {
-		reg &= ~(CLKPWR_USBCTRL_CLK_EN1 | CLKPWR_USBCTRL_CLK_EN2);
-		writel(reg, CLKPWR_USB_CTRL(CLKPWR_IOBASE));
-	} else if (reg & CLKPWR_USBCTRL_PLL_PWRUP) {
-		reg |= CLKPWR_USBCTRL_CLK_EN1;
-		writel(reg, CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+		reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
+			LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
+		writel(reg, LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+	} else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
+		reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+		writel(reg, LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
 
 		/* Wait for PLL lock */
 		while (qj < jiffies) {
-			reg = readl(CLKPWR_USB_CTRL(CLKPWR_IOBASE));
-			if (reg & CLKPWR_USBCTRL_PLL_STS)
+			reg = readl(LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+			if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
 				ret = 0;
 		}
 
 		if (ret == 0) {
-			reg |= CLKPWR_USBCTRL_CLK_EN2;
-			writel(reg, CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+			reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+			writel(reg, LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
 		}
 	}
 
@@ -450,25 +451,25 @@ static int local_usbpll_set_rate(struct clk *clk, u32 rate)
 		return 0;
 
 	clkin = clk->parent->rate;
-	usbdiv = readl(CLKPWR_USBCLK_PDIV(CLKPWR_IOBASE)) + 1;
+	usbdiv = readl(LPC32XX_CLKPWR_USBCLK_PDIV(CLKPWR_IOBASE)) + 1;
 	clkin = clkin / usbdiv;
 
 	/* Try to find a good rate setup */
 	if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
 		return -EINVAL;
 
-	reg = readl(CLKPWR_USB_CTRL(CLKPWR_IOBASE));
-	reg |= CLKPWR_USBCTRL_CLK_EN1;
-	writel(reg, CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+	reg = readl(LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+	reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+	writel(reg, LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
 
 	pllsetup.analog_on = 1;
 	local_clk_usbpll_setup(&pllsetup);
 
 	clk->rate = clk_check_pll_setup(clkin, &pllsetup);
 
-	reg = readl(CLKPWR_USB_CTRL(CLKPWR_IOBASE));
-	reg |= CLKPWR_USBCTRL_CLK_EN2;
-	writel(reg, CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+	reg = readl(LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
+	reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+	writel(reg, LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE));
 
 	return 0;
 }
@@ -482,8 +483,8 @@ static struct clk clk_usbpll = {
 static u32 clk_get_hclk_div(void)
 {
 	static const u32 hclkdivs[4] = {1, 2, 4, 4};
-	return hclkdivs[CLKPWR_HCLKDIV_DIV_2POW(
-		readl(CLKPWR_HCLK_DIV(CLKPWR_IOBASE)))];
+	return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
+		readl(LPC32XX_CLKPWR_HCLK_DIV(CLKPWR_IOBASE)))];
 }
 
 static struct clk clk_hclk = {
@@ -514,86 +515,86 @@ static int local_onoff_enable(struct clk *clk, int enable)
 static struct clk clk_timer0 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_TMRPWMCLK_TIMER0_EN,
+	.enable_reg	= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
 };
 static struct clk clk_timer1 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_TMRPWMCLK_TIMER1_EN,
+	.enable_reg	= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
 };
 static struct clk clk_timer2 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_TMRPWMCLK_TIMER2_EN,
+	.enable_reg	= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
 };
 static struct clk clk_timer3 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_TMRPWMCLK_TIMER3_EN,
+	.enable_reg	= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
 };
 static struct clk clk_wdt = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_TIMER_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_PWMCLK_WDOG_EN,
+	.enable_reg	= LPC32XX_CLKPWR_TIMER_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
 };
 static struct clk clk_vfp9 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_DEBUG_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_VFP_CLOCK_ENABLE_BIT,
+	.enable_reg	= LPC32XX_CLKPWR_DEBUG_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
 };
 static struct clk clk_dma = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_DMA_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_DMACLKCTRL_CLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_DMA_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
 };
 
 static struct clk clk_uart3 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_UARTCLKCTRL_UART3_EN,
+	.enable_reg	= LPC32XX_CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
 };
 
 static struct clk clk_uart4 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_UARTCLKCTRL_UART4_EN,
+	.enable_reg	= LPC32XX_CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
 };
 
 static struct clk clk_uart5 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_UARTCLKCTRL_UART5_EN,
+	.enable_reg	= LPC32XX_CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
 };
 
 static struct clk clk_uart6 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_UARTCLKCTRL_UART6_EN,
+	.enable_reg	= LPC32XX_CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
 };
 
 static struct clk clk_i2c0 = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_I2CCLK_I2C1CLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
 };
 
 static struct clk clk_i2c1 = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_I2CCLK_I2C2CLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
 };
 
 static struct clk clk_i2c2 = {
@@ -606,49 +607,50 @@ static struct clk clk_i2c2 = {
 static struct clk clk_ssp0 = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_SSPCTRL_SSPCLK0_EN,
+	.enable_reg	= LPC32XX_CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
 };
 static struct clk clk_ssp1 = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_SSPCTRL_SSPCLK1_EN,
+	.enable_reg	= LPC32XX_CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
 };
 
 static struct clk clk_kscan = {
 	.parent		= &osc_32KHz,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_KEY_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_KEYCLKCTRL_CLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_KEY_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
 };
 
 static struct clk clk_nand = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_NAND_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_NANDCLK_SLCCLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_NAND_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
 };
 
 static struct clk clk_i2s0 = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_I2SCTRL_I2SCLK0_EN,
+	.enable_reg	= LPC32XX_CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
 };
 static struct clk clk_i2s1 = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_I2SCTRL_I2SCLK1_EN,
+	.enable_reg	= LPC32XX_CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
 };
 
 static struct clk clk_net = {
 	.parent		= &clk_hclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_MACCLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= (CLKPWR_MACCTRL_DMACLK_EN |
-		CLKPWR_MACCTRL_MMIOCLK_EN | CLKPWR_MACCTRL_HRCCLK_EN),
+	.enable_reg	= LPC32XX_CLKPWR_MACCLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
+		LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
+		LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
 };
 
 static struct clk clk_rtc = {
@@ -659,8 +661,8 @@ static struct clk clk_rtc = {
 static struct clk clk_usbd = {
 	.parent		= &clk_usbpll,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_USB_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_USBCTRL_HCLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_USB_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
 };
 
 static int tsc_onoff_enable(struct clk *clk, int enable)
@@ -668,9 +670,9 @@ static int tsc_onoff_enable(struct clk *clk, int enable)
 	u32 tmp;
 
 	/* Make sure 32KHz clock is the selected clock */
-	tmp = readl(CLKPWR_ADC_CLK_CTRL_1(CLKPWR_IOBASE));
-	tmp &= ~CLKPWR_ADCCTRL1_PCLK_SEL;
-	writel(tmp, CLKPWR_ADC_CLK_CTRL_1(CLKPWR_IOBASE));
+	tmp = readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1(CLKPWR_IOBASE));
+	tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+	writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1(CLKPWR_IOBASE));
 
 	if (enable == 0)
 		writel(0, clk->enable_reg);
@@ -683,22 +685,24 @@ static int tsc_onoff_enable(struct clk *clk, int enable)
 static struct clk clk_tsc = {
 	.parent		= &osc_32KHz,
 	.enable		= &tsc_onoff_enable,
-	.enable_reg	= CLKPWR_ADC_CLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_ADC32CLKCTRL_CLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_ADC_CLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
 };
 
 static int mmc_onoff_enable(struct clk *clk, int enable)
 {
 	u32 tmp;
 
-	tmp = readl(CLKPWR_MS_CTRL(CLKPWR_IOBASE)) &
-		~(CLKPWR_MSCARD_SDCARD_EN|CLKPWR_MSCARD_SDCARD_DIV(15));
+	tmp = readl(LPC32XX_CLKPWR_MS_CTRL(CLKPWR_IOBASE)) &
+		~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
+		LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(15));
 
 	/* If rate is 0, disable clock */
 	if (enable != 0)
-		tmp |= CLKPWR_MSCARD_SDCARD_EN | CLKPWR_MSCARD_SDCARD_DIV(1);
+		tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
+			LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(1);
 
-	writel(tmp, CLKPWR_MS_CTRL(CLKPWR_IOBASE));
+	writel(tmp, LPC32XX_CLKPWR_MS_CTRL(CLKPWR_IOBASE));
 
 	return 0;
 }
@@ -707,8 +711,8 @@ static u32 mmc_get_rate(struct clk *clk)
 {
 	u32 div, tmp, rate;
 
-	div = readl(CLKPWR_MS_CTRL(CLKPWR_IOBASE));
-	tmp = div & CLKPWR_MSCARD_SDCARD_EN;
+	div = readl(LPC32XX_CLKPWR_MS_CTRL(CLKPWR_IOBASE));
+	tmp = div & LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
 
 	if (!tmp)
 		return 0;
@@ -742,16 +746,16 @@ static struct clk clk_mmc = {
 	.set_rate	= &mmc_set_rate,
 	.get_rate	= &mmc_get_rate,
 	.enable		= &mmc_onoff_enable,
-	.enable_reg	= CLKPWR_MS_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_MSCARD_SDCARD_EN,
+	.enable_reg	= LPC32XX_CLKPWR_MS_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
 };
 
 static u32 clcd_get_rate(struct clk *clk)
 {
 	u32 tmp, div, rate;
 
-	tmp = readl(CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE)) &
-		CLKPWR_LCDCTRL_CLK_EN;
+	tmp = readl(LPC32XX_CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE)) &
+		LPC32XX_CLKPWR_LCDCTRL_CLK_EN;
 
 	if (!tmp)
 		return 0;
@@ -802,8 +806,8 @@ static struct clk clk_lcd = {
 	.set_rate	= &clcd_set_rate,
 	.get_rate	= &clcd_get_rate,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE),
-	.enable_mask	= CLKPWR_LCDCTRL_CLK_EN,
+	.enable_reg	= LPC32XX_CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE),
+	.enable_mask	= LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
 };
 
 static inline void clk_lock(void)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index f4e2113..2a97ce0 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -109,7 +109,7 @@ void lpc32xx_get_uid(u32 devid[4])
 	int i;
 
 	for (i = 0; i < 4; i++)
-		devid[i] = readl(CLKPWR_DEVID(CLKPWR_IOBASE, i << 2));
+		devid[i] = readl(LPC32XX_CLKPWR_DEVID(CLKPWR_IOBASE, i << 2));
 }
 
 /*
@@ -118,8 +118,8 @@ void lpc32xx_get_uid(u32 devid[4])
  */
 int clk_is_sysclk_mainosc(void)
 {
-	if ((readl(CLKPWR_SYSCLK_CTRL(CLKPWR_IOBASE)) &
-		CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
+	if ((readl(LPC32XX_CLKPWR_SYSCLK_CTRL(CLKPWR_IOBASE)) &
+		LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
 		return 1;
 
 	return 0;
@@ -131,8 +131,8 @@ int clk_is_sysclk_mainosc(void)
 void lpc32xx_watchdog_reset(void)
 {
 	/* Make sure WDT clocks are enabled */
-	writel(CLKPWR_PWMCLK_WDOG_EN,
-		CLKPWR_TIMER_CLK_CTRL(CLKPWR_IOBASE));
+	writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+		LPC32XX_CLKPWR_TIMER_CLK_CTRL(CLKPWR_IOBASE));
 
 	/* Instand assert of RESETOUT_N with pulse length 1mS */
 	writel(13000, WDT_IOBASE + 0x18);
@@ -217,11 +217,11 @@ u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
 	pllcfg.cco_bypass_b15 = 0;
 	pllcfg.direct_output_b14 = 0;
 	pllcfg.fdbk_div_ctrl_b13 = 0;
-	if ((regval & CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
+	if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
 		pllcfg.cco_bypass_b15 = 1;
-	if ((regval & CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
+	if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
 		pllcfg.direct_output_b14 = 1;
-	if ((regval & CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
+	if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
 		pllcfg.fdbk_div_ctrl_b13 = 1;
 	pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
 	pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
@@ -232,7 +232,7 @@ u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
 
 u32 clk_get_pclk_div(void)
 {
-	return 1 + ((readl(CLKPWR_HCLK_DIV(CLKPWR_IOBASE)) >> 2) &
+	return 1 + ((readl(LPC32XX_CLKPWR_HCLK_DIV(CLKPWR_IOBASE)) >> 2) &
 		0x1F);
 }
 
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 42fe08d..7e9ade1 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -135,455 +135,455 @@
 /*
  * Clock and Power control register offsets
  */
-#define CLKPWR_DEBUG_CTRL(x)		((x) + 0x000)
-#define CLKPWR_BOOTMAP(x)		((x) + 0x014)
-#define CLKPWR_P01_ER(x)		((x) + 0x018)
-#define CLKPWR_USBCLK_PDIV(x)		((x) + 0x01C)
-#define CLKPWR_INT_ER(x)		((x) + 0x020)
-#define CLKPWR_INT_RS(x)		((x) + 0x024)
-#define CLKPWR_INT_SR(x)		((x) + 0x028)
-#define CLKPWR_INT_AP(x)		((x) + 0x02C)
-#define CLKPWR_PIN_ER(x)		((x) + 0x030)
-#define CLKPWR_PIN_RS(x)		((x) + 0x034)
-#define CLKPWR_PIN_SR(x)		((x) + 0x038)
-#define CLKPWR_PIN_AP(x)		((x) + 0x03C)
-#define CLKPWR_HCLK_DIV(x)		((x) + 0x040)
-#define CLKPWR_PWR_CTRL(x)		((x) + 0x044)
-#define CLKPWR_PLL397_CTRL(x)		((x) + 0x048)
-#define CLKPWR_MAIN_OSC_CTRL(x)		((x) + 0x04C)
-#define CLKPWR_SYSCLK_CTRL(x)		((x) + 0x050)
-#define CLKPWR_LCDCLK_CTRL(x)		((x) + 0x054)
-#define CLKPWR_HCLKPLL_CTRL(x)		((x) + 0x058)
-#define CLKPWR_ADC_CLK_CTRL_1(x)	((x) + 0x060)
-#define CLKPWR_USB_CTRL(x)		((x) + 0x064)
-#define CLKPWR_SDRAMCLK_CTRL(x)		((x) + 0x068)
-#define CLKPWR_DDR_LAP_NOM(x)		((x) + 0x06C)
-#define CLKPWR_DDR_LAP_COUNT(x)		((x) + 0x070)
-#define CLKPWR_DDR_LAP_DELAY(x)		((x) + 0x074)
-#define CLKPWR_SSP_CLK_CTRL(x)		((x) + 0x078)
-#define CLKPWR_I2S_CLK_CTRL(x)		((x) + 0x07C)
-#define CLKPWR_MS_CTRL(x)		((x) + 0x080)
-#define CLKPWR_MACCLK_CTRL(x)		((x) + 0x090)
-#define CLKPWR_TEST_CLK_SEL(x)		((x) + 0x0A4)
-#define CLKPWR_SFW_INT(x)		((x) + 0x0A8)
-#define CLKPWR_I2C_CLK_CTRL(x)		((x) + 0x0AC)
-#define CLKPWR_KEY_CLK_CTRL(x)		((x) + 0x0B0)
-#define CLKPWR_ADC_CLK_CTRL(x)		((x) + 0x0B4)
-#define CLKPWR_PWM_CLK_CTRL(x)		((x) + 0x0B8)
-#define CLKPWR_TIMER_CLK_CTRL(x)	((x) + 0x0BC)
-#define CLKPWR_TIMERS_PWMS_CLK_CTRL_1(x) ((x) + 0x0C0)
-#define CLKPWR_SPI_CLK_CTRL(x)		((x) + 0x0C4)
-#define CLKPWR_NAND_CLK_CTRL(x)		((x) + 0x0C8)
-#define CLKPWR_UART3_CLK_CTRL(x)	((x) + 0x0D0)
-#define CLKPWR_UART4_CLK_CTRL(x)	((x) + 0x0D4)
-#define CLKPWR_UART5_CLK_CTRL(x)	((x) + 0x0D8)
-#define CLKPWR_UART6_CLK_CTRL(x)	((x) + 0x0DC)
-#define CLKPWR_IRDA_CLK_CTRL(x)		((x) + 0x0E0)
-#define CLKPWR_UART_CLK_CTRL(x)		((x) + 0x0E4)
-#define CLKPWR_DMA_CLK_CTRL(x)		((x) + 0x0E8)
-#define CLKPWR_AUTOCLOCK(x)		((x) + 0x0EC)
-#define CLKPWR_DEVID(x, y)		((x) + 0x130 + (y))
+#define LPC32XX_CLKPWR_DEBUG_CTRL(x)		((x) + 0x000)
+#define LPC32XX_CLKPWR_BOOTMAP(x)		((x) + 0x014)
+#define LPC32XX_CLKPWR_P01_ER(x)		((x) + 0x018)
+#define LPC32XX_CLKPWR_USBCLK_PDIV(x)		((x) + 0x01C)
+#define LPC32XX_CLKPWR_INT_ER(x)		((x) + 0x020)
+#define LPC32XX_CLKPWR_INT_RS(x)		((x) + 0x024)
+#define LPC32XX_CLKPWR_INT_SR(x)		((x) + 0x028)
+#define LPC32XX_CLKPWR_INT_AP(x)		((x) + 0x02C)
+#define LPC32XX_CLKPWR_PIN_ER(x)		((x) + 0x030)
+#define LPC32XX_CLKPWR_PIN_RS(x)		((x) + 0x034)
+#define LPC32XX_CLKPWR_PIN_SR(x)		((x) + 0x038)
+#define LPC32XX_CLKPWR_PIN_AP(x)		((x) + 0x03C)
+#define LPC32XX_CLKPWR_HCLK_DIV(x)		((x) + 0x040)
+#define LPC32XX_CLKPWR_PWR_CTRL(x)		((x) + 0x044)
+#define LPC32XX_CLKPWR_PLL397_CTRL(x)		((x) + 0x048)
+#define LPC32XX_CLKPWR_MAIN_OSC_CTRL(x)		((x) + 0x04C)
+#define LPC32XX_CLKPWR_SYSCLK_CTRL(x)		((x) + 0x050)
+#define LPC32XX_CLKPWR_LCDCLK_CTRL(x)		((x) + 0x054)
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL(x)		((x) + 0x058)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1(x)	((x) + 0x060)
+#define LPC32XX_CLKPWR_USB_CTRL(x)		((x) + 0x064)
+#define LPC32XX_CLKPWR_SDRAMCLK_CTRL(x)		((x) + 0x068)
+#define LPC32XX_CLKPWR_DDR_LAP_NOM(x)		((x) + 0x06C)
+#define LPC32XX_CLKPWR_DDR_LAP_COUNT(x)		((x) + 0x070)
+#define LPC32XX_CLKPWR_DDR_LAP_DELAY(x)		((x) + 0x074)
+#define LPC32XX_CLKPWR_SSP_CLK_CTRL(x)		((x) + 0x078)
+#define LPC32XX_CLKPWR_I2S_CLK_CTRL(x)		((x) + 0x07C)
+#define LPC32XX_CLKPWR_MS_CTRL(x)		((x) + 0x080)
+#define LPC32XX_CLKPWR_MACCLK_CTRL(x)		((x) + 0x090)
+#define LPC32XX_CLKPWR_TEST_CLK_SEL(x)		((x) + 0x0A4)
+#define LPC32XX_CLKPWR_SFW_INT(x)		((x) + 0x0A8)
+#define LPC32XX_CLKPWR_I2C_CLK_CTRL(x)		((x) + 0x0AC)
+#define LPC32XX_CLKPWR_KEY_CLK_CTRL(x)		((x) + 0x0B0)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL(x)		((x) + 0x0B4)
+#define LPC32XX_CLKPWR_PWM_CLK_CTRL(x)		((x) + 0x0B8)
+#define LPC32XX_CLKPWR_TIMER_CLK_CTRL(x)	((x) + 0x0BC)
+#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(x) ((x) + 0x0C0)
+#define LPC32XX_CLKPWR_SPI_CLK_CTRL(x)		((x) + 0x0C4)
+#define LPC32XX_CLKPWR_NAND_CLK_CTRL(x)		((x) + 0x0C8)
+#define LPC32XX_CLKPWR_UART3_CLK_CTRL(x)	((x) + 0x0D0)
+#define LPC32XX_CLKPWR_UART4_CLK_CTRL(x)	((x) + 0x0D4)
+#define LPC32XX_CLKPWR_UART5_CLK_CTRL(x)	((x) + 0x0D8)
+#define LPC32XX_CLKPWR_UART6_CLK_CTRL(x)	((x) + 0x0DC)
+#define LPC32XX_CLKPWR_IRDA_CLK_CTRL(x)		((x) + 0x0E0)
+#define LPC32XX_CLKPWR_UART_CLK_CTRL(x)		((x) + 0x0E4)
+#define LPC32XX_CLKPWR_DMA_CLK_CTRL(x)		((x) + 0x0E8)
+#define LPC32XX_CLKPWR_AUTOCLOCK(x)		((x) + 0x0EC)
+#define LPC32XX_CLKPWR_DEVID(x, y)		((x) + 0x130 + (y))
 
 /*
  * clkpwr_debug_ctrl register definitions
 */
-#define CLKPWR_VFP_CLOCK_ENABLE_BIT	_BIT(4)
+#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT	_BIT(4)
 
 /*
  * clkpwr_bootmap register definitions
  */
-#define CLKPWR_BOOTMAP_SEL_BIT		_BIT(1)
+#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT		_BIT(1)
 
 /*
  * clkpwr_start_gpio register bit definitions
  */
-#define CLKPWR_GPIOSRC_P1IO23_BIT	_BIT(31)
-#define CLKPWR_GPIOSRC_P1IO22_BIT	_BIT(30)
-#define CLKPWR_GPIOSRC_P1IO21_BIT	_BIT(29)
-#define CLKPWR_GPIOSRC_P1IO20_BIT	_BIT(28)
-#define CLKPWR_GPIOSRC_P1IO19_BIT	_BIT(27)
-#define CLKPWR_GPIOSRC_P1IO18_BIT	_BIT(26)
-#define CLKPWR_GPIOSRC_P1IO17_BIT	_BIT(25)
-#define CLKPWR_GPIOSRC_P1IO16_BIT	_BIT(24)
-#define CLKPWR_GPIOSRC_P1IO15_BIT	_BIT(23)
-#define CLKPWR_GPIOSRC_P1IO14_BIT	_BIT(22)
-#define CLKPWR_GPIOSRC_P1IO13_BIT	_BIT(21)
-#define CLKPWR_GPIOSRC_P1IO12_BIT	_BIT(20)
-#define CLKPWR_GPIOSRC_P1IO11_BIT	_BIT(19)
-#define CLKPWR_GPIOSRC_P1IO10_BIT	_BIT(18)
-#define CLKPWR_GPIOSRC_P1IO9_BIT	_BIT(17)
-#define CLKPWR_GPIOSRC_P1IO8_BIT	_BIT(16)
-#define CLKPWR_GPIOSRC_P1IO7_BIT	_BIT(15)
-#define CLKPWR_GPIOSRC_P1IO6_BIT	_BIT(14)
-#define CLKPWR_GPIOSRC_P1IO5_BIT	_BIT(13)
-#define CLKPWR_GPIOSRC_P1IO4_BIT	_BIT(12)
-#define CLKPWR_GPIOSRC_P1IO3_BIT	_BIT(11)
-#define CLKPWR_GPIOSRC_P1IO2_BIT	_BIT(10)
-#define CLKPWR_GPIOSRC_P1IO1_BIT	_BIT(9)
-#define CLKPWR_GPIOSRC_P1IO0_BIT	_BIT(8)
-#define CLKPWR_GPIOSRC_P0IO7_BIT	_BIT(7)
-#define CLKPWR_GPIOSRC_P0IO6_BIT	_BIT(6)
-#define CLKPWR_GPIOSRC_P0IO5_BIT	_BIT(5)
-#define CLKPWR_GPIOSRC_P0IO4_BIT	_BIT(4)
-#define CLKPWR_GPIOSRC_P0IO3_BIT	_BIT(3)
-#define CLKPWR_GPIOSRC_P0IO2_BIT	_BIT(2)
-#define CLKPWR_GPIOSRC_P0IO1_BIT	_BIT(1)
-#define CLKPWR_GPIOSRC_P0IO0_BIT	_BIT(0)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT	_BIT(31)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT	_BIT(30)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT	_BIT(29)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT	_BIT(28)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT	_BIT(27)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT	_BIT(26)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT	_BIT(25)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT	_BIT(24)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT	_BIT(23)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT	_BIT(22)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT	_BIT(21)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT	_BIT(20)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT	_BIT(19)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT	_BIT(18)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT	_BIT(17)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT	_BIT(16)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT	_BIT(15)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT	_BIT(14)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT	_BIT(13)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT	_BIT(12)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT	_BIT(11)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT	_BIT(10)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT	_BIT(9)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT	_BIT(8)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT	_BIT(7)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT	_BIT(6)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT	_BIT(5)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT	_BIT(4)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT	_BIT(3)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT	_BIT(2)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT	_BIT(1)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT	_BIT(0)
 
 /*
  * clkpwr_usbclk_pdiv register definitions
  */
-#define CLKPWR_SET_PLL_USBPDIV(n)	((n) & 0xF)
-#define CLKPWR_USBPDIV_PLL_MASK		0xF
+#define LPC32XX_CLKPWR_SET_PLL_USBPDIV(n)	((n) & 0xF)
+#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK		0xF
 
 /*
  * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
  * clkpwr_start_pol_int, register bit definitions
  */
-#define CLKPWR_INTSRC_ADC_BIT		_BIT(31)
-#define CLKPWR_INTSRC_TS_P_BIT		_BIT(30)
-#define CLKPWR_INTSRC_TS_AUX_BIT	_BIT(29)
-#define CLKPWR_INTSRC_USBAHNEEDCLK_BIT	_BIT(26)
-#define CLKPWR_INTSRC_MSTIMER_BIT	_BIT(25)
-#define CLKPWR_INTSRC_RTC_BIT		_BIT(24)
-#define CLKPWR_INTSRC_USBNEEDCLK_BIT	_BIT(23)
-#define CLKPWR_INTSRC_USB_BIT		_BIT(22)
-#define CLKPWR_INTSRC_I2C_BIT		_BIT(21)
-#define CLKPWR_INTSRC_USBOTGTIMER_BIT	_BIT(20)
-#define CLKPWR_INTSRC_USBATXINT_BIT	_BIT(19)
-#define CLKPWR_INTSRC_KEY_BIT		_BIT(16)
-#define CLKPWR_INTSRC_MAC_BIT		_BIT(7)
-#define CLKPWR_INTSRC_P0P1_BIT		_BIT(6)
-#define CLKPWR_INTSRC_GPIO_05_BIT	_BIT(5)
-#define CLKPWR_INTSRC_GPIO_04_BIT	_BIT(4)
-#define CLKPWR_INTSRC_GPIO_03_BIT	_BIT(3)
-#define CLKPWR_INTSRC_GPIO_02_BIT	_BIT(2)
-#define CLKPWR_INTSRC_GPIO_01_BIT	_BIT(1)
-#define CLKPWR_INTSRC_GPIO_00_BIT	_BIT(0)
+#define LPC32XX_CLKPWR_INTSRC_ADC_BIT		_BIT(31)
+#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT		_BIT(30)
+#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT	_BIT(29)
+#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT	_BIT(26)
+#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT	_BIT(25)
+#define LPC32XX_CLKPWR_INTSRC_RTC_BIT		_BIT(24)
+#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT	_BIT(23)
+#define LPC32XX_CLKPWR_INTSRC_USB_BIT		_BIT(22)
+#define LPC32XX_CLKPWR_INTSRC_I2C_BIT		_BIT(21)
+#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT	_BIT(20)
+#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT	_BIT(19)
+#define LPC32XX_CLKPWR_INTSRC_KEY_BIT		_BIT(16)
+#define LPC32XX_CLKPWR_INTSRC_MAC_BIT		_BIT(7)
+#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT		_BIT(6)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT	_BIT(5)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT	_BIT(4)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT	_BIT(3)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT	_BIT(2)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT	_BIT(1)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT	_BIT(0)
 
 /*
  * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
  * clkpwr_start_pol_pin register bit definitions
  */
-#define CLKPWR_EXTSRC_U7_RX_BIT		_BIT(31)
-#define CLKPWR_EXTSRC_U7_HCTS_BIT	_BIT(30)
-#define CLKPWR_EXTSRC_U6_IRRX_BIT	_BIT(28)
-#define CLKPWR_EXTSRC_U5_RX_BIT		_BIT(26)
-#define CLKPWR_EXTSRC_GPI_11_BIT	_BIT(25)
-#define CLKPWR_EXTSRC_U3_RX_BIT		_BIT(24)
-#define CLKPWR_EXTSRC_U2_HCTS_BIT	_BIT(23)
-#define CLKPWR_EXTSRC_U2_RX_BIT		_BIT(22)
-#define CLKPWR_EXTSRC_U1_RX_BIT		_BIT(21)
-#define CLKPWR_EXTSRC_MSDIO_INT_BIT	_BIT(18)
-#define CLKPWR_EXTSRC_MSDIO_SRT_BIT	_BIT(17)
-#define CLKPWR_EXTSRC_GPIO_O6_BIT	_BIT(16)
-#define CLKPWR_EXTSRC_GPIO_O5_BIT	_BIT(15)
-#define CLKPWR_EXTSRC_GPIO_O4_BIT	_BIT(14)
-#define CLKPWR_EXTSRC_GPIO_O3_BIT	_BIT(13)
-#define CLKPWR_EXTSRC_GPIO_O2_BIT	_BIT(12)
-#define CLKPWR_EXTSRC_GPIO_O1_BIT	_BIT(11)
-#define CLKPWR_EXTSRC_GPIO_O0_BIT	_BIT(10)
-#define CLKPWR_EXTSRC_SYSCLKEN_BIT	_BIT(9)
-#define CLKPWR_EXTSRC_SPI1_DATIN_BIT	_BIT(8)
-#define CLKPWR_EXTSRC_GPIO_O7_BIT	_BIT(7)
-#define CLKPWR_EXTSRC_SPI2_DATIN_BIT	_BIT(6)
-#define CLKPWR_EXTSRC_GPIO_19_BIT	_BIT(5)
-#define CLKPWR_EXTSRC_GPIO_O9_BIT	_BIT(4)
-#define CLKPWR_EXTSRC_GPIO_O8_BIT	_BIT(3)
+#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT		_BIT(31)
+#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT	_BIT(30)
+#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT	_BIT(28)
+#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT		_BIT(26)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_11_BIT	_BIT(25)
+#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT		_BIT(24)
+#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT	_BIT(23)
+#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT		_BIT(22)
+#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT		_BIT(21)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT	_BIT(18)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT	_BIT(17)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O6_BIT	_BIT(16)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O5_BIT	_BIT(15)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O4_BIT	_BIT(14)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O3_BIT	_BIT(13)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O2_BIT	_BIT(12)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O1_BIT	_BIT(11)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O0_BIT	_BIT(10)
+#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT	_BIT(9)
+#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT	_BIT(8)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O7_BIT	_BIT(7)
+#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT	_BIT(6)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_19_BIT	_BIT(5)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O9_BIT	_BIT(4)
+#define LPC32XX_CLKPWR_EXTSRC_GPIO_O8_BIT	_BIT(3)
 
 /*
  * clkpwr_hclk_div register definitions
  */
-#define CLKPWR_HCLKDIV_DDRCLK_STOP	(0x0 << 7)
-#define CLKPWR_HCLKDIV_DDRCLK_NORM	(0x1 << 7)
-#define CLKPWR_HCLKDIV_DDRCLK_HALF	(0x2 << 7)
-#define CLKPWR_HCLKDIV_PCLK_DIV(n)	(((n) & 0x1F) << 2)
-#define CLKPWR_HCLKDIV_DIV_2POW(n)	((n) & 0x3)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP	(0x0 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM	(0x1 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF	(0x2 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n)	(((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n)	((n) & 0x3)
 
 /*
  * clkpwr_pwr_ctrl register definitions
  */
-#define CLKPWR_CTRL_FORCE_PCLK		_BIT(10)
-#define CLKPWR_SDRAM_SELF_RFSH		_BIT(9)
-#define CLKPWR_UPD_SDRAM_SELF_RFSH	_BIT(8)
-#define CLKPWR_AUTO_SDRAM_SELF_RFSH	_BIT(7)
-#define CLKPWR_HIGHCORE_STATE_BIT	_BIT(5)
-#define CLKPWR_SYSCLKEN_STATE_BIT	_BIT(4)
-#define CLKPWR_SYSCLKEN_GPIO_EN		_BIT(3)
-#define CLKPWR_SELECT_RUN_MODE		_BIT(2)
-#define CLKPWR_HIGHCORE_GPIO_EN		_BIT(1)
-#define CLKPWR_STOP_MODE_CTRL		_BIT(0)
+#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK		_BIT(10)
+#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH		_BIT(9)
+#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH	_BIT(8)
+#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH	_BIT(7)
+#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT	_BIT(5)
+#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT	_BIT(4)
+#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN		_BIT(3)
+#define LPC32XX_CLKPWR_SELECT_RUN_MODE		_BIT(2)
+#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN		_BIT(1)
+#define LPC32XX_CLKPWR_STOP_MODE_CTRL		_BIT(0)
 
 /*
  * clkpwr_pll397_ctrl register definitions
  */
-#define CLKPWR_PLL397_MSLOCK_STS	_BIT(10)
-#define CLKPWR_PLL397_BYPASS		_BIT(9)
-#define CLKPWR_PLL397_BIAS_NORM		0x000
-#define CLKPWR_PLL397_BIAS_N12_5	0x040
-#define CLKPWR_PLL397_BIAS_N25		0x080
-#define CLKPWR_PLL397_BIAS_N37_5	0x0C0
-#define CLKPWR_PLL397_BIAS_P12_5	0x100
-#define CLKPWR_PLL397_BIAS_P25		0x140
-#define CLKPWR_PLL397_BIAS_P37_5	0x180
-#define CLKPWR_PLL397_BIAS_P50		0x1C0
-#define CLKPWR_PLL397_BIAS_MASK		0x1C0
-#define CLKPWR_SYSCTRL_PLL397_DIS	_BIT(1)
-#define CLKPWR_SYSCTRL_PLL397_STS	_BIT(0)
+#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS	_BIT(10)
+#define LPC32XX_CLKPWR_PLL397_BYPASS		_BIT(9)
+#define LPC32XX_CLKPWR_PLL397_BIAS_NORM		0x000
+#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5	0x040
+#define LPC32XX_CLKPWR_PLL397_BIAS_N25		0x080
+#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5	0x0C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5	0x100
+#define LPC32XX_CLKPWR_PLL397_BIAS_P25		0x140
+#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5	0x180
+#define LPC32XX_CLKPWR_PLL397_BIAS_P50		0x1C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_MASK		0x1C0
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS	_BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS	_BIT(0)
 
 /*
  * clkpwr_main_osc_ctrl register definitions
  */
-#define CLKPWR_MOSC_ADD_CAP(n)		(((n) & 0x7F) << 2)
-#define CLKPWR_MOSC_CAP_MASK		(0x7F << 2)
-#define CLKPWR_TEST_MODE		_BIT(1)
-#define CLKPWR_MOSC_DISABLE		_BIT(0)
+#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n)		(((n) & 0x7F) << 2)
+#define LPC32XX_CLKPWR_MOSC_CAP_MASK		(0x7F << 2)
+#define LPC32XX_CLKPWR_TEST_MODE		_BIT(1)
+#define LPC32XX_CLKPWR_MOSC_DISABLE		_BIT(0)
 
 /*
  * clkpwr_sysclk_ctrl register definitions
  */
-#define CLKPWR_SYSCTRL_BP_TRIG(n)	(((n) & 0x3FF) << 2)
-#define CLKPWR_SYSCTRL_BP_MASK		(0x3FF << 2)
-#define CLKPWR_SYSCTRL_USEPLL397	_BIT(1)
-#define CLKPWR_SYSCTRL_SYSCLKMUX	_BIT(0)
+#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n)	(((n) & 0x3FF) << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK		(0x3FF << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397	_BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX	_BIT(0)
 
 /*
  * clkpwr_lcdclk_ctrl register definitions
  */
-#define CLKPWR_LCDCTRL_LCDTYPE_TFT12	0x000
-#define CLKPWR_LCDCTRL_LCDTYPE_TFT16	0x040
-#define CLKPWR_LCDCTRL_LCDTYPE_TFT15	0x080
-#define CLKPWR_LCDCTRL_LCDTYPE_TFT24	0x0C0
-#define CLKPWR_LCDCTRL_LCDTYPE_STN4M	0x100
-#define CLKPWR_LCDCTRL_LCDTYPE_STN8C	0x140
-#define CLKPWR_LCDCTRL_LCDTYPE_DSTN4M	0x180
-#define CLKPWR_LCDCTRL_LCDTYPE_DSTN8C	0x1C0
-#define CLKPWR_LCDCTRL_LCDTYPE_MSK	0x01C0
-#define CLKPWR_LCDCTRL_CLK_EN		0x020
-#define CLKPWR_LCDCTRL_SET_PSCALE(n)	((n - 1) & 0x1F)
-#define CLKPWR_LCDCTRL_PSCALE_MSK	0x001F
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12	0x000
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16	0x040
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15	0x080
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24	0x0C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M	0x100
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C	0x140
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M	0x180
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C	0x1C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK	0x01C0
+#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN		0x020
+#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n)	((n - 1) & 0x1F)
+#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK	0x001F
 
 /*
  * clkpwr_hclkpll_ctrl register definitions
  */
-#define CLKPWR_HCLKPLL_POWER_UP		_BIT(16)
-#define CLKPWR_HCLKPLL_CCO_BYPASS	_BIT(15)
-#define CLKPWR_HCLKPLL_POSTDIV_BYPASS	_BIT(14)
-#define CLKPWR_HCLKPLL_FDBK_SEL_FCLK	_BIT(13)
-#define CLKPWR_HCLKPLL_POSTDIV_2POW(n)	(((n) & 0x3) << 11)
-#define CLKPWR_HCLKPLL_PREDIV_PLUS1(n)	(((n) & 0x3) << 9)
-#define CLKPWR_HCLKPLL_PLLM(n)		(((n) & 0xFF) << 1)
-#define CLKPWR_HCLKPLL_PLL_STS		_BIT(0)
+#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP		_BIT(16)
+#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS	_BIT(15)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS	_BIT(14)
+#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK	_BIT(13)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n)	(((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n)	(((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n)		(((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS		_BIT(0)
 
 /*
  * clkpwr_adc_clk_ctrl_1 register definitions
  */
-#define CLKPWR_ADCCTRL1_RTDIV(n)	(((n) & 0xFF) << 0)
-#define CLKPWR_ADCCTRL1_PCLK_SEL	_BIT(8)
+#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n)	(((n) & 0xFF) << 0)
+#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL	_BIT(8)
 
 /*
  * clkpwr_usb_ctrl register definitions
  */
-#define CLKPWR_USBCTRL_HCLK_EN		_BIT(24)
-#define CLKPWR_USBCTRL_USBI2C_EN	_BIT(23)
-#define CLKPWR_USBCTRL_USBDVND_EN	_BIT(22)
-#define CLKPWR_USBCTRL_USBHSTND_EN	_BIT(21)
-#define CLKPWR_USBCTRL_PU_ADD		(0x0 << 19)
-#define CLKPWR_USBCTRL_BUS_KEEPER	(0x1 << 19)
-#define CLKPWR_USBCTRL_PD_ADD		(0x3 << 19)
-#define CLKPWR_USBCTRL_CLK_EN2		_BIT(18)
-#define CLKPWR_USBCTRL_CLK_EN1		_BIT(17)
-#define CLKPWR_USBCTRL_PLL_PWRUP	_BIT(16)
-#define CLKPWR_USBCTRL_CCO_BYPASS	_BIT(15)
-#define CLKPWR_USBCTRL_POSTDIV_BYPASS	_BIT(14)
-#define CLKPWR_USBCTRL_FDBK_SEL_FCLK	_BIT(13)
-#define CLKPWR_USBCTRL_POSTDIV_2POW(n)	(((n) & 0x3) << 11)
-#define CLKPWR_USBCTRL_PREDIV_PLUS1(n)	(((n) & 0x3) << 9)
-#define CLKPWR_USBCTRL_FDBK_PLUS1(n)	(((n) & 0xFF) << 1)
-#define CLKPWR_USBCTRL_PLL_STS		_BIT(0)
+#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN		_BIT(24)
+#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN	_BIT(23)
+#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN	_BIT(22)
+#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN	_BIT(21)
+#define LPC32XX_CLKPWR_USBCTRL_PU_ADD		(0x0 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER	(0x1 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_PD_ADD		(0x3 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2		_BIT(18)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1		_BIT(17)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP	_BIT(16)
+#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS	_BIT(15)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS	_BIT(14)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK	_BIT(13)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n)	(((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n)	(((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n)	(((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_STS		_BIT(0)
 
 /*
  * clkpwr_sdramclk_ctrl register definitions
  */
-#define CLKPWR_SDRCLK_FASTSLEW_CLK	_BIT(22)
-#define CLKPWR_SDRCLK_FASTSLEW		_BIT(21)
-#define CLKPWR_SDRCLK_FASTSLEW_DAT	_BIT(20)
-#define CLKPWR_SDRCLK_SW_DDR_RESET	_BIT(19)
-#define CLKPWR_SDRCLK_HCLK_DLY(n)	(((n) & 0x1F) << 14)
-#define CLKPWR_SDRCLK_DLY_ADDR_STS	_BIT(13)
-#define CLKPWR_SDRCLK_SENS_FACT(n)	(((n) & 0x7) << 10)
-#define CLKPWR_SDRCLK_USE_CAL		_BIT(9)
-#define CLKPWR_SDRCLK_DO_CAL		_BIT(8)
-#define CLKPWR_SDRCLK_CAL_ON_RTC	_BIT(7)
-#define CLKPWR_SDRCLK_DQS_DLY(n)	(((n) & 0x1F) << 2)
-#define CLKPWR_SDRCLK_USE_DDR		_BIT(1)
-#define CLKPWR_SDRCLK_CLK_DIS		_BIT(0)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK	_BIT(22)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW		_BIT(21)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT	_BIT(20)
+#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET	_BIT(19)
+#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n)	(((n) & 0x1F) << 14)
+#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS	_BIT(13)
+#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n)	(((n) & 0x7) << 10)
+#define LPC32XX_CLKPWR_SDRCLK_USE_CAL		_BIT(9)
+#define LPC32XX_CLKPWR_SDRCLK_DO_CAL		_BIT(8)
+#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC	_BIT(7)
+#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n)	(((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_SDRCLK_USE_DDR		_BIT(1)
+#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS		_BIT(0)
 
 /*
  * clkpwr_ssp_blk_ctrl register definitions
  */
-#define CLKPWR_SSPCTRL_DMA_SSP1RX	_BIT(5)
-#define CLKPWR_SSPCTRL_DMA_SSP1TX	_BIT(4)
-#define CLKPWR_SSPCTRL_DMA_SSP0RX	_BIT(3)
-#define CLKPWR_SSPCTRL_DMA_SSP0TX	_BIT(2)
-#define CLKPWR_SSPCTRL_SSPCLK1_EN	_BIT(1)
-#define CLKPWR_SSPCTRL_SSPCLK0_EN	_BIT(0)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX	_BIT(5)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX	_BIT(4)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX	_BIT(3)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX	_BIT(2)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN	_BIT(1)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN	_BIT(0)
 
 /*
  * clkpwr_i2s_clk_ctrl register definitions
  */
-#define CLKPWR_I2SCTRL_I2S1_RX_FOR_TX	_BIT(6)
-#define CLKPWR_I2SCTRL_I2S1_TX_FOR_RX	_BIT(5)
-#define CLKPWR_I2SCTRL_I2S1_USE_DMA	_BIT(4)
-#define CLKPWR_I2SCTRL_I2S0_RX_FOR_TX	_BIT(3)
-#define CLKPWR_I2SCTRL_I2S0_TX_FOR_RX	_BIT(2)
-#define CLKPWR_I2SCTRL_I2SCLK1_EN	_BIT(1)
-#define CLKPWR_I2SCTRL_I2SCLK0_EN	_BIT(0)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX	_BIT(6)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX	_BIT(5)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA	_BIT(4)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX	_BIT(3)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX	_BIT(2)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN	_BIT(1)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN	_BIT(0)
 
 /*
  * clkpwr_ms_ctrl register definitions
  */
-#define CLKPWR_MSCARD_MSDIO_PIN_DIS	_BIT(10)
-#define CLKPWR_MSCARD_MSDIO_PU_EN	_BIT(9)
-#define CLKPWR_MSCARD_MSDIO23_DIS	_BIT(8)
-#define CLKPWR_MSCARD_MSDIO1_DIS	_BIT(7)
-#define CLKPWR_MSCARD_MSDIO0_DIS	_BIT(6)
-#define CLKPWR_MSCARD_SDCARD_EN		_BIT(5)
-#define CLKPWR_MSCARD_SDCARD_DIV(n)	((n) & 0xF)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS	_BIT(10)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN	_BIT(9)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS	_BIT(8)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS	_BIT(7)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS	_BIT(6)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN		_BIT(5)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n)	((n) & 0xF)
 
 /*
  * clkpwr_macclk_ctrl register definitions
  */
-#define CLKPWR_MACCTRL_NO_ENET_PIS	0x00
-#define CLKPWR_MACCTRL_USE_MII_PINS	0x08
-#define CLKPWR_MACCTRL_USE_RMII_PINS	0x18
-#define CLKPWR_MACCTRL_PINS_MSK		0x18
-#define CLKPWR_MACCTRL_DMACLK_EN	_BIT(2)
-#define CLKPWR_MACCTRL_MMIOCLK_EN	_BIT(1)
-#define CLKPWR_MACCTRL_HRCCLK_EN	_BIT(0)
+#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS	0x00
+#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS	0x08
+#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS	0x18
+#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK		0x18
+#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN	_BIT(2)
+#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN	_BIT(1)
+#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN	_BIT(0)
 
 /*
  * clkpwr_test_clk_sel register definitions
  */
-#define CLKPWR_TESTCLK1_SEL_PERCLK	(0x0 << 5)
-#define CLKPWR_TESTCLK1_SEL_RTC		(0x1 << 5)
-#define CLKPWR_TESTCLK1_SEL_MOSC	(0x2 << 5)
-#define CLKPWR_TESTCLK1_SEL_MASK	(0x3 << 5)
-#define CLKPWR_TESTCLK_TESTCLK1_EN	_BIT(4)
-#define CLKPWR_TESTCLK2_SEL_HCLK	(0x0 << 1)
-#define CLKPWR_TESTCLK2_SEL_PERCLK	(0x1 << 1)
-#define CLKPWR_TESTCLK2_SEL_USBCLK	(0x2 << 1)
-#define CLKPWR_TESTCLK2_SEL_MOSC	(0x5 << 1)
-#define CLKPWR_TESTCLK2_SEL_PLL397	(0x7 << 1)
-#define CLKPWR_TESTCLK2_SEL_MASK	(0x7 << 1)
-#define CLKPWR_TESTCLK_TESTCLK2_EN	_BIT(0)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK	(0x0 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC		(0x1 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC	(0x2 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK	(0x3 << 5)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN	_BIT(4)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK	(0x0 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK	(0x1 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK	(0x2 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC	(0x5 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397	(0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK	(0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN	_BIT(0)
 
 /*
  * clkpwr_sw_int register definitions
  */
-#define CLKPWR_SW_INT(n)		(_BIT(0) | (((n) & 0x7F) << 1))
-#define CLKPWR_SW_GET_ARG(n)		(((n) & 0xFE) >> 1)
+#define LPC32XX_CLKPWR_SW_INT(n)		(_BIT(0) | (((n) & 0x7F) << 1))
+#define LPC32XX_CLKPWR_SW_GET_ARG(n)		(((n) & 0xFE) >> 1)
 
 /*
  * clkpwr_i2c_clk_ctrl register definitions
  */
-#define CLKPWR_I2CCLK_USBI2CHI_DRIVE	_BIT(4)
-#define CLKPWR_I2CCLK_I2C2HI_DRIVE	_BIT(3)
-#define CLKPWR_I2CCLK_I2C1HI_DRIVE	_BIT(2)
-#define CLKPWR_I2CCLK_I2C2CLK_EN	_BIT(1)
-#define CLKPWR_I2CCLK_I2C1CLK_EN	_BIT(0)
+#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE	_BIT(4)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE	_BIT(3)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE	_BIT(2)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN	_BIT(1)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN	_BIT(0)
 
 /*
  * clkpwr_key_clk_ctrl register definitions
  */
-#define CLKPWR_KEYCLKCTRL_CLK_EN	0x1
+#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN	0x1
 
 /*
  * clkpwr_adc_clk_ctrl register definitions
  */
-#define CLKPWR_ADC32CLKCTRL_CLK_EN	0x1
+#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN	0x1
 
 /*
  * clkpwr_pwm_clk_ctrl register definitions
  */
-#define CLKPWR_PWMCLK_PWM2_DIV(n)	(((n) & 0xF) << 8)
-#define CLKPWR_PWMCLK_PWM1_DIV(n)	(((n) & 0xF) << 4)
-#define CLKPWR_PWMCLK_PWM2SEL_PCLK	0x8
-#define CLKPWR_PWMCLK_PWM2CLK_EN	0x4
-#define CLKPWR_PWMCLK_PWM1SEL_PCLK	0x2
-#define CLKPWR_PWMCLK_PWM1CLK_EN	0x1
+#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n)	(((n) & 0xF) << 8)
+#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n)	(((n) & 0xF) << 4)
+#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK	0x8
+#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN	0x4
+#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK	0x2
+#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN	0x1
 
 /*
  * clkpwr_timer_clk_ctrl register definitions
  */
-#define CLKPWR_PWMCLK_HSTIMER_EN	0x2
-#define CLKPWR_PWMCLK_WDOG_EN		0x1
+#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN	0x2
+#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN		0x1
 
 /*
  * clkpwr_timers_pwms_clk_ctrl_1 register definitions
  */
-#define CLKPWR_TMRPWMCLK_TIMER3_EN	0x20
-#define CLKPWR_TMRPWMCLK_TIMER2_EN	0x10
-#define CLKPWR_TMRPWMCLK_TIMER1_EN	0x08
-#define CLKPWR_TMRPWMCLK_TIMER0_EN	0x04
-#define CLKPWR_TMRPWMCLK_PWM4_EN	0x02
-#define CLKPWR_TMRPWMCLK_PWM3_EN	0x01
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN	0x20
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN	0x10
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN	0x08
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN	0x04
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN	0x02
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN	0x01
 
 /*
  * clkpwr_spi_clk_ctrl register definitions
  */
-#define CLKPWR_SPICLK_SET_SPI2DATIO	0x80
-#define CLKPWR_SPICLK_SET_SPI2CLK	0x40
-#define CLKPWR_SPICLK_USE_SPI2		0x20
-#define CLKPWR_SPICLK_SPI2CLK_EN	0x10
-#define CLKPWR_SPICLK_SET_SPI1DATIO	0x08
-#define CLKPWR_SPICLK_SET_SPI1CLK	0x04
-#define CLKPWR_SPICLK_USE_SPI1		0x02
-#define CLKPWR_SPICLK_SPI1CLK_EN	0x01
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO	0x80
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK	0x40
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI2		0x20
+#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN	0x10
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO	0x08
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK	0x04
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI1		0x02
+#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN	0x01
 
 /*
  * clkpwr_nand_clk_ctrl register definitions
  */
-#define CLKPWR_NANDCLK_INTSEL_MLC	0x20
-#define CLKPWR_NANDCLK_DMA_RNB		0x10
-#define CLKPWR_NANDCLK_DMA_INT		0x08
-#define CLKPWR_NANDCLK_SEL_SLC		0x04
-#define CLKPWR_NANDCLK_MLCCLK_EN	0x02
-#define CLKPWR_NANDCLK_SLCCLK_EN	0x01
+#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC	0x20
+#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB		0x10
+#define LPC32XX_CLKPWR_NANDCLK_DMA_INT		0x08
+#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC		0x04
+#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN	0x02
+#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN	0x01
 
 /*
  * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
  * and clkpwr_uart6_clk_ctrl register definitions
  */
-#define CLKPWR_UART_Y_DIV(y)		((y) & 0xFF)
-#define CLKPWR_UART_X_DIV(x)		(((x) & 0xFF) << 8)
-#define CLKPWR_UART_USE_HCLK		_BIT(16)
+#define LPC32XX_CLKPWR_UART_Y_DIV(y)		((y) & 0xFF)
+#define LPC32XX_CLKPWR_UART_X_DIV(x)		(((x) & 0xFF) << 8)
+#define LPC32XX_CLKPWR_UART_USE_HCLK		_BIT(16)
 
 /*
  * clkpwr_irda_clk_ctrl register definitions
  */
-#define CLKPWR_IRDA_Y_DIV(y)		((y) & 0xFF)
-#define CLKPWR_IRDA_X_DIV(x)		(((x) & 0xFF) << 8)
+#define LPC32XX_CLKPWR_IRDA_Y_DIV(y)		((y) & 0xFF)
+#define LPC32XX_CLKPWR_IRDA_X_DIV(x)		(((x) & 0xFF) << 8)
 
 /*
  * clkpwr_uart_clk_ctrl register definitions
  */
-#define CLKPWR_UARTCLKCTRL_UART6_EN	_BIT(3)
-#define CLKPWR_UARTCLKCTRL_UART5_EN	_BIT(2)
-#define CLKPWR_UARTCLKCTRL_UART4_EN	_BIT(1)
-#define CLKPWR_UARTCLKCTRL_UART3_EN	_BIT(0)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN	_BIT(3)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN	_BIT(2)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN	_BIT(1)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN	_BIT(0)
 
 /*
  * clkpwr_dmaclk_ctrl register definitions
  */
-#define CLKPWR_DMACLKCTRL_CLK_EN	0x1
+#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN	0x1
 
 /*
  * clkpwr_autoclock register definitions
  */
-#define CLKPWR_AUTOCLK_USB_EN		0x40
-#define CLKPWR_AUTOCLK_IRAM_EN		0x02
-#define CLKPWR_AUTOCLK_IROM_EN		0x01
+#define LPC32XX_CLKPWR_AUTOCLK_USB_EN		0x40
+#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN		0x02
+#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN		0x01
 
 /*
  * Interrupt controller register offsets
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 4ee9714..0612994 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -333,30 +333,32 @@ static void __init phy3250_board_init(void)
 	gpio_direction_output(SPI0_CS_GPIO, 1);
 
 	/* Setup network interface for RMII mode */
-	tmp = readl(CLKPWR_MACCLK_CTRL(CLKPWR_IOBASE));
-	tmp &= ~CLKPWR_MACCTRL_PINS_MSK;
-	tmp |= CLKPWR_MACCTRL_USE_RMII_PINS;
-	writel(tmp, CLKPWR_MACCLK_CTRL(CLKPWR_IOBASE));
+	tmp = readl(LPC32XX_CLKPWR_MACCLK_CTRL(CLKPWR_IOBASE));
+	tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
+	tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
+	writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL(CLKPWR_IOBASE));
 
 	/* Setup SLC NAND controller muxing */
-	writel(CLKPWR_NANDCLK_SEL_SLC,
-		CLKPWR_NAND_CLK_CTRL(CLKPWR_IOBASE));
+	writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
+		LPC32XX_CLKPWR_NAND_CLK_CTRL(CLKPWR_IOBASE));
 
 	/* Setup LCD muxing to RGB565 */
-	tmp = readl(CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE)) &
-		~(CLKPWR_LCDCTRL_LCDTYPE_MSK | CLKPWR_LCDCTRL_PSCALE_MSK);
-	tmp |= CLKPWR_LCDCTRL_LCDTYPE_TFT16;
-	writel(tmp, CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE));
+	tmp = readl(LPC32XX_CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE)) &
+		~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
+		LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
+	tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
+	writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE));
 
 	/* Set up I2C pull levels */
-	tmp = readl(CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE));
-	tmp |= CLKPWR_I2CCLK_USBI2CHI_DRIVE | CLKPWR_I2CCLK_I2C2HI_DRIVE;
-	writel(tmp, CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE));
+	tmp = readl(LPC32XX_CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE));
+	tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
+		LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
+	writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL(CLKPWR_IOBASE));
 
 	/* Enable DMA for I2S1 channel */
-	tmp = readl(CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE));
-	tmp = CLKPWR_I2SCTRL_I2S1_USE_DMA;
-	writel(tmp, CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE));
+	tmp = readl(LPC32XX_CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE));
+	tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
+	writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL(CLKPWR_IOBASE));
 
 	lpc32xx_serial_init();
 
@@ -365,14 +367,14 @@ static void __init phy3250_board_init(void)
 	   here. However, we don't want to enable them if the peripheral
 	   isn't included in the image */
 #ifdef CONFIG_FB_ARMCLCD
-	tmp = readl(CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE));
-	writel((tmp | CLKPWR_LCDCTRL_CLK_EN),
-		CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE));
+	tmp = readl(LPC32XX_CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE));
+	writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
+		LPC32XX_CLKPWR_LCDCLK_CTRL(CLKPWR_IOBASE));
 #endif
 #ifdef CONFIG_SPI_PL022
-	tmp = readl(CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE));
-	writel((tmp | CLKPWR_SSPCTRL_SSPCLK0_EN),
-		CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE));
+	tmp = readl(LPC32XX_CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE));
+	writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
+		LPC32XX_CLKPWR_SSP_CLK_CTRL(CLKPWR_IOBASE));
 #endif
 
 	platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
@@ -382,8 +384,9 @@ static void __init phy3250_board_init(void)
 	}
 
 	/* Test clock needed for UDA1380 initial init */
-	writel((CLKPWR_TESTCLK2_SEL_MOSC | CLKPWR_TESTCLK_TESTCLK2_EN),
-		CLKPWR_TEST_CLK_SEL(CLKPWR_IOBASE));
+	writel((LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
+		LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN),
+		LPC32XX_CLKPWR_TEST_CLK_SEL(CLKPWR_IOBASE));
 
 	i2c_register_board_info(0, phy3250_i2c_board_info,
 				ARRAY_SIZE(phy3250_i2c_board_info));
diff --git a/arch/arm/mach-lpc32xx/pm_events.c b/arch/arm/mach-lpc32xx/pm_events.c
index d3b1b54..ffd46c4 100644
--- a/arch/arm/mach-lpc32xx/pm_events.c
+++ b/arch/arm/mach-lpc32xx/pm_events.c
@@ -36,301 +36,301 @@ struct lpc32xx_event_info {
 
 static const struct lpc32xx_event_info events[LPC32XX_LAST_EVENT + 1] = {
 	[LPC32XX_WKUP_GPI_08] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O8_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O8_BIT,
 	},
 	[LPC32XX_WKUP_GPI_09] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O9_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O9_BIT,
 	},
 	[LPC32XX_WKUP_GPI_19] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_19_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_19_BIT,
 	},
 	[LPC32XX_WKUP_SPI2_DATIN] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_SPI2_DATIN_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT,
 	},
 	[LPC32XX_WKUP_GPI_07] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O7_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O7_BIT,
 	},
 	[LPC32XX_WKUP_SPI1_DATIN] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_SPI1_DATIN_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT,
 	},
 	[LPC32XX_WKUP_SYSCLKEN] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_SYSCLKEN_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT,
 	},
 	[LPC32XX_WKUP_GPI00] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O0_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O0_BIT,
 	},
 	[LPC32XX_WKUP_GPI01] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O1_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O1_BIT,
 	},
 	[LPC32XX_WKUP_GPI02] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O2_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O2_BIT,
 	},
 	[LPC32XX_WKUP_GPI03] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O3_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O3_BIT,
 	},
 	[LPC32XX_WKUP_GPI04] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O4_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O4_BIT,
 	},
 	[LPC32XX_WKUP_GPI05] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O5_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O5_BIT,
 	},
 	[LPC32XX_WKUP_GPI06] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPIO_O6_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O6_BIT,
 	},
 	[LPC32XX_WKUP_MSDIO_START] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_MSDIO_SRT_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT,
 	},
 	[LPC32XX_WKUP_SDIO_INT_N] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_MSDIO_INT_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT,
 	},
 	[LPC32XX_WKUP_U1_RX] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U1_RX_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT,
 	},
 	[LPC32XX_WKUP_U2_RX] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U2_RX_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT,
 	},
 	[LPC32XX_WKUP_U2_HCTS] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U2_HCTS_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT,
 	},
 	[LPC32XX_WKUP_U3_RX] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U3_RX_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT,
 	},
 	[LPC32XX_WKUP_GPI_28] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_GPI_11_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_11_BIT,
 	},
 	[LPC32XX_WKUP_U5_RX] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U5_RX_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT,
 	},
 	[LPC32XX_WKUP_U6_IRRX] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U6_IRRX_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT,
 	},
 	[LPC32XX_WKUP_U7_HCTS] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U7_HCTS_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT,
 	},
 	[LPC32XX_WKUP_U7_RX] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_EXTSRC_U7_RX_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT,
 	},
 
 	[LPC32XX_WKUP_GPIO_00] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_GPIO_00_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_01] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_GPIO_01_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_02] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_GPIO_02_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_03] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_GPIO_03_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_04] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_GPIO_04_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_05] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_GPIO_05_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
 	},
 	[LPC32XX_WKUP_P0_P1_ALL] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_P0P1_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_P0P1_BIT,
 	},
 	[LPC32XX_WKUP_MAC_START] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_MAC_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
 	},
 	[LPC32XX_WKUP_KEY_IRQ] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_KEY_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
 	},
 	[LPC32XX_WKUP_USB_OTG_ATX_INT_N] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_USBATXINT_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
 	},
 	[LPC32XX_WKUP_USB_OTG_TIMER] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_USBOTGTIMER_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT,
 	},
 	[LPC32XX_WKUP_USB_I2C_INT] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_I2C_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_I2C_BIT,
 	},
 	[LPC32XX_WKUP_USB_INT] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_USB_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
 	},
 	[LPC32XX_WKUP_USB_NEED_CLK] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_USBNEEDCLK_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT,
 	},
 	[LPC32XX_WKUP_RTC_INT] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_RTC_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
 	},
 	[LPC32XX_WKUP_MSTIMER_INT] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_MSTIMER_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
 	},
 	[LPC32XX_WKUP_USB_AHC_NEED_CLK] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_USBAHNEEDCLK_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT,
 	},
 	[LPC32XX_WKUP_TS_AUX_INT] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_TS_AUX_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
 	},
 	[LPC32XX_WKUP_TS_P_INT] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_TS_P_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
 	},
 	[LPC32XX_WKUP_TS_INT] = {
-		.offs = CLKPWR_INT_ER(0),
-		.mask = CLKPWR_INTSRC_ADC_BIT,
+		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
 	},
 	[LPC32XX_WKUP_P0_0] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO0_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT,
 	},
 	[LPC32XX_WKUP_P0_1] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO1_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT,
 	},
 	[LPC32XX_WKUP_P0_2] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO2_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT,
 	},
 	[LPC32XX_WKUP_P0_3] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO3_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT,
 	},
 	[LPC32XX_WKUP_P0_4] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO4_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT,
 	},
 	[LPC32XX_WKUP_P0_5] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO5_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT,
 	},
 	[LPC32XX_WKUP_P0_6] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO6_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT,
 	},
 	[LPC32XX_WKUP_P0_7] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P0IO7_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT,
 	},
 	[LPC32XX_WKUP_P1_3] = {
-		.offs = CLKPWR_PIN_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO3_BIT,
+		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT,
 	},
 	[LPC32XX_WKUP_P1_4] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO4_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT,
 	},
 	[LPC32XX_WKUP_P1_5] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO5_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT,
 	},
 	[LPC32XX_WKUP_P1_6] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO6_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT,
 	},
 	[LPC32XX_WKUP_P1_7] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO7_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT,
 	},
 	[LPC32XX_WKUP_P1_8] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO8_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT,
 	},
 	[LPC32XX_WKUP_P1_9] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO9_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT,
 	},
 	[LPC32XX_WKUP_P1_10] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO10_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT,
 	},
 	[LPC32XX_WKUP_P1_11] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO11_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT,
 	},
 	[LPC32XX_WKUP_P1_12] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO12_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT,
 	},
 	[LPC32XX_WKUP_P1_13] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO13_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT,
 	},
 	[LPC32XX_WKUP_P1_14] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO14_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT,
 	},
 	[LPC32XX_WKUP_P1_15] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO15_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT,
 	},
 	[LPC32XX_WKUP_P1_16] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO16_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT,
 	},
 	[LPC32XX_WKUP_P1_17] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO17_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT,
 	},
 	[LPC32XX_WKUP_P1_18] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO18_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT,
 	},
 	[LPC32XX_WKUP_P1_19] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO19_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT,
 	},
 	[LPC32XX_WKUP_P1_20] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO20_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT,
 	},
 	[LPC32XX_WKUP_P1_21] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO21_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT,
 	},
 	[LPC32XX_WKUP_P1_22] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO22_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT,
 	},
 	[LPC32XX_WKUP_P1_23] = {
-		.offs = CLKPWR_P01_ER(0),
-		.mask = CLKPWR_GPIOSRC_P1IO23_BIT,
+		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT,
 	},
 };
 
@@ -339,21 +339,23 @@ void lpc32xx_event_init(void)
 	/* Initially disable all events, set all events to default
 	   type and polarity per chip User guide, and clear any
 	   pending event statuses */
-	writel(0, CLKPWR_P01_ER(CLKPWR_IOBASE));
-	writel(0, CLKPWR_INT_ER(CLKPWR_IOBASE));
-	writel(0, CLKPWR_PIN_ER(CLKPWR_IOBASE));
+	writel(0, LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE));
+	writel(0, LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE));
+	writel(0, LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE));
 
 	/* Default activation polarities, all pin sources are low edge
 	   triggered */
-	writel(CLKPWR_INTSRC_TS_P_BIT | CLKPWR_INTSRC_MSTIMER_BIT |
-		CLKPWR_INTSRC_RTC_BIT, CLKPWR_INT_AP(CLKPWR_IOBASE));
-	writel(0, CLKPWR_PIN_AP(CLKPWR_IOBASE));
+	writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
+		LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
+		LPC32XX_CLKPWR_INTSRC_RTC_BIT,
+		LPC32XX_CLKPWR_INT_AP(CLKPWR_IOBASE));
+	writel(0, LPC32XX_CLKPWR_PIN_AP(CLKPWR_IOBASE));
 
 	/* Clear latched event states */
-	writel(readl(CLKPWR_PIN_RS(CLKPWR_IOBASE)),
-		CLKPWR_PIN_RS(CLKPWR_IOBASE));
-	writel(readl(CLKPWR_INT_RS(CLKPWR_IOBASE)),
-		CLKPWR_INT_RS(CLKPWR_IOBASE));
+	writel(readl(LPC32XX_CLKPWR_PIN_RS(CLKPWR_IOBASE)),
+		LPC32XX_CLKPWR_PIN_RS(CLKPWR_IOBASE));
+	writel(readl(LPC32XX_CLKPWR_INT_RS(CLKPWR_IOBASE)),
+		LPC32XX_CLKPWR_INT_RS(CLKPWR_IOBASE));
 }
 
 void lpc32xx_event_enable(enum lpc32xx_events event_id)
@@ -374,23 +376,23 @@ extern int lpc32xx_event_set(enum lpc32xx_events event_id,
 	u32 tmp;
 
 	if (event_id <= LPC32XX_WKUP_U7_RX) {
-		tmp = readl(CLKPWR_PIN_AP(CLKPWR_IOBASE));
+		tmp = readl(LPC32XX_CLKPWR_PIN_AP(CLKPWR_IOBASE));
 
 		if (high_edge)
 			tmp |= events[event_id].mask;
 		else
 			tmp &= ~events[event_id].mask;
 
-		writel(tmp, CLKPWR_PIN_AP(CLKPWR_IOBASE));
+		writel(tmp, LPC32XX_CLKPWR_PIN_AP(CLKPWR_IOBASE));
 	} else if (event_id <= LPC32XX_WKUP_TS_INT) {
-		tmp = readl(CLKPWR_INT_AP(CLKPWR_IOBASE));
+		tmp = readl(LPC32XX_CLKPWR_INT_AP(CLKPWR_IOBASE));
 
 		if (high_edge)
 			tmp |= events[event_id].mask;
 		else
 			tmp &= ~events[event_id].mask;
 
-		writel(tmp, CLKPWR_INT_AP(CLKPWR_IOBASE));
+		writel(tmp, LPC32XX_CLKPWR_INT_AP(CLKPWR_IOBASE));
 	} else
 		return -EINVAL;
 
@@ -410,17 +412,19 @@ int lpc32xx_event_enabled(enum lpc32xx_events event_id)
 void lpc32xx_event_clear(enum lpc32xx_events event_id)
 {
 	if (event_id <= LPC32XX_WKUP_U7_RX)
-		writel(events[event_id].mask, CLKPWR_PIN_RS(CLKPWR_IOBASE));
+		writel(events[event_id].mask,
+			LPC32XX_CLKPWR_PIN_RS(CLKPWR_IOBASE));
 	else if (event_id <= LPC32XX_WKUP_TS_INT)
-		writel(events[event_id].mask, CLKPWR_INT_RS(CLKPWR_IOBASE));
+		writel(events[event_id].mask,
+			LPC32XX_CLKPWR_INT_RS(CLKPWR_IOBASE));
 }
 
 void lpc32xx_event_clear_all(void)
 {
 	/* Clear all latched event states */
-	writel(readl(CLKPWR_PIN_RS(CLKPWR_IOBASE)),
-		CLKPWR_PIN_RS(CLKPWR_IOBASE));
-	writel(readl(CLKPWR_INT_RS(CLKPWR_IOBASE)),
-		CLKPWR_INT_RS(CLKPWR_IOBASE));
+	writel(readl(LPC32XX_CLKPWR_PIN_RS(CLKPWR_IOBASE)),
+		LPC32XX_CLKPWR_PIN_RS(CLKPWR_IOBASE));
+	writel(readl(LPC32XX_CLKPWR_INT_RS(CLKPWR_IOBASE)),
+		LPC32XX_CLKPWR_INT_RS(CLKPWR_IOBASE));
 }
 
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index e4479ba..def5003 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -98,28 +98,28 @@ static struct uartinit uartinit_data[] __initdata = {
 	{
 		.uart_ck_name = "uart5_ck",
 		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 5),
-		.pdiv_clk_reg = CLKPWR_UART5_CLK_CTRL(CLKPWR_IOBASE),
+		.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART3_ENABLE
 	{
 		.uart_ck_name = "uart3_ck",
 		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 3),
-		.pdiv_clk_reg = CLKPWR_UART3_CLK_CTRL(CLKPWR_IOBASE),
+		.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART4_ENABLE
 	{
 		.uart_ck_name = "uart4_ck",
 		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 4),
-		.pdiv_clk_reg = CLKPWR_UART4_CLK_CTRL(CLKPWR_IOBASE),
+		.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART6_ENABLE
 	{
 		.uart_ck_name = "uart6_ck",
 		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 6),
-		.pdiv_clk_reg = CLKPWR_UART6_CLK_CTRL(CLKPWR_IOBASE),
+		.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
 };
@@ -144,7 +144,7 @@ void __init lpc32xx_serial_init(void)
 	int i;
 
 	/* UART clocks are off, let clock driver manage them */
-	__raw_writel(0, CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE));
+	__raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL(CLKPWR_IOBASE));
 
 	for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
 		clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
index aa06be8..1d35b34 100644
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -51,8 +51,9 @@ ENTRY(lpc32xx_sys_suspend)
 	ldr	CLKPWRBASE_REG, [WORK1_REG, #0]
 	ldr	EMCBASE_REG, [WORK1_REG, #4]
 
-	ldr	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
-	orr	WORK1_REG, SAVED_PWR_CTRL_REG, #CLKPWR_SDRAM_SELF_RFSH
+	ldr	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+		#LPC32XX_CLKPWR_PWR_CTRL(0)]
+	orr	WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
 
 	@ Wait for SDRAM busy status to go busy and then idle
 	@ This guarantees a small windows where DRAM isn't busy
@@ -69,10 +70,10 @@ ENTRY(lpc32xx_sys_suspend)
 
 	@ Setup self-refresh with support for manual exit of
 	@ self-refresh mode
-	str	WORK1_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
-	orr	WORK2_REG, WORK1_REG, #CLKPWR_UPD_SDRAM_SELF_RFSH
-	str	WORK2_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
-	str	WORK1_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	orr	WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
 
 	@ Wait for self-refresh acknowledge, clocks to the DRAM device
 	@ will automatically stop on start of self-refresh
@@ -83,23 +84,25 @@ ENTRY(lpc32xx_sys_suspend)
 	bne	3b @ Branch until self-refresh mode starts
 
 	@ Enter direct-run mode from run mode
-	bic	WORK1_REG, WORK1_REG, #CLKPWR_SELECT_RUN_MODE
-	str	WORK1_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
+	bic	WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
 
 	@ Safe disable of DRAM clock in EMC block, prevents DDR sync
 	@ issues on restart
-	ldr	SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG, #CLKPWR_HCLK_DIV(0)]
+	ldr	SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+		#LPC32XX_CLKPWR_HCLK_DIV(0)]
 	and	WORK2_REG, SAVED_HCLK_DIV_REG, #0xFFFFFE7F
-	str	WORK2_REG, [CLKPWRBASE_REG, #CLKPWR_HCLK_DIV(0)]
+	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV(0)]
 
 	@ Save HCLK PLL state and disable HCLK PLL
-	ldr	SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG, #CLKPWR_HCLKPLL_CTRL(0)]
-	bic	WORK2_REG, SAVED_HCLK_PLL_REG, #CLKPWR_HCLKPLL_POWER_UP
-	str	WORK2_REG, [CLKPWRBASE_REG, #CLKPWR_HCLKPLL_CTRL(0)]
+	ldr	SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+		#LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
+	bic	WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
+	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
 
 	@ Enter stop mode until an enabled event occurs
-	orr	WORK1_REG, WORK1_REG, #CLKPWR_STOP_MODE_CTRL
-	str	WORK1_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
+	orr	WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
 	nop
 	nop
 	nop
@@ -111,26 +114,31 @@ ENTRY(lpc32xx_sys_suspend)
 	nop
 
 	@ Clear stop status
-	bic	WORK1_REG, WORK1_REG, #CLKPWR_STOP_MODE_CTRL
+	bic	WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
 
 	@ Restore original HCLK PLL value and wait for PLL lock
-	str	SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG, #CLKPWR_HCLKPLL_CTRL(0)]
+	str	SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+		#LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
 4:
-	ldr	WORK2_REG, [CLKPWRBASE_REG, #CLKPWR_HCLKPLL_CTRL(0)]
-	and	WORK2_REG, WORK2_REG, #CLKPWR_HCLKPLL_PLL_STS
+	ldr	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
+	and	WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
 	bne	4b
 
 	@ Re-enter run mode with self-refresh flag cleared, but no DRAM
 	@ update yet. DRAM is still in self-refresh
-	str	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
+	str	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+		#LPC32XX_CLKPWR_PWR_CTRL(0)]
 
 	@ Restore original DRAM clock mode to restore DRAM clocks
-	str	SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG, #CLKPWR_HCLK_DIV(0)]
+	str	SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+		#LPC32XX_CLKPWR_HCLK_DIV(0)]
 
 	@ Clear self-refresh mode
-	orr	WORK1_REG, SAVED_PWR_CTRL_REG, #CLKPWR_UPD_SDRAM_SELF_RFSH
-	str	WORK1_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
-	str	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG, #CLKPWR_PWR_CTRL(0)]
+	orr	WORK1_REG, SAVED_PWR_CTRL_REG,\
+		#LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	str	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+		#LPC32XX_CLKPWR_PWR_CTRL(0)]
 
 	@ Wait for EMC to clear self-refresh mode
 5:
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index c5fa62d..35f58e2 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -132,9 +132,9 @@ static void __init lpc32xx_timer_init(void)
 	u32 clkrate, pllreg;
 
 	/* Enable timer clock */
-	writel(
-		(CLKPWR_TMRPWMCLK_TIMER0_EN | CLKPWR_TMRPWMCLK_TIMER1_EN),
-		CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE));
+	writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
+		LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
+		LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(CLKPWR_IOBASE));
 
 	/* The clock driver isn't initialized@this point. So determine if
 	   the SYSCLK is driven from the PLL397 or main oscillator and then use
@@ -146,7 +146,7 @@ static void __init lpc32xx_timer_init(void)
 		clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
 
 	/* Get ARM HCLKPLL register and convert it into a frequency*/
-	pllreg = readl(CLKPWR_HCLKPLL_CTRL(CLKPWR_IOBASE)) & 0x1FFFF;
+	pllreg = readl(LPC32XX_CLKPWR_HCLKPLL_CTRL(CLKPWR_IOBASE)) & 0x1FFFF;
 	clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
 
 	/* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 05/16] ARM: LPC32XX: Added LPC32XX identifier to INTC register field macros
       [not found] <LPC32XX architecture files (updated)>
                   ` (4 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 04/16] ARM: LPC32XX: Added LXP32XX identified to CLKPWR register field macros wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 06/16] ARM: LPC32XX: Added LPC32XX identifier to TIMER " wellsk40 at gmail.com
                   ` (10 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

The INTC macros and associated code have been updated with the
LPC32XX identifier.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/include/mach/entry-macro.S |    6 +-
 arch/arm/mach-lpc32xx/include/mach/platform.h    |   12 ++--
 arch/arm/mach-lpc32xx/irq.c                      |   69 +++++++++++-----------
 3 files changed, 44 insertions(+), 43 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index 01331f1..25f2adc 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -39,7 +39,7 @@
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	/* Get MIC status first */
 	ldr	\base, =IO_ADDRESS(LPC32XX_MIC_BASE)
-	ldr	\irqstat, [\base, #INTC_STAT]
+	ldr	\irqstat, [\base, #LPC32XX_INTC_STAT]
 	and	\irqstat, \irqstat, #0xFFFFFFFC
 	mov	\tmp, #0
 
@@ -49,7 +49,7 @@
 
 	/* SIC1 interrupts start at offset 32 */
 	ldr	\base, =IO_ADDRESS(LPC32XX_SIC1_BASE)
-	ldr	\irqstat, [\base, #INTC_STAT]
+	ldr	\irqstat, [\base, #LPC32XX_INTC_STAT]
 	mov	\tmp, #32
 
 	/* Drop through to SIC2 if SIC1 is not pending */
@@ -58,7 +58,7 @@
 
 	/* SIC2 interrupts start at offset 64 */
 	ldr	\base, =IO_ADDRESS(LPC32XX_SIC2_BASE)
-	ldr	\irqstat, [\base, #INTC_STAT]
+	ldr	\irqstat, [\base, #LPC32XX_INTC_STAT]
 	mov	\tmp, #64
 
 	/* Safety check only, exit if no status on MIC, SIC1, SIC2 */
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 7e9ade1..099db8a 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -588,12 +588,12 @@
 /*
  * Interrupt controller register offsets
  */
-#define INTC_MASK		0x00
-#define INTC_RAW_STAT		0x04
-#define INTC_STAT		0x08
-#define INTC_POLAR		0x0C
-#define INTC_ACT_TYPE		0x10
-#define INTC_TYPE		0x14
+#define LPC32XX_INTC_MASK			0x00
+#define LPC32XX_INTC_RAW_STAT			0x04
+#define LPC32XX_INTC_STAT			0x08
+#define LPC32XX_INTC_POLAR			0x0C
+#define LPC32XX_INTC_ACT_TYPE			0x10
+#define LPC32XX_INTC_TYPE			0x14
 
 /*
  *
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 3e45d32..3ac8b4d 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -68,9 +68,9 @@ static void lpc32xx_mask_irq(unsigned int irq)
 
 	get_controller(irq, &ctrl, &mask);
 
-	reg = readl(ctrl + INTC_MASK);
+	reg = readl(ctrl + LPC32XX_INTC_MASK);
 	reg &= ~mask;
-	writel(reg, (ctrl + INTC_MASK));
+	writel(reg, (ctrl + LPC32XX_INTC_MASK));
 }
 
 static void lpc32xx_unmask_irq(unsigned int irq)
@@ -79,9 +79,9 @@ static void lpc32xx_unmask_irq(unsigned int irq)
 
 	get_controller(irq, &ctrl, &mask);
 
-	reg = readl(ctrl + INTC_MASK);
+	reg = readl(ctrl + LPC32XX_INTC_MASK);
 	reg |= mask;
-	writel(reg, (ctrl + INTC_MASK));
+	writel(reg, (ctrl + LPC32XX_INTC_MASK));
 }
 
 static void lpc32xx_mask_ack_irq(unsigned int irq)
@@ -90,7 +90,7 @@ static void lpc32xx_mask_ack_irq(unsigned int irq)
 
 	get_controller(irq, &ctrl, &mask);
 
-	writel(mask, (ctrl + INTC_RAW_STAT));
+	writel(mask, (ctrl + LPC32XX_INTC_RAW_STAT));
 }
 
 static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
@@ -102,45 +102,45 @@ static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
 		/* Rising edge sensitive */
-		reg = readl(ctrl + INTC_POLAR);
+		reg = readl(ctrl + LPC32XX_INTC_POLAR);
 		reg |= mask;
-		writel(reg, (ctrl + INTC_POLAR));
-		reg = readl(ctrl + INTC_ACT_TYPE);
+		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
+		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
 		reg |= mask;
-		writel(reg, (ctrl + INTC_ACT_TYPE));
+		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
 		set_irq_handler(irq, handle_edge_irq);
 		break;
 
 	case IRQ_TYPE_EDGE_FALLING:
 		/* Falling edge sensitive */
-		reg = readl(ctrl + INTC_POLAR);
+		reg = readl(ctrl + LPC32XX_INTC_POLAR);
 		reg &= ~mask;
-		writel(reg, (ctrl + INTC_POLAR));
-		reg = readl(ctrl + INTC_ACT_TYPE);
+		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
+		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
 		reg |= mask;
-		writel(reg, (ctrl + INTC_ACT_TYPE));
+		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
 		set_irq_handler(irq, handle_edge_irq);
 		break;
 
 	case IRQ_TYPE_LEVEL_LOW:
 		/* Low level sensitive */
-		reg = readl(ctrl + INTC_POLAR);
+		reg = readl(ctrl + LPC32XX_INTC_POLAR);
 		reg &= ~mask;
-		writel(reg, (ctrl + INTC_POLAR));
-		reg = readl(ctrl + INTC_ACT_TYPE);
+		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
+		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
 		reg &= ~mask;
-		writel(reg, (ctrl + INTC_ACT_TYPE));
+		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
 		set_irq_handler(irq, handle_level_irq);
 		break;
 
 	case IRQ_TYPE_LEVEL_HIGH:
 		/* High level sensitive */
-		reg = readl(ctrl + INTC_POLAR);
+		reg = readl(ctrl + LPC32XX_INTC_POLAR);
 		reg |= mask;
-		writel(reg, (ctrl + INTC_POLAR));
-		reg = readl(ctrl + INTC_ACT_TYPE);
+		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
+		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
 		reg &= ~mask;
-		writel(reg, (ctrl + INTC_ACT_TYPE));
+		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
 		set_irq_handler(irq, handle_level_irq);
 		break;
 
@@ -198,21 +198,21 @@ void __init lpc32xx_init_irq(void)
 
 	/* Setup MIC */
 	vloc = io_p2v(LPC32XX_MIC_BASE);
-	writel(0, (vloc + INTC_MASK));
-	writel(MIC_APR_DEFAULT, (vloc + INTC_POLAR));
-	writel(MIC_ATR_DEFAULT, (vloc + INTC_ACT_TYPE));
+	writel(0, (vloc + LPC32XX_INTC_MASK));
+	writel(MIC_APR_DEFAULT, (vloc + LPC32XX_INTC_POLAR));
+	writel(MIC_ATR_DEFAULT, (vloc + LPC32XX_INTC_ACT_TYPE));
 
 	/* Setup SIC1 */
 	vloc = io_p2v(LPC32XX_SIC1_BASE);
-	writel(0, (vloc + INTC_MASK));
-	writel(SIC1_APR_DEFAULT, (vloc + INTC_POLAR));
-	writel(SIC1_ATR_DEFAULT, (vloc + INTC_ACT_TYPE));
+	writel(0, (vloc + LPC32XX_INTC_MASK));
+	writel(SIC1_APR_DEFAULT, (vloc + LPC32XX_INTC_POLAR));
+	writel(SIC1_ATR_DEFAULT, (vloc + LPC32XX_INTC_ACT_TYPE));
 
 	/* Setup SIC2 */
 	vloc = io_p2v(LPC32XX_SIC2_BASE);
-	writel(0, (vloc + INTC_MASK));
-	writel(SIC2_APR_DEFAULT, (vloc + INTC_POLAR));
-	writel(SIC2_ATR_DEFAULT, (vloc + INTC_ACT_TYPE));
+	writel(0, (vloc + LPC32XX_INTC_MASK));
+	writel(SIC2_APR_DEFAULT, (vloc + LPC32XX_INTC_POLAR));
+	writel(SIC2_ATR_DEFAULT, (vloc + LPC32XX_INTC_ACT_TYPE));
 
 	/* Configure supported IRQ's */
 	for (i = 0; i < NR_IRQS; i++) {
@@ -229,8 +229,9 @@ void __init lpc32xx_init_irq(void)
 		SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
 
 	/* mask all interrupts except SUBIRQA and SUBFIQ */
-	writel((1 << IRQ_SUB1IRQ) | (1 << IRQ_SUB2IRQ) | (1 << IRQ_SUB1FIQ) |
-		(1 << IRQ_SUB2FIQ), (io_p2v(LPC32XX_MIC_BASE) + INTC_MASK));
-	writel(0, (io_p2v(LPC32XX_SIC1_BASE) + INTC_MASK));
-	writel(0, (io_p2v(LPC32XX_SIC2_BASE) + INTC_MASK));
+	writel((1 << IRQ_SUB1IRQ) | (1 << IRQ_SUB2IRQ) |
+		(1 << IRQ_SUB1FIQ) | (1 << IRQ_SUB2FIQ),
+		(io_p2v(LPC32XX_MIC_BASE) + LPC32XX_INTC_MASK));
+	writel(0, (io_p2v(LPC32XX_SIC1_BASE) + LPC32XX_INTC_MASK));
+	writel(0, (io_p2v(LPC32XX_SIC2_BASE) + LPC32XX_INTC_MASK));
 }
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 06/16] ARM: LPC32XX: Added LPC32XX identifier to TIMER register field macros
       [not found] <LPC32XX architecture files (updated)>
                   ` (5 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 05/16] ARM: LPC32XX: Added LPC32XX identifier to INTC " wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 07/16] ARM: LPC32XX: Added LPC32XX identifier to UART " wellsk40 at gmail.com
                   ` (9 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

The TIMER macros and associated code have been updated with the
LPC32XX identifier.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/include/mach/platform.h |   48 ++++++++++++------------
 arch/arm/mach-lpc32xx/timer.c                 |   34 ++++++++++--------
 2 files changed, 43 insertions(+), 39 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 099db8a..1ee148c 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -600,42 +600,42 @@
  * Timer/counter register offsets
  *
  */
-#define TIMER_IR(x)			((x) + 0x00)
-#define TIMER_TCR(x)			((x) + 0x04)
-#define TIMER_TC(x)			((x) + 0x08)
-#define TIMER_PR(x)			((x) + 0x0C)
-#define TIMER_PC(x)			((x) + 0x10)
-#define TIMER_MCR(x)			((x) + 0x14)
-#define TIMER_MR0(x)			((x) + 0x18)
-#define TIMER_MR1(x)			((x) + 0x1C)
-#define TIMER_MR2(x)			((x) + 0x20)
-#define TIMER_MR3(x)			((x) + 0x24)
-#define TIMER_CCR(x)			((x) + 0x28)
-#define TIMER_CR0(x)			((x) + 0x2C)
-#define TIMER_CR1(x)			((x) + 0x30)
-#define TIMER_CR2(x)			((x) + 0x34)
-#define TIMER_CR3(x)			((x) + 0x38)
-#define TIMER_EMR(x)			((x) + 0x3C)
-#define TIMER_CTCR(x)			((x) + 0x70)
+#define LCP32XX_TIMER_IR(x)			((x) + 0x00)
+#define LCP32XX_TIMER_TCR(x)			((x) + 0x04)
+#define LCP32XX_TIMER_TC(x)			((x) + 0x08)
+#define LCP32XX_TIMER_PR(x)			((x) + 0x0C)
+#define LCP32XX_TIMER_PC(x)			((x) + 0x10)
+#define LCP32XX_TIMER_MCR(x)			((x) + 0x14)
+#define LCP32XX_TIMER_MR0(x)			((x) + 0x18)
+#define LCP32XX_TIMER_MR1(x)			((x) + 0x1C)
+#define LCP32XX_TIMER_MR2(x)			((x) + 0x20)
+#define LCP32XX_TIMER_MR3(x)			((x) + 0x24)
+#define LCP32XX_TIMER_CCR(x)			((x) + 0x28)
+#define LCP32XX_TIMER_CR0(x)			((x) + 0x2C)
+#define LCP32XX_TIMER_CR1(x)			((x) + 0x30)
+#define LCP32XX_TIMER_CR2(x)			((x) + 0x34)
+#define LCP32XX_TIMER_CR3(x)			((x) + 0x38)
+#define LCP32XX_TIMER_EMR(x)			((x) + 0x3C)
+#define LCP32XX_TIMER_CTCR(x)			((x) + 0x70)
 
 /*
  * ir register definitions
  */
-#define TIMER_CNTR_MTCH_BIT(n)		(1 << ((n) & 0x3))
-#define TIMER_CNTR_CAPT_BIT(n)		(1 << (4 + ((n) & 0x3)))
+#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)		(1 << ((n) & 0x3))
+#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)		(1 << (4 + ((n) & 0x3)))
 
 /*
  * tcr register definitions
  */
-#define TIMER_CNTR_TCR_EN		0x1
-#define TIMER_CNTR_TCR_RESET		0x2
+#define LCP32XX_TIMER_CNTR_TCR_EN		0x1
+#define LCP32XX_TIMER_CNTR_TCR_RESET		0x2
 
 /*
  * mcr register definitions
  */
-#define TIMER_CNTR_MCR_MTCH(n)		(0x1 << ((n) * 3))
-#define TIMER_CNTR_MCR_RESET(n)		(0x1 << (((n) * 3) + 1))
-#define TIMER_CNTR_MCR_STOP(n)		(0x1 << (((n) * 3) + 2))
+#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)		(0x1 << ((n) * 3))
+#define LCP32XX_TIMER_CNTR_MCR_RESET(n)		(0x1 << (((n) * 3) + 1))
+#define LCP32XX_TIMER_CNTR_MCR_STOP(n)		(0x1 << (((n) * 3) + 2))
 
 /*
  *
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 35f58e2..cd79017 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -40,7 +40,7 @@
 
 static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
 {
-	return (cycle_t)readl(TIMER_TC(TIMER1_IOBASE));
+	return (cycle_t)readl(LCP32XX_TIMER_TC(TIMER1_IOBASE));
 }
 
 static struct clocksource lpc32xx_clksrc = {
@@ -62,9 +62,9 @@ static int lpc32xx_clkevt_next_event(unsigned long delta,
 
 	local_irq_save(flags);
 
-	writel(TIMER_CNTR_TCR_RESET, TIMER_TCR(TIMER0_IOBASE));
-	writel(delta, TIMER_PR(TIMER0_IOBASE));
-	writel(TIMER_CNTR_TCR_EN, TIMER_TCR(TIMER0_IOBASE));
+	writel(LCP32XX_TIMER_CNTR_TCR_RESET, LCP32XX_TIMER_TCR(TIMER0_IOBASE));
+	writel(delta, LCP32XX_TIMER_PR(TIMER0_IOBASE));
+	writel(LCP32XX_TIMER_CNTR_TCR_EN, LCP32XX_TIMER_TCR(TIMER0_IOBASE));
 
 	local_irq_restore(flags);
 
@@ -86,7 +86,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
 		 * disable the timer to wait for the first call to
 		 * set_next_event().
 		 */
-		writel(0, TIMER_TCR(TIMER0_IOBASE));
+		writel(0, LCP32XX_TIMER_TCR(TIMER0_IOBASE));
 		break;
 
 	case CLOCK_EVT_MODE_UNUSED:
@@ -109,7 +109,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
 	struct clock_event_device *evt = &lpc32xx_clkevt;
 
 	/* Clear match */
-	writel(TIMER_CNTR_MTCH_BIT(0), TIMER_IR(TIMER0_IOBASE));
+	writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+		LCP32XX_TIMER_IR(TIMER0_IOBASE));
 
 	evt->event_handler(evt);
 
@@ -153,11 +154,14 @@ static void __init lpc32xx_timer_init(void)
 	clkrate = clkrate / clk_get_pclk_div();
 
 	/* Initial timer setup */
-	writel(0, TIMER_TCR(TIMER0_IOBASE));
-	writel(TIMER_CNTR_MTCH_BIT(0), TIMER_IR(TIMER0_IOBASE));
-	writel(1, TIMER_MR0(TIMER0_IOBASE));
-	writel(TIMER_CNTR_MCR_MTCH(0) | TIMER_CNTR_MCR_STOP(0) |
-	    TIMER_CNTR_MCR_RESET(0), TIMER_MCR(TIMER0_IOBASE));
+	writel(0, LCP32XX_TIMER_TCR(TIMER0_IOBASE));
+	writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+		LCP32XX_TIMER_IR(TIMER0_IOBASE));
+	writel(1, LCP32XX_TIMER_MR0(TIMER0_IOBASE));
+	writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
+		LCP32XX_TIMER_CNTR_MCR_STOP(0) |
+		LCP32XX_TIMER_CNTR_MCR_RESET(0),
+		LCP32XX_TIMER_MCR(TIMER0_IOBASE));
 
 	/* Setup tick interrupt */
 	setup_irq(IRQ_TIMER0, &lpc32xx_timer_irq);
@@ -172,10 +176,10 @@ static void __init lpc32xx_timer_init(void)
 	clockevents_register_device(&lpc32xx_clkevt);
 
 	/* Use timer1 as clock source. */
-	writel(TIMER_CNTR_TCR_RESET, TIMER_TCR(TIMER1_IOBASE));
-	writel(0, TIMER_PR(TIMER1_IOBASE));
-	writel(0, TIMER_MCR(TIMER1_IOBASE));
-	writel(TIMER_CNTR_TCR_EN, TIMER_TCR(TIMER1_IOBASE));
+	writel(LCP32XX_TIMER_CNTR_TCR_RESET, LCP32XX_TIMER_TCR(TIMER1_IOBASE));
+	writel(0, LCP32XX_TIMER_PR(TIMER1_IOBASE));
+	writel(0, LCP32XX_TIMER_MCR(TIMER1_IOBASE));
+	writel(LCP32XX_TIMER_CNTR_TCR_EN, LCP32XX_TIMER_TCR(TIMER1_IOBASE));
 	lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
 		lpc32xx_clksrc.shift);
 	clocksource_register(&lpc32xx_clksrc);
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 07/16] ARM: LPC32XX: Added LPC32XX identifier to UART register field macros
       [not found] <LPC32XX architecture files (updated)>
                   ` (6 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 06/16] ARM: LPC32XX: Added LPC32XX identifier to TIMER " wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 08/16] ARM: LPC32XX: Added LPC32XX identifier to GPIO " wellsk40 at gmail.com
                   ` (8 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

The UART macros and associated code have been updated with the
LPC32XX identifier.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/include/mach/platform.h |   56 ++++++++++++------------
 arch/arm/mach-lpc32xx/serial.c                |   37 +++++++++-------
 2 files changed, 49 insertions(+), 44 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 1ee148c..9de37ee 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -642,48 +642,48 @@
  * Standard UART register offsets
  *
  */
-#define UART_DLL_FIFO(x)		((x) + 0x00)
-#define UART_DLM_IER(x)			((x) + 0x04)
-#define UART_IIR_FCR(x)			((x) + 0x08)
-#define UART_LCR_(x)			((x) + 0x0C)
-#define UART_MODEM_CTRL(x)		((x) + 0x10)
-#define UART_LSR_(x)			((x) + 0x14)
-#define UART_MODEM_STATUS(x)		((x) + 0x18)
-#define UART_RXLEV(x)			((x) + 0x1C)
+#define LPC32XX_UART_DLL_FIFO(x)		((x) + 0x00)
+#define LPC32XX_UART_DLM_IER(x)			((x) + 0x04)
+#define LPC32XX_UART_IIR_FCR(x)			((x) + 0x08)
+#define LPC32XX_UART_LCR_(x)			((x) + 0x0C)
+#define LPC32XX_UART_MODEM_CTRL(x)		((x) + 0x10)
+#define LPC32XX_UART_LSR_(x)			((x) + 0x14)
+#define LPC32XX_UART_MODEM_STATUS(x)		((x) + 0x18)
+#define LPC32XX_UART_RXLEV(x)			((x) + 0x1C)
 
 /*
  *
  * UART control structure offsets
  *
  */
-#define UARTCTL_CTRL(x)			((x) + 0x00)
-#define UARTCTL_CLKMODE(x)		((x) + 0x04)
-#define UARTCTL_CLOOP(x)		((x) + 0x08)
+#define LPC32XX_UARTCTL_CTRL(x)			((x) + 0x00)
+#define LPC32XX_UARTCTL_CLKMODE(x)		((x) + 0x04)
+#define LPC32XX_UARTCTL_CLOOP(x)		((x) + 0x08)
 
 /*
  * ctrl register definitions
  */
-#define UART_U3_MD_CTRL_EN		_BIT(11)
-#define UART_IRRX6_INV_EN		_BIT(10)
-#define UART_HDPX_EN			_BIT(9)
-#define UART_UART6_IRDAMOD_BYPASS	_BIT(5)
-#define RT_IRTX6_INV_EN			_BIT(4)
-#define RT_IRTX6_INV_MIR_EN		_BIT(3)
-#define RT_RX_IRPULSE_3_16_115K		_BIT(2)
-#define RT_TX_IRPULSE_3_16_115K		_BIT(1)
-#define UART_U5_ROUTE_TO_USB		_BIT(0)
+#define LPC32XX_UART_U3_MD_CTRL_EN		_BIT(11)
+#define LPC32XX_UART_IRRX6_INV_EN		_BIT(10)
+#define LPC32XX_UART_HDPX_EN			_BIT(9)
+#define LPC32XX_UART_UART6_IRDAMOD_BYPASS	_BIT(5)
+#define LPC32XX_RT_IRTX6_INV_EN			_BIT(4)
+#define LPC32XX_RT_IRTX6_INV_MIR_EN		_BIT(3)
+#define LPC32XX_RT_RX_IRPULSE_3_16_115K		_BIT(2)
+#define LPC32XX_RT_TX_IRPULSE_3_16_115K		_BIT(1)
+#define LPC32XX_UART_U5_ROUTE_TO_USB		_BIT(0)
 
 /*
  * clkmode register definitions
  */
-#define UART_ENABLED_CLOCKS(n)		(((n) >> 16) & 0x7F)
-#define UART_ENABLED_CLOCK(n, u)	(((n) >> (16 + (u))) & 0x1)
-#define UART_ENABLED_CLKS_ANY		_BIT(14)
-#define UART_CLKMODE_OFF		0x0
-#define UART_CLKMODE_ON			0x1
-#define UART_CLKMODE_AUTO		0x2
-#define UART_CLKMODE_MASK(u)		(0x3 << ((((u) - 3) * 2) + 4))
-#define UART_CLKMODE_LOAD(m, u)		((m) << ((((u) - 3) * 2) + 4))
+#define LPC32XX_UART_ENABLED_CLOCKS(n)		(((n) >> 16) & 0x7F)
+#define LPC32XX_UART_ENABLED_CLOCK(n, u)	(((n) >> (16 + (u))) & 0x1)
+#define LPC32XX_UART_ENABLED_CLKS_ANY		_BIT(14)
+#define LPC32XX_UART_CLKMODE_OFF		0x0
+#define LPC32XX_UART_CLKMODE_ON			0x1
+#define LPC32XX_UART_CLKMODE_AUTO		0x2
+#define LPC32XX_UART_CLKMODE_MASK(u)		(0x3 << ((((u) - 3) * 2) + 4))
+#define LPC32XX_UART_CLKMODE_LOAD(m, u)		((m) << ((((u) - 3) * 2) + 4))
 
 /*
  *
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index def5003..3a0acfd 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -97,28 +97,32 @@ static struct uartinit uartinit_data[] __initdata = {
 #ifdef CONFIG_ARCH_LPC32XX_UART5_ENABLE
 	{
 		.uart_ck_name = "uart5_ck",
-		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 5),
+		.ck_mode_mask =
+			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
 		.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART3_ENABLE
 	{
 		.uart_ck_name = "uart3_ck",
-		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 3),
+		.ck_mode_mask =
+			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
 		.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART4_ENABLE
 	{
 		.uart_ck_name = "uart4_ck",
-		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 4),
+		.ck_mode_mask =
+			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
 		.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART6_ENABLE
 	{
 		.uart_ck_name = "uart6_ck",
-		.ck_mode_mask = UART_CLKMODE_LOAD(UART_CLKMODE_ON, 6),
+		.ck_mode_mask =
+			LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
 		.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL(CLKPWR_IOBASE),
 	},
 #endif
@@ -169,31 +173,32 @@ void __init lpc32xx_serial_init(void)
 	}
 
 	/* This needs to be done after all UART clocks are setup */
-	writel(clkmodes, UARTCTL_CLKMODE(io_p2v(LPC32XX_UART_CTRL_BASE)));
+	writel(clkmodes,
+		LPC32XX_UARTCTL_CLKMODE(io_p2v(LPC32XX_UART_CTRL_BASE)));
 	for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
 		/* Force a flush of the RX FIFOs to work around a HW bug */
 		puart = serial_std_platform_data[i].membase;
-		writel(0xC1, UART_IIR_FCR(puart));
-		writel(0x00, UART_DLL_FIFO(puart));
+		writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
+		writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
 		clkmodes = 64;
 		while (clkmodes--)
-			tmp = readl(UART_DLL_FIFO(puart));
-		writel(0, UART_IIR_FCR(puart));
+			tmp = readl(LPC32XX_UART_DLL_FIFO(puart));
+		writel(0, LPC32XX_UART_IIR_FCR(puart));
 	}
 
 	/* IrDA pulsing support on UART6. This only enables the IrDA mux */
-	tmp = readl(UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
+	tmp = readl(LPC32XX_UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
 #ifdef CONFIG_ARCH_LPC32XX_UART6_IRDAMODE
-	tmp &= ~UART_UART6_IRDAMOD_BYPASS;
+	tmp &= ~LPC32XX_UART_UART6_IRDAMOD_BYPASS;
 #else
-	tmp |= UART_UART6_IRDAMOD_BYPASS;
+	tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
 #endif
-	writel(tmp, UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
+	writel(tmp, LPC32XX_UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
 
 	/* Disable UART5->USB transparent mode or USB won't work */
-	tmp = readl(UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
-	tmp &= ~UART_U5_ROUTE_TO_USB;
-	writel(tmp, UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
+	tmp = readl(LPC32XX_UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
+	tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
+	writel(tmp, LPC32XX_UARTCTL_CTRL(io_p2v(LPC32XX_UART_CTRL_BASE)));
 
 	platform_add_devices(lpc32xx_serial_devs,
 		ARRAY_SIZE(lpc32xx_serial_devs));
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 08/16] ARM: LPC32XX: Added LPC32XX identifier to GPIO register field macros
       [not found] <LPC32XX architecture files (updated)>
                   ` (7 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 07/16] ARM: LPC32XX: Added LPC32XX identifier to UART " wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 09/16] ARM: LPC32XX: LPC32XX macro name changes and local macro use wellsk40 at gmail.com
                   ` (7 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

The GPIO macros and associated code have been updated with the
LPC32XX identifier.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/gpiolib.c               |   96 +++++++++++++++----------
 arch/arm/mach-lpc32xx/include/mach/gpio.h     |   26 ++++----
 arch/arm/mach-lpc32xx/include/mach/platform.h |   78 ++++++++++----------
 arch/arm/mach-lpc32xx/phy3250.c               |    8 +-
 4 files changed, 114 insertions(+), 94 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
index 803c48f..beed7eb 100644
--- a/arch/arm/mach-lpc32xx/gpiolib.c
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -42,12 +42,12 @@ struct gpio_regs {
 /*
  * GPIO names
  */
-static char *gpio_p0_names[GPIO_P0_MAX] = {
+static char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
 	"p0.0", "p0.1", "p0.2", "p0.3",
 	"p0.4", "p0.5", "p0.6", "p0.7"
 };
 
-static char *gpio_p1_names[GPIO_P1_MAX] = {
+static char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
 	"p1.0", "p1.1", "p1.2", "p1.3",
 	"p1.4", "p1.5", "p1.6", "p1.7",
 	"p1.8", "p1.9", "p1.10", "p1.11",
@@ -56,19 +56,19 @@ static char *gpio_p1_names[GPIO_P1_MAX] = {
 	"p1.20", "p1.21", "p1.22", "p1.23",
 };
 
-static char *gpio_p2_names[GPIO_P2_MAX] = {
+static char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
 	"p2.0", "p2.1", "p2.2", "p2.3",
 	"p2.4", "p2.5", "p2.6", "p2.7",
 	"p2.8", "p2.9", "p2.10", "p2.11",
 	"p2.12"
 };
 
-static char *gpio_p3_names[GPIO_P3_MAX] = {
+static char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
 	"gpi000", "gpio01", "gpio02", "gpio03",
 	"gpio04", "gpio05"
 };
 
-static char *gpi_p3_names[GPI_P3_MAX] = {
+static char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
 	"gpi00", "gpi01", "gpi02", "gpi03",
 	"gpi04", "gpi05", "gpi06", "gpi07",
 	"gpi08", "gpi09", "na",    "na",
@@ -78,7 +78,7 @@ static char *gpi_p3_names[GPI_P3_MAX] = {
 	"gpi24", "gpi25", "gpi26", "gpi27"
 };
 
-static char *gpo_p3_names[GPO_P3_MAX] = {
+static char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
 	"gpo00", "gpo01", "gpo02", "gpo03",
 	"gpo04", "gpo05", "gpo06", "gpo07",
 	"gpo08", "gpo09", "gpo10", "gpo11",
@@ -89,32 +89,52 @@ static char *gpo_p3_names[GPO_P3_MAX] = {
 
 static struct gpio_regs gpio_grp_regs[] = {
 	{
-		.inp_state	= (void __iomem *) GPIO_P0_INP_STATE(GPIOBASE),
-		.outp_set	= (void __iomem *) GPIO_P0_OUTP_SET(GPIOBASE),
-		.outp_clr	= (void __iomem *) GPIO_P0_OUTP_CLR(GPIOBASE),
-		.dir_set	= (void __iomem *) GPIO_P0_DIR_SET(GPIOBASE),
-		.dir_clr	= (void __iomem *) GPIO_P0_DIR_CLR(GPIOBASE),
+		.inp_state	=
+			(void __iomem *) LPC32XX_GPIO_P0_INP_STATE(GPIOBASE),
+		.outp_set	=
+			(void __iomem *) LPC32XX_GPIO_P0_OUTP_SET(GPIOBASE),
+		.outp_clr	=
+			(void __iomem *) LPC32XX_GPIO_P0_OUTP_CLR(GPIOBASE),
+		.dir_set	=
+			(void __iomem *) LPC32XX_GPIO_P0_DIR_SET(GPIOBASE),
+		.dir_clr	=
+			(void __iomem *) LPC32XX_GPIO_P0_DIR_CLR(GPIOBASE),
 	},
 	{
-		.inp_state	= (void __iomem *) GPIO_P1_INP_STATE(GPIOBASE),
-		.outp_set	= (void __iomem *) GPIO_P1_OUTP_SET(GPIOBASE),
-		.outp_clr	= (void __iomem *) GPIO_P1_OUTP_CLR(GPIOBASE),
-		.dir_set	= (void __iomem *) GPIO_P1_DIR_SET(GPIOBASE),
-		.dir_clr	= (void __iomem *) GPIO_P1_DIR_CLR(GPIOBASE),
+		.inp_state	=
+			(void __iomem *) LPC32XX_GPIO_P1_INP_STATE(GPIOBASE),
+		.outp_set	=
+			(void __iomem *) LPC32XX_GPIO_P1_OUTP_SET(GPIOBASE),
+		.outp_clr	=
+			(void __iomem *) LPC32XX_GPIO_P1_OUTP_CLR(GPIOBASE),
+		.dir_set	=
+			(void __iomem *) LPC32XX_GPIO_P1_DIR_SET(GPIOBASE),
+		.dir_clr	=
+			(void __iomem *) LPC32XX_GPIO_P1_DIR_CLR(GPIOBASE),
 	},
 	{
-		.inp_state	= (void __iomem *) GPIO_P2_INP_STATE(GPIOBASE),
-		.outp_set	= (void __iomem *) GPIO_P2_OUTP_SET(GPIOBASE),
-		.outp_clr	= (void __iomem *) GPIO_P2_OUTP_CLR(GPIOBASE),
-		.dir_set	= (void __iomem *) GPIO_P2_DIR_SET(GPIOBASE),
-		.dir_clr	= (void __iomem *) GPIO_P2_DIR_CLR(GPIOBASE),
+		.inp_state	=
+			(void __iomem *) LPC32XX_GPIO_P2_INP_STATE(GPIOBASE),
+		.outp_set	=
+			(void __iomem *) LPC32XX_GPIO_P2_OUTP_SET(GPIOBASE),
+		.outp_clr	=
+			(void __iomem *) LPC32XX_GPIO_P2_OUTP_CLR(GPIOBASE),
+		.dir_set	=
+			(void __iomem *) LPC32XX_GPIO_P2_DIR_SET(GPIOBASE),
+		.dir_clr	=
+			(void __iomem *) LPC32XX_GPIO_P2_DIR_CLR(GPIOBASE),
 	},
 	{
-		.inp_state	= (void __iomem *) GPIO_P3_INP_STATE(GPIOBASE),
-		.outp_set	= (void __iomem *) GPIO_P3_OUTP_SET(GPIOBASE),
-		.outp_clr	= (void __iomem *) GPIO_P3_OUTP_CLR(GPIOBASE),
-		.dir_set	= (void __iomem *) GPIO_P2_DIR_SET(GPIOBASE),
-		.dir_clr	= (void __iomem *) GPIO_P2_DIR_CLR(GPIOBASE),
+		.inp_state	=
+			(void __iomem *) LPC32XX_GPIO_P3_INP_STATE(GPIOBASE),
+		.outp_set	=
+			(void __iomem *) LPC32XX_GPIO_P3_OUTP_SET(GPIOBASE),
+		.outp_clr	=
+			(void __iomem *) LPC32XX_GPIO_P3_OUTP_CLR(GPIOBASE),
+		.dir_set	=
+			(void __iomem *) LPC32XX_GPIO_P2_DIR_SET(GPIOBASE),
+		.dir_clr	=
+			(void __iomem *) LPC32XX_GPIO_P2_DIR_CLR(GPIOBASE),
 	},
 };
 
@@ -329,8 +349,8 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 			.direction_output	= lpc32xx_gpio_dir_output_p012,
 			.set			= lpc32xx_gpio_set_value_p012,
 			.request		= lpc32xx_gpio_request,
-			.base			= GPIO_P0_GRP,
-			.ngpio			= GPIO_P0_MAX,
+			.base			= LPC32XX_GPIO_P0_GRP,
+			.ngpio			= LPC32XX_GPIO_P0_MAX,
 			.names			= gpio_p0_names,
 			.can_sleep		= 0,
 		},
@@ -344,8 +364,8 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 			.direction_output	= lpc32xx_gpio_dir_output_p012,
 			.set			= lpc32xx_gpio_set_value_p012,
 			.request		= lpc32xx_gpio_request,
-			.base			= GPIO_P1_GRP,
-			.ngpio			= GPIO_P1_MAX,
+			.base			= LPC32XX_GPIO_P1_GRP,
+			.ngpio			= LPC32XX_GPIO_P1_MAX,
 			.names			= gpio_p1_names,
 			.can_sleep		= 0,
 		},
@@ -359,8 +379,8 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 			.direction_output	= lpc32xx_gpio_dir_output_p012,
 			.set			= lpc32xx_gpio_set_value_p012,
 			.request		= lpc32xx_gpio_request,
-			.base			= GPIO_P2_GRP,
-			.ngpio			= GPIO_P2_MAX,
+			.base			= LPC32XX_GPIO_P2_GRP,
+			.ngpio			= LPC32XX_GPIO_P2_MAX,
 			.names			= gpio_p2_names,
 			.can_sleep		= 0,
 		},
@@ -374,8 +394,8 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 			.direction_output	= lpc32xx_gpio_dir_output_p3,
 			.set			= lpc32xx_gpio_set_value_p3,
 			.request		= lpc32xx_gpio_request,
-			.base			= GPIO_P3_GRP,
-			.ngpio			= GPIO_P3_MAX,
+			.base			= LPC32XX_GPIO_P3_GRP,
+			.ngpio			= LPC32XX_GPIO_P3_MAX,
 			.names			= gpio_p3_names,
 			.can_sleep		= 0,
 		},
@@ -387,8 +407,8 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 			.direction_input	= lpc32xx_gpio_dir_in_always,
 			.get			= lpc32xx_gpi_get_value,
 			.request		= lpc32xx_gpio_request,
-			.base			= GPI_P3_GRP,
-			.ngpio			= GPI_P3_MAX,
+			.base			= LPC32XX_GPI_P3_GRP,
+			.ngpio			= LPC32XX_GPI_P3_MAX,
 			.names			= gpi_p3_names,
 			.can_sleep		= 0,
 		},
@@ -400,8 +420,8 @@ static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
 			.direction_output	= lpc32xx_gpio_dir_out_always,
 			.set			= lpc32xx_gpo_set_value,
 			.request		= lpc32xx_gpio_request,
-			.base			= GPO_P3_GRP,
-			.ngpio			= GPO_P3_MAX,
+			.base			= LPC32XX_GPO_P3_GRP,
+			.ngpio			= LPC32XX_GPO_P3_MAX,
 			.names			= gpo_p3_names,
 			.can_sleep		= 0,
 		},
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
index 8df2198..e95b113 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -34,23 +34,23 @@
  * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
  */
 
-#define GPIO_P0_MAX 8
-#define GPIO_P1_MAX 24
-#define GPIO_P2_MAX 13
-#define GPIO_P3_MAX 6
-#define GPI_P3_MAX 28
-#define GPO_P3_MAX 24
+#define LPC32XX_GPIO_P0_MAX 8
+#define LPC32XX_GPIO_P1_MAX 24
+#define LPC32XX_GPIO_P2_MAX 13
+#define LPC32XX_GPIO_P3_MAX 6
+#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPO_P3_MAX 24
 
-#define GPIO_P0_GRP 0
-#define GPIO_P1_GRP (GPIO_P0_GRP + GPIO_P0_MAX)
-#define GPIO_P2_GRP (GPIO_P1_GRP + GPIO_P1_MAX)
-#define GPIO_P3_GRP (GPIO_P2_GRP + GPIO_P2_MAX)
-#define GPI_P3_GRP (GPIO_P3_GRP + GPIO_P3_MAX)
-#define GPO_P3_GRP (GPI_P3_GRP + GPI_P3_MAX)
+#define LPC32XX_GPIO_P0_GRP 0
+#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
+#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
+#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
+#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
+#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
 
 /*
  * A specific GPIO can be selected with this macro
- * ie, GPIO_05 can be selected with LPC32XX_GPIO(GPIO_P3_GRP, 5)
+ * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
  * See the LPC32x0 User's guide for GPIO group numbers
  */
 #define LPC32XX_GPIO(x, y) ((x) + (y))
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 9de37ee..adc932b 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -690,44 +690,44 @@
  * GPIO Module Register offsets
  *
  */
-#define GPIO_P3_INP_STATE(x)		((x) + 0x000)
-#define GPIO_P3_OUTP_SET(x)		((x) + 0x004)
-#define GPIO_P3_OUTP_CLR(x)		((x) + 0x008)
-#define GPIO_P3_OUTP_STATE(x)		((x) + 0x00C)
-#define GPIO_P2_DIR_SET(x)		((x) + 0x010)
-#define GPIO_P2_DIR_CLR(x)		((x) + 0x014)
-#define GPIO_P2_DIR_STATE(x)		((x) + 0x018)
-#define GPIO_P2_INP_STATE(x)		((x) + 0x01C)
-#define GPIO_P2_OUTP_SET(x)		((x) + 0x020)
-#define GPIO_P2_OUTP_CLR(x)		((x) + 0x024)
-#define GPIO_P2_MUX_SET(x)		((x) + 0x028)
-#define GPIO_P2_MUX_CLR(x)		((x) + 0x02C)
-#define GPIO_P2_MUX_STATE(x)		((x) + 0x030)
-#define GPIO_P0_INP_STATE(x)		((x) + 0x040)
-#define GPIO_P0_OUTP_SET(x)		((x) + 0x044)
-#define GPIO_P0_OUTP_CLR(x)		((x) + 0x048)
-#define GPIO_P0_OUTP_STATE(x)		((x) + 0x04C)
-#define GPIO_P0_DIR_SET(x)		((x) + 0x050)
-#define GPIO_P0_DIR_CLR(x)		((x) + 0x054)
-#define GPIO_P0_DIR_STATE(x)		((x) + 0x058)
-#define GPIO_P1_INP_STATE(x)		((x) + 0x060)
-#define GPIO_P1_OUTP_SET(x)		((x) + 0x064)
-#define GPIO_P1_OUTP_CLR(x)		((x) + 0x068)
-#define GPIO_P1_OUTP_STATE(x)		((x) + 0x06C)
-#define GPIO_P1_DIR_SET(x)		((x) + 0x070)
-#define GPIO_P1_DIR_CLR(x)		((x) + 0x074)
-#define GPIO_P1_DIR_STATE(x)		((x) + 0x078)
-#define GPIO_P_MUX_SET(x)		((x) + 0x100)
-#define GPIO_P_MUX_CLR(x)		((x) + 0x104)
-#define GPIO_P_MUX_STATE(x)		((x) + 0x108)
-#define GPIO_P3_MUX_SET(x)		((x) + 0x110)
-#define GPIO_P3_MUX_CLR(x)		((x) + 0x114)
-#define GPIO_P3_MUX_STATE(x)		((x) + 0x118)
-#define GPIO_P0_MUX_SET(x)		((x) + 0x120)
-#define GPIO_P0_MUX_CLR(x)		((x) + 0x124)
-#define GPIO_P0_MUX_STATE(x)		((x) + 0x128)
-#define GPIO_P1_MUX_SET(x)		((x) + 0x130)
-#define GPIO_P1_MUX_CLR(x)		((x) + 0x134)
-#define GPIO_P1_MUX_STATE(x)		((x) + 0x138)
+#define LPC32XX_GPIO_P3_INP_STATE(x)		((x) + 0x000)
+#define LPC32XX_GPIO_P3_OUTP_SET(x)		((x) + 0x004)
+#define LPC32XX_GPIO_P3_OUTP_CLR(x)		((x) + 0x008)
+#define LPC32XX_GPIO_P3_OUTP_STATE(x)		((x) + 0x00C)
+#define LPC32XX_GPIO_P2_DIR_SET(x)		((x) + 0x010)
+#define LPC32XX_GPIO_P2_DIR_CLR(x)		((x) + 0x014)
+#define LPC32XX_GPIO_P2_DIR_STATE(x)		((x) + 0x018)
+#define LPC32XX_GPIO_P2_INP_STATE(x)		((x) + 0x01C)
+#define LPC32XX_GPIO_P2_OUTP_SET(x)		((x) + 0x020)
+#define LPC32XX_GPIO_P2_OUTP_CLR(x)		((x) + 0x024)
+#define LPC32XX_GPIO_P2_MUX_SET(x)		((x) + 0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR(x)		((x) + 0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE(x)		((x) + 0x030)
+#define LPC32XX_GPIO_P0_INP_STATE(x)		((x) + 0x040)
+#define LPC32XX_GPIO_P0_OUTP_SET(x)		((x) + 0x044)
+#define LPC32XX_GPIO_P0_OUTP_CLR(x)		((x) + 0x048)
+#define LPC32XX_GPIO_P0_OUTP_STATE(x)		((x) + 0x04C)
+#define LPC32XX_GPIO_P0_DIR_SET(x)		((x) + 0x050)
+#define LPC32XX_GPIO_P0_DIR_CLR(x)		((x) + 0x054)
+#define LPC32XX_GPIO_P0_DIR_STATE(x)		((x) + 0x058)
+#define LPC32XX_GPIO_P1_INP_STATE(x)		((x) + 0x060)
+#define LPC32XX_GPIO_P1_OUTP_SET(x)		((x) + 0x064)
+#define LPC32XX_GPIO_P1_OUTP_CLR(x)		((x) + 0x068)
+#define LPC32XX_GPIO_P1_OUTP_STATE(x)		((x) + 0x06C)
+#define LPC32XX_GPIO_P1_DIR_SET(x)		((x) + 0x070)
+#define LPC32XX_GPIO_P1_DIR_CLR(x)		((x) + 0x074)
+#define LPC32XX_GPIO_P1_DIR_STATE(x)		((x) + 0x078)
+#define LPC32XX_GPIO_P_MUX_SET(x)		((x) + 0x100)
+#define LPC32XX_GPIO_P_MUX_CLR(x)		((x) + 0x104)
+#define LPC32XX_GPIO_P_MUX_STATE(x)		((x) + 0x108)
+#define LPC32XX_GPIO_P3_MUX_SET(x)		((x) + 0x110)
+#define LPC32XX_GPIO_P3_MUX_CLR(x)		((x) + 0x114)
+#define LPC32XX_GPIO_P3_MUX_STATE(x)		((x) + 0x118)
+#define LPC32XX_GPIO_P0_MUX_SET(x)		((x) + 0x120)
+#define LPC32XX_GPIO_P0_MUX_CLR(x)		((x) + 0x124)
+#define LPC32XX_GPIO_P0_MUX_STATE(x)		((x) + 0x128)
+#define LPC32XX_GPIO_P1_MUX_SET(x)		((x) + 0x130)
+#define LPC32XX_GPIO_P1_MUX_CLR(x)		((x) + 0x134)
+#define LPC32XX_GPIO_P1_MUX_STATE(x)		((x) + 0x138)
 
 #endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 0612994..80958b9 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -48,10 +48,10 @@
 /*
  * Mapped GPIOLIB GPIOs
  */
-#define SPI0_CS_GPIO	LPC32XX_GPIO(GPIO_P3_GRP, 5)
-#define LCD_POWER_GPIO	LPC32XX_GPIO(GPO_P3_GRP, 0)
-#define BKL_POWER_GPIO	LPC32XX_GPIO(GPO_P3_GRP, 4)
-#define LED_GPIO	LPC32XX_GPIO(GPO_P3_GRP, 1)
+#define SPI0_CS_GPIO	LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+#define LCD_POWER_GPIO	LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
+#define BKL_POWER_GPIO	LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define LED_GPIO	LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
 
 /*
  * AMBA LCD controller
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 09/16] ARM: LPC32XX: LPC32XX macro name changes and local macro use
       [not found] <LPC32XX architecture files (updated)>
                   ` (8 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 08/16] ARM: LPC32XX: Added LPC32XX identifier to GPIO " wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem * wellsk40 at gmail.com
                   ` (6 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Added the LPC32XX prefix to local macro names. Added several
new local macros for register offsets.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/suspend.S |   83 ++++++++++++++++++++-------------------
 1 files changed, 43 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
index 1d35b34..eea6ddc 100644
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -26,19 +26,22 @@
 #include <mach/hardware.h>
 
 /* Using named register defines makes the code easier to follow */
-#define WORK1_REG		r0
-#define WORK2_REG		r1
-#define SAVED_HCLK_DIV_REG	r2
-#define SAVED_HCLK_PLL_REG	r3
-#define SAVED_DRAM_CLKCTRL_REG	r4
-#define SAVED_PWR_CTRL_REG	r5
-#define CLKPWRBASE_REG		r6
-#define EMCBASE_REG		r7
-
-#define EMC_STATUS_OFFS		0x04
-#define EMC_STATUS_BUSY		0x1
-#define EMC_STATUS_SELF_RFSH	0x4
-
+#define WORK1_REG			r0
+#define WORK2_REG			r1
+#define SAVED_HCLK_DIV_REG		r2
+#define SAVED_HCLK_PLL_REG		r3
+#define SAVED_DRAM_CLKCTRL_REG		r4
+#define SAVED_PWR_CTRL_REG		r5
+#define CLKPWRBASE_REG			r6
+#define EMCBASE_REG			r7
+
+#define LPC32XX_EMC_STATUS_OFFS		0x04
+#define LPC32XX_EMC_STATUS_BUSY		0x1
+#define LPC32XX_EMC_STATUS_SELF_RFSH	0x4
+
+#define LPC32XX_CLKPWR_PWR_CTRL_OFFS	0x44
+#define LPC32XX_CLKPWR_HCLK_DIV_OFFS	0x40
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
 	.text
 
 ENTRY(lpc32xx_sys_suspend)
@@ -52,57 +55,57 @@ ENTRY(lpc32xx_sys_suspend)
 	ldr	EMCBASE_REG, [WORK1_REG, #4]
 
 	ldr	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
-		#LPC32XX_CLKPWR_PWR_CTRL(0)]
+		#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 	orr	WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
 
 	@ Wait for SDRAM busy status to go busy and then idle
 	@ This guarantees a small windows where DRAM isn't busy
 1:
-	ldr	WORK2_REG, [EMCBASE_REG, #EMC_STATUS_OFFS]
-	and	WORK2_REG, WORK2_REG, #EMC_STATUS_BUSY
-	cmp	WORK2_REG, #EMC_STATUS_BUSY
+	ldr	WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+	and	WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+	cmp	WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
 	bne	1b @ Branch while idle
 2:
-	ldr	WORK2_REG, [EMCBASE_REG, #EMC_STATUS_OFFS]
-	and	WORK2_REG, WORK2_REG, #EMC_STATUS_BUSY
-	cmp	WORK2_REG, #EMC_STATUS_BUSY
+	ldr	WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+	and	WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+	cmp	WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
 	beq	2b @ Branch until idle
 
 	@ Setup self-refresh with support for manual exit of
 	@ self-refresh mode
-	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 	orr	WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
-	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
-	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 
 	@ Wait for self-refresh acknowledge, clocks to the DRAM device
 	@ will automatically stop on start of self-refresh
 3:
-	ldr	WORK2_REG, [EMCBASE_REG, #EMC_STATUS_OFFS]
-	and	WORK2_REG, WORK2_REG, #EMC_STATUS_SELF_RFSH
-	cmp	WORK2_REG, #EMC_STATUS_SELF_RFSH
+	ldr	WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+	and	WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+	cmp	WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
 	bne	3b @ Branch until self-refresh mode starts
 
 	@ Enter direct-run mode from run mode
 	bic	WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
-	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 
 	@ Safe disable of DRAM clock in EMC block, prevents DDR sync
 	@ issues on restart
 	ldr	SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
-		#LPC32XX_CLKPWR_HCLK_DIV(0)]
+		#LPC32XX_CLKPWR_HCLK_DIV_OFFS]
 	and	WORK2_REG, SAVED_HCLK_DIV_REG, #0xFFFFFE7F
-	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV(0)]
+	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
 
 	@ Save HCLK PLL state and disable HCLK PLL
 	ldr	SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
-		#LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
+		#LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
 	bic	WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
-	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
+	str	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
 
 	@ Enter stop mode until an enabled event occurs
 	orr	WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
-	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 	nop
 	nop
 	nop
@@ -118,32 +121,32 @@ ENTRY(lpc32xx_sys_suspend)
 
 	@ Restore original HCLK PLL value and wait for PLL lock
 	str	SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
-		#LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
+		#LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
 4:
-	ldr	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL(0)]
+	ldr	WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
 	and	WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
 	bne	4b
 
 	@ Re-enter run mode with self-refresh flag cleared, but no DRAM
 	@ update yet. DRAM is still in self-refresh
 	str	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
-		#LPC32XX_CLKPWR_PWR_CTRL(0)]
+		#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 
 	@ Restore original DRAM clock mode to restore DRAM clocks
 	str	SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
-		#LPC32XX_CLKPWR_HCLK_DIV(0)]
+		#LPC32XX_CLKPWR_HCLK_DIV_OFFS]
 
 	@ Clear self-refresh mode
 	orr	WORK1_REG, SAVED_PWR_CTRL_REG,\
 		#LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
-	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL(0)]
+	str	WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 	str	SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
-		#LPC32XX_CLKPWR_PWR_CTRL(0)]
+		#LPC32XX_CLKPWR_PWR_CTRL_OFFS]
 
 	@ Wait for EMC to clear self-refresh mode
 5:
-	ldr	WORK2_REG, [EMCBASE_REG, #EMC_STATUS_OFFS]
-	and	WORK2_REG, WORK2_REG, #EMC_STATUS_SELF_RFSH
+	ldr	WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+	and	WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
 	bne	5b @ Branch until self-refresh has exited
 
 	@ restore regs and return
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem *
       [not found] <LPC32XX architecture files (updated)>
                   ` (9 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 09/16] ARM: LPC32XX: LPC32XX macro name changes and local macro use wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-03 10:10   ` Russell King - ARM Linux
  2010-02-03 10:18   ` Russell King - ARM Linux
  2010-02-02 23:59 ` [PATCH 11/16] ARM: LPC32XX: Converted interrupt registers " wellsk40 at gmail.com
                   ` (5 subsequent siblings)
  16 siblings, 2 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Most defined registers addresses used for readl/writel were untyped.
These have been changed to (void __iomem *).

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/clock.c                 |    2 +-
 arch/arm/mach-lpc32xx/clock.h                 |    2 +-
 arch/arm/mach-lpc32xx/gpiolib.c               |   60 ++-----
 arch/arm/mach-lpc32xx/include/mach/platform.h |  233 +++++++++++++------------
 arch/arm/mach-lpc32xx/pm_events.c             |  161 +++++++++---------
 arch/arm/mach-lpc32xx/serial.c                |    2 +-
 6 files changed, 221 insertions(+), 239 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index befe6fa..1b8616f 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -600,7 +600,7 @@ static struct clk clk_i2c1 = {
 static struct clk clk_i2c2 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= USB_OTG_IOBASE + 0xFF4,
+	.enable_reg	= (void __iomem *) (USB_OTG_IOBASE + 0xFF4),
 	.enable_mask	= 0x4,
 };
 
diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
index f37f245..619c332 100644
--- a/arch/arm/mach-lpc32xx/clock.h
+++ b/arch/arm/mach-lpc32xx/clock.h
@@ -34,7 +34,7 @@ struct clk {
 	u32 (*get_rate) (struct clk *clk);
 
 	/* Register address and bit mask for simple clocks */
-	u32 enable_reg;
+	void __iomem *enable_reg;
 	u32 enable_mask;
 };
 
diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
index beed7eb..13930d4 100644
--- a/arch/arm/mach-lpc32xx/gpiolib.c
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -89,52 +89,32 @@ static char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
 
 static struct gpio_regs gpio_grp_regs[] = {
 	{
-		.inp_state	=
-			(void __iomem *) LPC32XX_GPIO_P0_INP_STATE(GPIOBASE),
-		.outp_set	=
-			(void __iomem *) LPC32XX_GPIO_P0_OUTP_SET(GPIOBASE),
-		.outp_clr	=
-			(void __iomem *) LPC32XX_GPIO_P0_OUTP_CLR(GPIOBASE),
-		.dir_set	=
-			(void __iomem *) LPC32XX_GPIO_P0_DIR_SET(GPIOBASE),
-		.dir_clr	=
-			(void __iomem *) LPC32XX_GPIO_P0_DIR_CLR(GPIOBASE),
+		.inp_state	= LPC32XX_GPIO_P0_INP_STATE(GPIOBASE),
+		.outp_set	= LPC32XX_GPIO_P0_OUTP_SET(GPIOBASE),
+		.outp_clr	= LPC32XX_GPIO_P0_OUTP_CLR(GPIOBASE),
+		.dir_set	= LPC32XX_GPIO_P0_DIR_SET(GPIOBASE),
+		.dir_clr	= LPC32XX_GPIO_P0_DIR_CLR(GPIOBASE),
 	},
 	{
-		.inp_state	=
-			(void __iomem *) LPC32XX_GPIO_P1_INP_STATE(GPIOBASE),
-		.outp_set	=
-			(void __iomem *) LPC32XX_GPIO_P1_OUTP_SET(GPIOBASE),
-		.outp_clr	=
-			(void __iomem *) LPC32XX_GPIO_P1_OUTP_CLR(GPIOBASE),
-		.dir_set	=
-			(void __iomem *) LPC32XX_GPIO_P1_DIR_SET(GPIOBASE),
-		.dir_clr	=
-			(void __iomem *) LPC32XX_GPIO_P1_DIR_CLR(GPIOBASE),
+		.inp_state	= LPC32XX_GPIO_P1_INP_STATE(GPIOBASE),
+		.outp_set	= LPC32XX_GPIO_P1_OUTP_SET(GPIOBASE),
+		.outp_clr	= LPC32XX_GPIO_P1_OUTP_CLR(GPIOBASE),
+		.dir_set	= LPC32XX_GPIO_P1_DIR_SET(GPIOBASE),
+		.dir_clr	= LPC32XX_GPIO_P1_DIR_CLR(GPIOBASE),
 	},
 	{
-		.inp_state	=
-			(void __iomem *) LPC32XX_GPIO_P2_INP_STATE(GPIOBASE),
-		.outp_set	=
-			(void __iomem *) LPC32XX_GPIO_P2_OUTP_SET(GPIOBASE),
-		.outp_clr	=
-			(void __iomem *) LPC32XX_GPIO_P2_OUTP_CLR(GPIOBASE),
-		.dir_set	=
-			(void __iomem *) LPC32XX_GPIO_P2_DIR_SET(GPIOBASE),
-		.dir_clr	=
-			(void __iomem *) LPC32XX_GPIO_P2_DIR_CLR(GPIOBASE),
+		.inp_state	= LPC32XX_GPIO_P2_INP_STATE(GPIOBASE),
+		.outp_set	= LPC32XX_GPIO_P2_OUTP_SET(GPIOBASE),
+		.outp_clr	= LPC32XX_GPIO_P2_OUTP_CLR(GPIOBASE),
+		.dir_set	= LPC32XX_GPIO_P2_DIR_SET(GPIOBASE),
+		.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR(GPIOBASE),
 	},
 	{
-		.inp_state	=
-			(void __iomem *) LPC32XX_GPIO_P3_INP_STATE(GPIOBASE),
-		.outp_set	=
-			(void __iomem *) LPC32XX_GPIO_P3_OUTP_SET(GPIOBASE),
-		.outp_clr	=
-			(void __iomem *) LPC32XX_GPIO_P3_OUTP_CLR(GPIOBASE),
-		.dir_set	=
-			(void __iomem *) LPC32XX_GPIO_P2_DIR_SET(GPIOBASE),
-		.dir_clr	=
-			(void __iomem *) LPC32XX_GPIO_P2_DIR_CLR(GPIOBASE),
+		.inp_state	= LPC32XX_GPIO_P3_INP_STATE(GPIOBASE),
+		.outp_set	= LPC32XX_GPIO_P3_OUTP_SET(GPIOBASE),
+		.outp_clr	= LPC32XX_GPIO_P3_OUTP_CLR(GPIOBASE),
+		.dir_set	= LPC32XX_GPIO_P2_DIR_SET(GPIOBASE),
+		.dir_clr	= LPC32XX_GPIO_P2_DIR_CLR(GPIOBASE),
 	},
 };
 
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index adc932b..93541f4 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -23,6 +23,8 @@
 #ifndef __ASM_ARCH_PLATFORM_H
 #define __ASM_ARCH_PLATFORM_H
 
+#define IOMEM(x, y)			(__force void __iomem *)((x) + (y))
+
 #define _SBF(f, v)			(((v)) << (f))
 #define _BIT(n)				(1 << (n))
 
@@ -135,54 +137,55 @@
 /*
  * Clock and Power control register offsets
  */
-#define LPC32XX_CLKPWR_DEBUG_CTRL(x)		((x) + 0x000)
-#define LPC32XX_CLKPWR_BOOTMAP(x)		((x) + 0x014)
-#define LPC32XX_CLKPWR_P01_ER(x)		((x) + 0x018)
-#define LPC32XX_CLKPWR_USBCLK_PDIV(x)		((x) + 0x01C)
-#define LPC32XX_CLKPWR_INT_ER(x)		((x) + 0x020)
-#define LPC32XX_CLKPWR_INT_RS(x)		((x) + 0x024)
-#define LPC32XX_CLKPWR_INT_SR(x)		((x) + 0x028)
-#define LPC32XX_CLKPWR_INT_AP(x)		((x) + 0x02C)
-#define LPC32XX_CLKPWR_PIN_ER(x)		((x) + 0x030)
-#define LPC32XX_CLKPWR_PIN_RS(x)		((x) + 0x034)
-#define LPC32XX_CLKPWR_PIN_SR(x)		((x) + 0x038)
-#define LPC32XX_CLKPWR_PIN_AP(x)		((x) + 0x03C)
-#define LPC32XX_CLKPWR_HCLK_DIV(x)		((x) + 0x040)
-#define LPC32XX_CLKPWR_PWR_CTRL(x)		((x) + 0x044)
-#define LPC32XX_CLKPWR_PLL397_CTRL(x)		((x) + 0x048)
-#define LPC32XX_CLKPWR_MAIN_OSC_CTRL(x)		((x) + 0x04C)
-#define LPC32XX_CLKPWR_SYSCLK_CTRL(x)		((x) + 0x050)
-#define LPC32XX_CLKPWR_LCDCLK_CTRL(x)		((x) + 0x054)
-#define LPC32XX_CLKPWR_HCLKPLL_CTRL(x)		((x) + 0x058)
-#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1(x)	((x) + 0x060)
-#define LPC32XX_CLKPWR_USB_CTRL(x)		((x) + 0x064)
-#define LPC32XX_CLKPWR_SDRAMCLK_CTRL(x)		((x) + 0x068)
-#define LPC32XX_CLKPWR_DDR_LAP_NOM(x)		((x) + 0x06C)
-#define LPC32XX_CLKPWR_DDR_LAP_COUNT(x)		((x) + 0x070)
-#define LPC32XX_CLKPWR_DDR_LAP_DELAY(x)		((x) + 0x074)
-#define LPC32XX_CLKPWR_SSP_CLK_CTRL(x)		((x) + 0x078)
-#define LPC32XX_CLKPWR_I2S_CLK_CTRL(x)		((x) + 0x07C)
-#define LPC32XX_CLKPWR_MS_CTRL(x)		((x) + 0x080)
-#define LPC32XX_CLKPWR_MACCLK_CTRL(x)		((x) + 0x090)
-#define LPC32XX_CLKPWR_TEST_CLK_SEL(x)		((x) + 0x0A4)
-#define LPC32XX_CLKPWR_SFW_INT(x)		((x) + 0x0A8)
-#define LPC32XX_CLKPWR_I2C_CLK_CTRL(x)		((x) + 0x0AC)
-#define LPC32XX_CLKPWR_KEY_CLK_CTRL(x)		((x) + 0x0B0)
-#define LPC32XX_CLKPWR_ADC_CLK_CTRL(x)		((x) + 0x0B4)
-#define LPC32XX_CLKPWR_PWM_CLK_CTRL(x)		((x) + 0x0B8)
-#define LPC32XX_CLKPWR_TIMER_CLK_CTRL(x)	((x) + 0x0BC)
-#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(x) ((x) + 0x0C0)
-#define LPC32XX_CLKPWR_SPI_CLK_CTRL(x)		((x) + 0x0C4)
-#define LPC32XX_CLKPWR_NAND_CLK_CTRL(x)		((x) + 0x0C8)
-#define LPC32XX_CLKPWR_UART3_CLK_CTRL(x)	((x) + 0x0D0)
-#define LPC32XX_CLKPWR_UART4_CLK_CTRL(x)	((x) + 0x0D4)
-#define LPC32XX_CLKPWR_UART5_CLK_CTRL(x)	((x) + 0x0D8)
-#define LPC32XX_CLKPWR_UART6_CLK_CTRL(x)	((x) + 0x0DC)
-#define LPC32XX_CLKPWR_IRDA_CLK_CTRL(x)		((x) + 0x0E0)
-#define LPC32XX_CLKPWR_UART_CLK_CTRL(x)		((x) + 0x0E4)
-#define LPC32XX_CLKPWR_DMA_CLK_CTRL(x)		((x) + 0x0E8)
-#define LPC32XX_CLKPWR_AUTOCLOCK(x)		((x) + 0x0EC)
-#define LPC32XX_CLKPWR_DEVID(x, y)		((x) + 0x130 + (y))
+#define LPC32XX_CLKPWR_DEBUG_CTRL(x)		IOMEM((x), 0x000)
+#define LPC32XX_CLKPWR_BOOTMAP(x)		IOMEM((x), 0x014)
+#define LPC32XX_CLKPWR_P01_ER(x)		IOMEM((x), 0x018)
+#define LPC32XX_CLKPWR_USBCLK_PDIV(x)		IOMEM((x), 0x01C)
+#define LPC32XX_CLKPWR_INT_ER(x)		IOMEM((x), 0x020)
+#define LPC32XX_CLKPWR_INT_RS(x)		IOMEM((x), 0x024)
+#define LPC32XX_CLKPWR_INT_SR(x)		IOMEM((x), 0x028)
+#define LPC32XX_CLKPWR_INT_AP(x)		IOMEM((x), 0x02C)
+#define LPC32XX_CLKPWR_PIN_ER(x)		IOMEM((x), 0x030)
+#define LPC32XX_CLKPWR_PIN_RS(x)		IOMEM((x), 0x034)
+#define LPC32XX_CLKPWR_PIN_SR(x)		IOMEM((x), 0x038)
+#define LPC32XX_CLKPWR_PIN_AP(x)		IOMEM((x), 0x03C)
+#define LPC32XX_CLKPWR_HCLK_DIV(x)		IOMEM((x), 0x040)
+#define LPC32XX_CLKPWR_PWR_CTRL(x)		IOMEM((x), 0x044)
+#define LPC32XX_CLKPWR_PLL397_CTRL(x)		IOMEM((x), 0x048)
+#define LPC32XX_CLKPWR_MAIN_OSC_CTRL(x)		IOMEM((x), 0x04C)
+#define LPC32XX_CLKPWR_SYSCLK_CTRL(x)		IOMEM((x), 0x050)
+#define LPC32XX_CLKPWR_LCDCLK_CTRL(x)		IOMEM((x), 0x054)
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL(x)		IOMEM((x), 0x058)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1(x)	IOMEM((x), 0x060)
+#define LPC32XX_CLKPWR_USB_CTRL(x)		IOMEM((x), 0x064)
+#define LPC32XX_CLKPWR_SDRAMCLK_CTRL(x)		IOMEM((x), 0x068)
+#define LPC32XX_CLKPWR_DDR_LAP_NOM(x)		IOMEM((x), 0x06C)
+#define LPC32XX_CLKPWR_DDR_LAP_COUNT(x)		IOMEM((x), 0x070)
+#define LPC32XX_CLKPWR_DDR_LAP_DELAY(x)		IOMEM((x), 0x074)
+#define LPC32XX_CLKPWR_SSP_CLK_CTRL(x)		IOMEM((x), 0x078)
+#define LPC32XX_CLKPWR_I2S_CLK_CTRL(x)		IOMEM((x), 0x07C)
+#define LPC32XX_CLKPWR_MS_CTRL(x)		IOMEM((x), 0x080)
+#define LPC32XX_CLKPWR_MACCLK_CTRL(x)		IOMEM((x), 0x090)
+#define LPC32XX_CLKPWR_TEST_CLK_SEL(x)		IOMEM((x), 0x0A4)
+#define LPC32XX_CLKPWR_SFW_INT(x)		IOMEM((x), 0x0A8)
+#define LPC32XX_CLKPWR_I2C_CLK_CTRL(x)		IOMEM((x), 0x0AC)
+#define LPC32XX_CLKPWR_KEY_CLK_CTRL(x)		IOMEM((x), 0x0B0)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL(x)		IOMEM((x), 0x0B4)
+#define LPC32XX_CLKPWR_PWM_CLK_CTRL(x)		IOMEM((x), 0x0B8)
+#define LPC32XX_CLKPWR_TIMER_CLK_CTRL(x)	IOMEM((x), 0x0BC)
+#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1(x) IOMEM((x), 0x0C0)
+#define LPC32XX_CLKPWR_SPI_CLK_CTRL(x)		IOMEM((x), 0x0C4)
+#define LPC32XX_CLKPWR_NAND_CLK_CTRL(x)		IOMEM((x), 0x0C8)
+#define LPC32XX_CLKPWR_UART3_CLK_CTRL(x)	IOMEM((x), 0x0D0)
+#define LPC32XX_CLKPWR_UART4_CLK_CTRL(x)	IOMEM((x), 0x0D4)
+#define LPC32XX_CLKPWR_UART5_CLK_CTRL(x)	IOMEM((x), 0x0D8)
+#define LPC32XX_CLKPWR_UART6_CLK_CTRL(x)	IOMEM((x), 0x0DC)
+#define LPC32XX_CLKPWR_IRDA_CLK_CTRL(x)		IOMEM((x), 0x0E0)
+#define LPC32XX_CLKPWR_UART_CLK_CTRL(x)		IOMEM((x), 0x0E4)
+#define LPC32XX_CLKPWR_DMA_CLK_CTRL(x)		IOMEM((x), 0x0E8)
+#define LPC32XX_CLKPWR_AUTOCLOCK(x)		IOMEM((x), 0x0EC)
+#define LPC32XX_CLKPWR_DEVID(x, y)		(__force void __iomem *)\
+						((x) + 0x130 + (y))
 
 /*
  * clkpwr_debug_ctrl register definitions
@@ -600,23 +603,23 @@
  * Timer/counter register offsets
  *
  */
-#define LCP32XX_TIMER_IR(x)			((x) + 0x00)
-#define LCP32XX_TIMER_TCR(x)			((x) + 0x04)
-#define LCP32XX_TIMER_TC(x)			((x) + 0x08)
-#define LCP32XX_TIMER_PR(x)			((x) + 0x0C)
-#define LCP32XX_TIMER_PC(x)			((x) + 0x10)
-#define LCP32XX_TIMER_MCR(x)			((x) + 0x14)
-#define LCP32XX_TIMER_MR0(x)			((x) + 0x18)
-#define LCP32XX_TIMER_MR1(x)			((x) + 0x1C)
-#define LCP32XX_TIMER_MR2(x)			((x) + 0x20)
-#define LCP32XX_TIMER_MR3(x)			((x) + 0x24)
-#define LCP32XX_TIMER_CCR(x)			((x) + 0x28)
-#define LCP32XX_TIMER_CR0(x)			((x) + 0x2C)
-#define LCP32XX_TIMER_CR1(x)			((x) + 0x30)
-#define LCP32XX_TIMER_CR2(x)			((x) + 0x34)
-#define LCP32XX_TIMER_CR3(x)			((x) + 0x38)
-#define LCP32XX_TIMER_EMR(x)			((x) + 0x3C)
-#define LCP32XX_TIMER_CTCR(x)			((x) + 0x70)
+#define LCP32XX_TIMER_IR(x)			IOMEM((x), 0x00)
+#define LCP32XX_TIMER_TCR(x)			IOMEM((x), 0x04)
+#define LCP32XX_TIMER_TC(x)			IOMEM((x), 0x08)
+#define LCP32XX_TIMER_PR(x)			IOMEM((x), 0x0C)
+#define LCP32XX_TIMER_PC(x)			IOMEM((x), 0x10)
+#define LCP32XX_TIMER_MCR(x)			IOMEM((x), 0x14)
+#define LCP32XX_TIMER_MR0(x)			IOMEM((x), 0x18)
+#define LCP32XX_TIMER_MR1(x)			IOMEM((x), 0x1C)
+#define LCP32XX_TIMER_MR2(x)			IOMEM((x), 0x20)
+#define LCP32XX_TIMER_MR3(x)			IOMEM((x), 0x24)
+#define LCP32XX_TIMER_CCR(x)			IOMEM((x), 0x28)
+#define LCP32XX_TIMER_CR0(x)			IOMEM((x), 0x2C)
+#define LCP32XX_TIMER_CR1(x)			IOMEM((x), 0x30)
+#define LCP32XX_TIMER_CR2(x)			IOMEM((x), 0x34)
+#define LCP32XX_TIMER_CR3(x)			IOMEM((x), 0x38)
+#define LCP32XX_TIMER_EMR(x)			IOMEM((x), 0x3C)
+#define LCP32XX_TIMER_CTCR(x)			IOMEM((x), 0x70)
 
 /*
  * ir register definitions
@@ -642,23 +645,23 @@
  * Standard UART register offsets
  *
  */
-#define LPC32XX_UART_DLL_FIFO(x)		((x) + 0x00)
-#define LPC32XX_UART_DLM_IER(x)			((x) + 0x04)
-#define LPC32XX_UART_IIR_FCR(x)			((x) + 0x08)
-#define LPC32XX_UART_LCR_(x)			((x) + 0x0C)
-#define LPC32XX_UART_MODEM_CTRL(x)		((x) + 0x10)
-#define LPC32XX_UART_LSR_(x)			((x) + 0x14)
-#define LPC32XX_UART_MODEM_STATUS(x)		((x) + 0x18)
-#define LPC32XX_UART_RXLEV(x)			((x) + 0x1C)
+#define LPC32XX_UART_DLL_FIFO(x)		IOMEM((x), 0x00)
+#define LPC32XX_UART_DLM_IER(x)			IOMEM((x), 0x04)
+#define LPC32XX_UART_IIR_FCR(x)			IOMEM((x), 0x08)
+#define LPC32XX_UART_LCR_(x)			IOMEM((x), 0x0C)
+#define LPC32XX_UART_MODEM_CTRL(x)		IOMEM((x), 0x10)
+#define LPC32XX_UART_LSR_(x)			IOMEM((x), 0x14)
+#define LPC32XX_UART_MODEM_STATUS(x)		IOMEM((x), 0x18)
+#define LPC32XX_UART_RXLEV(x)			IOMEM((x), 0x1C)
 
 /*
  *
  * UART control structure offsets
  *
  */
-#define LPC32XX_UARTCTL_CTRL(x)			((x) + 0x00)
-#define LPC32XX_UARTCTL_CLKMODE(x)		((x) + 0x04)
-#define LPC32XX_UARTCTL_CLOOP(x)		((x) + 0x08)
+#define LPC32XX_UARTCTL_CTRL(x)			IOMEM((x), 0x00)
+#define LPC32XX_UARTCTL_CLKMODE(x)		IOMEM((x), 0x04)
+#define LPC32XX_UARTCTL_CLOOP(x)		IOMEM((x), 0x08)
 
 /*
  * ctrl register definitions
@@ -690,44 +693,44 @@
  * GPIO Module Register offsets
  *
  */
-#define LPC32XX_GPIO_P3_INP_STATE(x)		((x) + 0x000)
-#define LPC32XX_GPIO_P3_OUTP_SET(x)		((x) + 0x004)
-#define LPC32XX_GPIO_P3_OUTP_CLR(x)		((x) + 0x008)
-#define LPC32XX_GPIO_P3_OUTP_STATE(x)		((x) + 0x00C)
-#define LPC32XX_GPIO_P2_DIR_SET(x)		((x) + 0x010)
-#define LPC32XX_GPIO_P2_DIR_CLR(x)		((x) + 0x014)
-#define LPC32XX_GPIO_P2_DIR_STATE(x)		((x) + 0x018)
-#define LPC32XX_GPIO_P2_INP_STATE(x)		((x) + 0x01C)
-#define LPC32XX_GPIO_P2_OUTP_SET(x)		((x) + 0x020)
-#define LPC32XX_GPIO_P2_OUTP_CLR(x)		((x) + 0x024)
-#define LPC32XX_GPIO_P2_MUX_SET(x)		((x) + 0x028)
-#define LPC32XX_GPIO_P2_MUX_CLR(x)		((x) + 0x02C)
-#define LPC32XX_GPIO_P2_MUX_STATE(x)		((x) + 0x030)
-#define LPC32XX_GPIO_P0_INP_STATE(x)		((x) + 0x040)
-#define LPC32XX_GPIO_P0_OUTP_SET(x)		((x) + 0x044)
-#define LPC32XX_GPIO_P0_OUTP_CLR(x)		((x) + 0x048)
-#define LPC32XX_GPIO_P0_OUTP_STATE(x)		((x) + 0x04C)
-#define LPC32XX_GPIO_P0_DIR_SET(x)		((x) + 0x050)
-#define LPC32XX_GPIO_P0_DIR_CLR(x)		((x) + 0x054)
-#define LPC32XX_GPIO_P0_DIR_STATE(x)		((x) + 0x058)
-#define LPC32XX_GPIO_P1_INP_STATE(x)		((x) + 0x060)
-#define LPC32XX_GPIO_P1_OUTP_SET(x)		((x) + 0x064)
-#define LPC32XX_GPIO_P1_OUTP_CLR(x)		((x) + 0x068)
-#define LPC32XX_GPIO_P1_OUTP_STATE(x)		((x) + 0x06C)
-#define LPC32XX_GPIO_P1_DIR_SET(x)		((x) + 0x070)
-#define LPC32XX_GPIO_P1_DIR_CLR(x)		((x) + 0x074)
-#define LPC32XX_GPIO_P1_DIR_STATE(x)		((x) + 0x078)
-#define LPC32XX_GPIO_P_MUX_SET(x)		((x) + 0x100)
-#define LPC32XX_GPIO_P_MUX_CLR(x)		((x) + 0x104)
-#define LPC32XX_GPIO_P_MUX_STATE(x)		((x) + 0x108)
-#define LPC32XX_GPIO_P3_MUX_SET(x)		((x) + 0x110)
-#define LPC32XX_GPIO_P3_MUX_CLR(x)		((x) + 0x114)
-#define LPC32XX_GPIO_P3_MUX_STATE(x)		((x) + 0x118)
-#define LPC32XX_GPIO_P0_MUX_SET(x)		((x) + 0x120)
-#define LPC32XX_GPIO_P0_MUX_CLR(x)		((x) + 0x124)
-#define LPC32XX_GPIO_P0_MUX_STATE(x)		((x) + 0x128)
-#define LPC32XX_GPIO_P1_MUX_SET(x)		((x) + 0x130)
-#define LPC32XX_GPIO_P1_MUX_CLR(x)		((x) + 0x134)
-#define LPC32XX_GPIO_P1_MUX_STATE(x)		((x) + 0x138)
+#define LPC32XX_GPIO_P3_INP_STATE(x)		IOMEM((x), 0x000)
+#define LPC32XX_GPIO_P3_OUTP_SET(x)		IOMEM((x), 0x004)
+#define LPC32XX_GPIO_P3_OUTP_CLR(x)		IOMEM((x), 0x008)
+#define LPC32XX_GPIO_P3_OUTP_STATE(x)		IOMEM((x), 0x00C)
+#define LPC32XX_GPIO_P2_DIR_SET(x)		IOMEM((x), 0x010)
+#define LPC32XX_GPIO_P2_DIR_CLR(x)		IOMEM((x), 0x014)
+#define LPC32XX_GPIO_P2_DIR_STATE(x)		IOMEM((x), 0x018)
+#define LPC32XX_GPIO_P2_INP_STATE(x)		IOMEM((x), 0x01C)
+#define LPC32XX_GPIO_P2_OUTP_SET(x)		IOMEM((x), 0x020)
+#define LPC32XX_GPIO_P2_OUTP_CLR(x)		IOMEM((x), 0x024)
+#define LPC32XX_GPIO_P2_MUX_SET(x)		IOMEM((x), 0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR(x)		IOMEM((x), 0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE(x)		IOMEM((x), 0x030)
+#define LPC32XX_GPIO_P0_INP_STATE(x)		IOMEM((x), 0x040)
+#define LPC32XX_GPIO_P0_OUTP_SET(x)		IOMEM((x), 0x044)
+#define LPC32XX_GPIO_P0_OUTP_CLR(x)		IOMEM((x), 0x048)
+#define LPC32XX_GPIO_P0_OUTP_STATE(x)		IOMEM((x), 0x04C)
+#define LPC32XX_GPIO_P0_DIR_SET(x)		IOMEM((x), 0x050)
+#define LPC32XX_GPIO_P0_DIR_CLR(x)		IOMEM((x), 0x054)
+#define LPC32XX_GPIO_P0_DIR_STATE(x)		IOMEM((x), 0x058)
+#define LPC32XX_GPIO_P1_INP_STATE(x)		IOMEM((x), 0x060)
+#define LPC32XX_GPIO_P1_OUTP_SET(x)		IOMEM((x), 0x064)
+#define LPC32XX_GPIO_P1_OUTP_CLR(x)		IOMEM((x), 0x068)
+#define LPC32XX_GPIO_P1_OUTP_STATE(x)		IOMEM((x), 0x06C)
+#define LPC32XX_GPIO_P1_DIR_SET(x)		IOMEM((x), 0x070)
+#define LPC32XX_GPIO_P1_DIR_CLR(x)		IOMEM((x), 0x074)
+#define LPC32XX_GPIO_P1_DIR_STATE(x)		IOMEM((x), 0x078)
+#define LPC32XX_GPIO_P_MUX_SET(x)		IOMEM((x), 0x100)
+#define LPC32XX_GPIO_P_MUX_CLR(x)		IOMEM((x), 0x104)
+#define LPC32XX_GPIO_P_MUX_STATE(x)		IOMEM((x), 0x108)
+#define LPC32XX_GPIO_P3_MUX_SET(x)		IOMEM((x), 0x110)
+#define LPC32XX_GPIO_P3_MUX_CLR(x)		IOMEM((x), 0x114)
+#define LPC32XX_GPIO_P3_MUX_STATE(x)		IOMEM((x), 0x118)
+#define LPC32XX_GPIO_P0_MUX_SET(x)		IOMEM((x), 0x120)
+#define LPC32XX_GPIO_P0_MUX_CLR(x)		IOMEM((x), 0x124)
+#define LPC32XX_GPIO_P0_MUX_STATE(x)		IOMEM((x), 0x128)
+#define LPC32XX_GPIO_P1_MUX_SET(x)		IOMEM((x), 0x130)
+#define LPC32XX_GPIO_P1_MUX_CLR(x)		IOMEM((x), 0x134)
+#define LPC32XX_GPIO_P1_MUX_STATE(x)		IOMEM((x), 0x138)
 
 #endif
diff --git a/arch/arm/mach-lpc32xx/pm_events.c b/arch/arm/mach-lpc32xx/pm_events.c
index ffd46c4..835207d 100644
--- a/arch/arm/mach-lpc32xx/pm_events.c
+++ b/arch/arm/mach-lpc32xx/pm_events.c
@@ -30,306 +30,306 @@
 #include "pm.h"
 
 struct lpc32xx_event_info {
-	u32 offs;
+	void __iomem *reg;
 	u32 mask;
 };
 
 static const struct lpc32xx_event_info events[LPC32XX_LAST_EVENT + 1] = {
 	[LPC32XX_WKUP_GPI_08] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O8_BIT,
 	},
 	[LPC32XX_WKUP_GPI_09] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O9_BIT,
 	},
 	[LPC32XX_WKUP_GPI_19] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_19_BIT,
 	},
 	[LPC32XX_WKUP_SPI2_DATIN] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT,
 	},
 	[LPC32XX_WKUP_GPI_07] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O7_BIT,
 	},
 	[LPC32XX_WKUP_SPI1_DATIN] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT,
 	},
 	[LPC32XX_WKUP_SYSCLKEN] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT,
 	},
 	[LPC32XX_WKUP_GPI00] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O0_BIT,
 	},
 	[LPC32XX_WKUP_GPI01] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O1_BIT,
 	},
 	[LPC32XX_WKUP_GPI02] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O2_BIT,
 	},
 	[LPC32XX_WKUP_GPI03] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O3_BIT,
 	},
 	[LPC32XX_WKUP_GPI04] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O4_BIT,
 	},
 	[LPC32XX_WKUP_GPI05] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O5_BIT,
 	},
 	[LPC32XX_WKUP_GPI06] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPIO_O6_BIT,
 	},
 	[LPC32XX_WKUP_MSDIO_START] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT,
 	},
 	[LPC32XX_WKUP_SDIO_INT_N] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT,
 	},
 	[LPC32XX_WKUP_U1_RX] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT,
 	},
 	[LPC32XX_WKUP_U2_RX] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT,
 	},
 	[LPC32XX_WKUP_U2_HCTS] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT,
 	},
 	[LPC32XX_WKUP_U3_RX] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT,
 	},
 	[LPC32XX_WKUP_GPI_28] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_GPI_11_BIT,
 	},
 	[LPC32XX_WKUP_U5_RX] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT,
 	},
 	[LPC32XX_WKUP_U6_IRRX] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT,
 	},
 	[LPC32XX_WKUP_U7_HCTS] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT,
 	},
 	[LPC32XX_WKUP_U7_RX] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_PIN_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT,
 	},
 
 	[LPC32XX_WKUP_GPIO_00] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_01] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_02] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_03] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_04] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
 	},
 	[LPC32XX_WKUP_GPIO_05] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
 	},
 	[LPC32XX_WKUP_P0_P1_ALL] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_P0P1_BIT,
 	},
 	[LPC32XX_WKUP_MAC_START] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
 	},
 	[LPC32XX_WKUP_KEY_IRQ] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
 	},
 	[LPC32XX_WKUP_USB_OTG_ATX_INT_N] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
 	},
 	[LPC32XX_WKUP_USB_OTG_TIMER] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT,
 	},
 	[LPC32XX_WKUP_USB_I2C_INT] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_I2C_BIT,
 	},
 	[LPC32XX_WKUP_USB_INT] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
 	},
 	[LPC32XX_WKUP_USB_NEED_CLK] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT,
 	},
 	[LPC32XX_WKUP_RTC_INT] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
 	},
 	[LPC32XX_WKUP_MSTIMER_INT] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
 	},
 	[LPC32XX_WKUP_USB_AHC_NEED_CLK] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT,
 	},
 	[LPC32XX_WKUP_TS_AUX_INT] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
 	},
 	[LPC32XX_WKUP_TS_P_INT] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
 	},
 	[LPC32XX_WKUP_TS_INT] = {
-		.offs = LPC32XX_CLKPWR_INT_ER(0),
+		.reg = LPC32XX_CLKPWR_INT_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
 	},
 	[LPC32XX_WKUP_P0_0] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT,
 	},
 	[LPC32XX_WKUP_P0_1] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT,
 	},
 	[LPC32XX_WKUP_P0_2] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT,
 	},
 	[LPC32XX_WKUP_P0_3] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT,
 	},
 	[LPC32XX_WKUP_P0_4] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT,
 	},
 	[LPC32XX_WKUP_P0_5] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT,
 	},
 	[LPC32XX_WKUP_P0_6] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT,
 	},
 	[LPC32XX_WKUP_P0_7] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT,
 	},
 	[LPC32XX_WKUP_P1_3] = {
-		.offs = LPC32XX_CLKPWR_PIN_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT,
 	},
 	[LPC32XX_WKUP_P1_4] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT,
 	},
 	[LPC32XX_WKUP_P1_5] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT,
 	},
 	[LPC32XX_WKUP_P1_6] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT,
 	},
 	[LPC32XX_WKUP_P1_7] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT,
 	},
 	[LPC32XX_WKUP_P1_8] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT,
 	},
 	[LPC32XX_WKUP_P1_9] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT,
 	},
 	[LPC32XX_WKUP_P1_10] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT,
 	},
 	[LPC32XX_WKUP_P1_11] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT,
 	},
 	[LPC32XX_WKUP_P1_12] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT,
 	},
 	[LPC32XX_WKUP_P1_13] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT,
 	},
 	[LPC32XX_WKUP_P1_14] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT,
 	},
 	[LPC32XX_WKUP_P1_15] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT,
 	},
 	[LPC32XX_WKUP_P1_16] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT,
 	},
 	[LPC32XX_WKUP_P1_17] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT,
 	},
 	[LPC32XX_WKUP_P1_18] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT,
 	},
 	[LPC32XX_WKUP_P1_19] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT,
 	},
 	[LPC32XX_WKUP_P1_20] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT,
 	},
 	[LPC32XX_WKUP_P1_21] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT,
 	},
 	[LPC32XX_WKUP_P1_22] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT,
 	},
 	[LPC32XX_WKUP_P1_23] = {
-		.offs = LPC32XX_CLKPWR_P01_ER(0),
+		.reg = LPC32XX_CLKPWR_P01_ER(CLKPWR_IOBASE),
 		.mask = LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT,
 	},
 };
@@ -360,14 +360,14 @@ void lpc32xx_event_init(void)
 
 void lpc32xx_event_enable(enum lpc32xx_events event_id)
 {
-	writel(readl(CLKPWR_IOBASE + events[event_id].offs) |
-		events[event_id].mask, CLKPWR_IOBASE + events[event_id].offs);
+	writel(readl(events[event_id].reg) | events[event_id].mask,
+		events[event_id].reg);
 }
 
 void lpc32xx_event_disable(enum lpc32xx_events event_id)
 {
-	writel(readl(CLKPWR_IOBASE + events[event_id].offs) &
-		~events[event_id].mask, CLKPWR_IOBASE + events[event_id].offs);
+	writel(readl(events[event_id].reg) & ~events[event_id].mask,
+		events[event_id].reg);
 }
 
 extern int lpc32xx_event_set(enum lpc32xx_events event_id,
@@ -403,8 +403,7 @@ int lpc32xx_event_enabled(enum lpc32xx_events event_id)
 {
 	u32 tmp;
 
-	tmp = readl(CLKPWR_IOBASE + events[event_id].offs) &
-		events[event_id].mask;
+	tmp = readl(events[event_id].reg) & events[event_id].mask;
 
 	return (tmp != 0);
 }
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 3a0acfd..a2b8e12 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -90,7 +90,7 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 struct uartinit {
 	char *uart_ck_name;
 	u32 ck_mode_mask;
-	u32 pdiv_clk_reg;
+	void __iomem *pdiv_clk_reg;
 };
 
 static struct uartinit uartinit_data[] __initdata = {
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 11/16] ARM: LPC32XX: Converted interrupt registers to void __iomem *
       [not found] <LPC32XX architecture files (updated)>
                   ` (10 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem * wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-04 10:05   ` Uwe Kleine-König
  2010-02-02 23:59 ` [PATCH 12/16] ARM: LPC32XX: Watchdog reset type and sparse fixes wellsk40 at gmail.com
                   ` (4 subsequent siblings)
  16 siblings, 1 reply; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Added register access macros (similar to other register accesses).
Updated irq handler to use new access macros.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/include/mach/entry-macro.S |    6 +-
 arch/arm/mach-lpc32xx/include/mach/platform.h    |   12 ++--
 arch/arm/mach-lpc32xx/irq.c                      |   66 +++++++++++-----------
 3 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
index 25f2adc..9626bac 100644
--- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -39,7 +39,7 @@
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	/* Get MIC status first */
 	ldr	\base, =IO_ADDRESS(LPC32XX_MIC_BASE)
-	ldr	\irqstat, [\base, #LPC32XX_INTC_STAT]
+	ldr	\irqstat, [\base, #8]
 	and	\irqstat, \irqstat, #0xFFFFFFFC
 	mov	\tmp, #0
 
@@ -49,7 +49,7 @@
 
 	/* SIC1 interrupts start at offset 32 */
 	ldr	\base, =IO_ADDRESS(LPC32XX_SIC1_BASE)
-	ldr	\irqstat, [\base, #LPC32XX_INTC_STAT]
+	ldr	\irqstat, [\base, #8]
 	mov	\tmp, #32
 
 	/* Drop through to SIC2 if SIC1 is not pending */
@@ -58,7 +58,7 @@
 
 	/* SIC2 interrupts start at offset 64 */
 	ldr	\base, =IO_ADDRESS(LPC32XX_SIC2_BASE)
-	ldr	\irqstat, [\base, #LPC32XX_INTC_STAT]
+	ldr	\irqstat, [\base, #8]
 	mov	\tmp, #64
 
 	/* Safety check only, exit if no status on MIC, SIC1, SIC2 */
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 93541f4..66c6072 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -591,12 +591,12 @@
 /*
  * Interrupt controller register offsets
  */
-#define LPC32XX_INTC_MASK			0x00
-#define LPC32XX_INTC_RAW_STAT			0x04
-#define LPC32XX_INTC_STAT			0x08
-#define LPC32XX_INTC_POLAR			0x0C
-#define LPC32XX_INTC_ACT_TYPE			0x10
-#define LPC32XX_INTC_TYPE			0x14
+#define LPC32XX_INTC_MASK(x)			IOMEM((x), 0x00)
+#define LPC32XX_INTC_RAW_STAT(x)		IOMEM((x), 0x04)
+#define LPC32XX_INTC_STAT(x)			IOMEM((x), 0x08)
+#define LPC32XX_INTC_POLAR(x)			IOMEM((x), 0x0C)
+#define LPC32XX_INTC_ACT_TYPE(x)		IOMEM((x), 0x10)
+#define LPC32XX_INTC_TYPE(x)			IOMEM((x), 0x14)
 
 /*
  *
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 3ac8b4d..3266856 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -68,9 +68,9 @@ static void lpc32xx_mask_irq(unsigned int irq)
 
 	get_controller(irq, &ctrl, &mask);
 
-	reg = readl(ctrl + LPC32XX_INTC_MASK);
+	reg = readl(LPC32XX_INTC_MASK(ctrl));
 	reg &= ~mask;
-	writel(reg, (ctrl + LPC32XX_INTC_MASK));
+	writel(reg, LPC32XX_INTC_MASK(ctrl));
 }
 
 static void lpc32xx_unmask_irq(unsigned int irq)
@@ -79,9 +79,9 @@ static void lpc32xx_unmask_irq(unsigned int irq)
 
 	get_controller(irq, &ctrl, &mask);
 
-	reg = readl(ctrl + LPC32XX_INTC_MASK);
+	reg = readl(LPC32XX_INTC_MASK(ctrl));
 	reg |= mask;
-	writel(reg, (ctrl + LPC32XX_INTC_MASK));
+	writel(reg, LPC32XX_INTC_MASK(ctrl));
 }
 
 static void lpc32xx_mask_ack_irq(unsigned int irq)
@@ -90,7 +90,7 @@ static void lpc32xx_mask_ack_irq(unsigned int irq)
 
 	get_controller(irq, &ctrl, &mask);
 
-	writel(mask, (ctrl + LPC32XX_INTC_RAW_STAT));
+	writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
 }
 
 static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
@@ -102,45 +102,45 @@ static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
 	switch (type) {
 	case IRQ_TYPE_EDGE_RISING:
 		/* Rising edge sensitive */
-		reg = readl(ctrl + LPC32XX_INTC_POLAR);
+		reg = readl(LPC32XX_INTC_POLAR(ctrl));
 		reg |= mask;
-		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
-		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
+		writel(reg, LPC32XX_INTC_POLAR(ctrl));
+		reg = readl(LPC32XX_INTC_ACT_TYPE(ctrl));
 		reg |= mask;
-		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
+		writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
 		set_irq_handler(irq, handle_edge_irq);
 		break;
 
 	case IRQ_TYPE_EDGE_FALLING:
 		/* Falling edge sensitive */
-		reg = readl(ctrl + LPC32XX_INTC_POLAR);
+		reg = readl(LPC32XX_INTC_POLAR(ctrl));
 		reg &= ~mask;
-		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
-		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
+		writel(reg, LPC32XX_INTC_POLAR(ctrl));
+		reg = readl(LPC32XX_INTC_ACT_TYPE(ctrl));
 		reg |= mask;
-		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
+		writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
 		set_irq_handler(irq, handle_edge_irq);
 		break;
 
 	case IRQ_TYPE_LEVEL_LOW:
 		/* Low level sensitive */
-		reg = readl(ctrl + LPC32XX_INTC_POLAR);
+		reg = readl(LPC32XX_INTC_POLAR(ctrl));
 		reg &= ~mask;
-		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
-		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
+		writel(reg, LPC32XX_INTC_POLAR(ctrl));
+		reg = readl(LPC32XX_INTC_ACT_TYPE(ctrl));
 		reg &= ~mask;
-		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
+		writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
 		set_irq_handler(irq, handle_level_irq);
 		break;
 
 	case IRQ_TYPE_LEVEL_HIGH:
 		/* High level sensitive */
-		reg = readl(ctrl + LPC32XX_INTC_POLAR);
+		reg = readl(LPC32XX_INTC_POLAR(ctrl));
 		reg |= mask;
-		writel(reg, (ctrl + LPC32XX_INTC_POLAR));
-		reg = readl(ctrl + LPC32XX_INTC_ACT_TYPE);
+		writel(reg, LPC32XX_INTC_POLAR(ctrl));
+		reg = readl(LPC32XX_INTC_ACT_TYPE(ctrl));
 		reg &= ~mask;
-		writel(reg, (ctrl + LPC32XX_INTC_ACT_TYPE));
+		writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
 		set_irq_handler(irq, handle_level_irq);
 		break;
 
@@ -198,21 +198,21 @@ void __init lpc32xx_init_irq(void)
 
 	/* Setup MIC */
 	vloc = io_p2v(LPC32XX_MIC_BASE);
-	writel(0, (vloc + LPC32XX_INTC_MASK));
-	writel(MIC_APR_DEFAULT, (vloc + LPC32XX_INTC_POLAR));
-	writel(MIC_ATR_DEFAULT, (vloc + LPC32XX_INTC_ACT_TYPE));
+	writel(0, LPC32XX_INTC_MASK(vloc));
+	writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(vloc));
+	writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(vloc));
 
 	/* Setup SIC1 */
 	vloc = io_p2v(LPC32XX_SIC1_BASE);
-	writel(0, (vloc + LPC32XX_INTC_MASK));
-	writel(SIC1_APR_DEFAULT, (vloc + LPC32XX_INTC_POLAR));
-	writel(SIC1_ATR_DEFAULT, (vloc + LPC32XX_INTC_ACT_TYPE));
+	writel(0, LPC32XX_INTC_MASK(vloc));
+	writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(vloc));
+	writel(SIC1_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(vloc));
 
 	/* Setup SIC2 */
 	vloc = io_p2v(LPC32XX_SIC2_BASE);
-	writel(0, (vloc + LPC32XX_INTC_MASK));
-	writel(SIC2_APR_DEFAULT, (vloc + LPC32XX_INTC_POLAR));
-	writel(SIC2_ATR_DEFAULT, (vloc + LPC32XX_INTC_ACT_TYPE));
+	writel(0, LPC32XX_INTC_MASK(vloc));
+	writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(vloc));
+	writel(SIC2_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(vloc));
 
 	/* Configure supported IRQ's */
 	for (i = 0; i < NR_IRQS; i++) {
@@ -231,7 +231,7 @@ void __init lpc32xx_init_irq(void)
 	/* mask all interrupts except SUBIRQA and SUBFIQ */
 	writel((1 << IRQ_SUB1IRQ) | (1 << IRQ_SUB2IRQ) |
 		(1 << IRQ_SUB1FIQ) | (1 << IRQ_SUB2FIQ),
-		(io_p2v(LPC32XX_MIC_BASE) + LPC32XX_INTC_MASK));
-	writel(0, (io_p2v(LPC32XX_SIC1_BASE) + LPC32XX_INTC_MASK));
-	writel(0, (io_p2v(LPC32XX_SIC2_BASE) + LPC32XX_INTC_MASK));
+		LPC32XX_INTC_MASK(io_p2v(LPC32XX_MIC_BASE)));
+	writel(0, LPC32XX_INTC_MASK(io_p2v(LPC32XX_SIC1_BASE)));
+	writel(0, LPC32XX_INTC_MASK(io_p2v(LPC32XX_SIC2_BASE)));
 }
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 12/16] ARM: LPC32XX: Watchdog reset type and sparse fixes
       [not found] <LPC32XX architecture files (updated)>
                   ` (11 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 11/16] ARM: LPC32XX: Converted interrupt registers " wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 13/16] ARM: LPC32XX: Various fixes with readl/writel types wellsk40 at gmail.com
                   ` (3 subsequent siblings)
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Changed the type used with the watchdog reset writel() function
to use void __iomem *

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/common.c |    7 ++++---
 arch/arm/mach-lpc32xx/common.h |    2 ++
 arch/arm/mach-lpc32xx/irq.c    |    1 +
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 2a97ce0..1efa3d1 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -36,7 +36,8 @@
 #include <mach/platform.h>
 #include "common.h"
 
-#define WDT_IOBASE io_p2v(LPC32XX_WDTIM_BASE)
+#define WDT_IOACCESS(x)	(__force void __iomem *)\
+	io_p2v(LPC32XX_WDTIM_BASE + (x))
 
 /*
  * Watchdog timer
@@ -135,8 +136,8 @@ void lpc32xx_watchdog_reset(void)
 		LPC32XX_CLKPWR_TIMER_CLK_CTRL(CLKPWR_IOBASE));
 
 	/* Instand assert of RESETOUT_N with pulse length 1mS */
-	writel(13000, WDT_IOBASE + 0x18);
-	writel(0x70, WDT_IOBASE + 0xC);
+	writel(13000, WDT_IOACCESS(0x18));
+	writel(0x70, WDT_IOACCESS(0xC));
 }
 
 /*
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 08fdfba..42c758e 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -73,4 +73,6 @@ extern void lpc32xx_get_uid(u32 devid[4]);
 extern void printascii(const char *);
 #endif
 
+extern void lpc32xx_watchdog_reset(void);
+
 #endif
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 3266856..a3ea5cc 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -30,6 +30,7 @@
 #include <mach/irqs.h>
 #include <mach/hardware.h>
 #include <mach/platform.h>
+#include "common.h"
 
 /*
  * Default value represeting the Activation polarity of all internal
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 13/16] ARM: LPC32XX: Various fixes with readl/writel types
       [not found] <LPC32XX architecture files (updated)>
                   ` (12 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 12/16] ARM: LPC32XX: Watchdog reset type and sparse fixes wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-03 10:20   ` Russell King - ARM Linux
  2010-02-02 23:59 ` [PATCH 14/16] ARM: LPC32XX: Several small sparse warning fixed wellsk40 at gmail.com
                   ` (2 subsequent siblings)
  16 siblings, 1 reply; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Fixed types used for readl/writel that would generate sparse
warnings.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/clock.c   |   12 +++++++-----
 arch/arm/mach-lpc32xx/phy3250.c |   16 +++++++++-------
 arch/arm/mach-lpc32xx/pm.c      |    6 +++---
 arch/arm/mach-lpc32xx/serial.c  |   14 +++++++++-----
 4 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 1b8616f..e51e801 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -102,6 +102,8 @@
 #include "clock.h"
 #include "common.h"
 
+#define LCD_REG(x) (__force void __iomem *) (io_p2v(LPC32XX_LCD_BASE) + (x))
+
 static struct clk clk_armpll;
 static struct clk clk_usbpll;
 
@@ -600,7 +602,7 @@ static struct clk clk_i2c1 = {
 static struct clk clk_i2c2 = {
 	.parent		= &clk_pclk,
 	.enable		= &local_onoff_enable,
-	.enable_reg	= (void __iomem *) (USB_OTG_IOBASE + 0xFF4),
+	.enable_reg	= (__force void __iomem *) (USB_OTG_IOBASE + 0xFF4),
 	.enable_mask	= 0x4,
 };
 
@@ -761,7 +763,7 @@ static u32 clcd_get_rate(struct clk *clk)
 		return 0;
 
 	rate = clk_get_rate(clk->parent);
-	tmp = readl((io_p2v(LPC32XX_LCD_BASE)) + CLCD_TIM2);
+	tmp = readl(LCD_REG(CLCD_TIM2));
 
 	/* Only supports internal clocking */
 	if (tmp & TIM2_BCD)
@@ -777,7 +779,7 @@ static int clcd_set_rate(struct clk *clk, u32 rate)
 {
 	u32 tmp, prate, div;
 
-	tmp = readl((io_p2v(LPC32XX_LCD_BASE)) + CLCD_TIM2);
+	tmp = readl(LCD_REG(CLCD_TIM2));
 	prate = clk_get_rate(clk->parent);
 
 	if (rate == prate) {
@@ -795,7 +797,7 @@ static int clcd_set_rate(struct clk *clk, u32 rate)
 		tmp &= ~TIM2_BCD;
 		tmp |= (div & 0x1F);
 		tmp |= (((div >> 5) & 0x1F) << 27);
-		writel(tmp, ((io_p2v(LPC32XX_LCD_BASE)) + CLCD_TIM2));
+		writel(tmp, LCD_REG(CLCD_TIM2));
 		local_onoff_enable(clk, 1);
 	}
 
@@ -1000,7 +1002,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
 };
 
-int __init clk_init(void)
+static int __init clk_init(void)
 {
 	int i;
 
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 80958b9..bd59aa9 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -85,17 +85,18 @@ static int lpc32xx_clcd_setup(struct clcd_fb *fb)
 {
 	dma_addr_t dma;
 
-	fb->fb.screen_base = (void *) NULL;
+	fb->fb.screen_base = (char __iomem *) NULL;
 #ifdef CONFIG_MACH_LPC32XX_IRAM_FOR_CLCD
 	if (PANEL_SIZE <= CONFIG_ARCH_LPC32XX_IRAM_SIZE) {
-		fb->fb.screen_base = (void *) io_p2v(LPC32XX_IRAM_BASE);
+		fb->fb.screen_base = (char __iomem *) io_p2v(LPC32XX_IRAM_BASE);
 		fb->fb.fix.smem_start = (dma_addr_t) LPC32XX_IRAM_BASE;
 	}
 #endif
 
 	if (fb->fb.screen_base == NULL) {
-		fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
-			PANEL_SIZE, &dma, GFP_KERNEL);
+		fb->fb.screen_base = (__force char __iomem *)
+			dma_alloc_writecombine(&fb->dev->dev, PANEL_SIZE,
+			&dma, GFP_KERNEL);
 		fb->fb.fix.smem_start = dma;
 	}
 
@@ -130,7 +131,7 @@ static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 #endif
 
 	return dma_mmap_writecombine(&fb->dev->dev, vma,
-				     fb->fb.screen_base,
+				     (__force void *) fb->fb.screen_base,
 				     fb->fb.fix.smem_start,
 				     fb->fb.fix.smem_len);
 }
@@ -140,11 +141,12 @@ static void lpc32xx_clcd_remove(struct clcd_fb *fb)
 #ifdef CONFIG_MACH_LPC32XX_IRAM_FOR_CLCD
 	if (PANEL_SIZE > CONFIG_ARCH_LPC32XX_IRAM_SIZE)
 		dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
-			fb->fb.screen_base, fb->fb.fix.smem_start);
+			(__force void *) fb->fb.screen_base,
+			fb->fb.fix.smem_start);
 
 #else
 	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
-		fb->fb.screen_base, fb->fb.fix.smem_start);
+		(__force void *) fb->fb.screen_base, fb->fb.fix.smem_start);
 #endif
 }
 
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index 5f0a805..0be1a47 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -146,13 +146,13 @@ static struct platform_suspend_ops lpc32xx_pm_ops = {
 
 #define EMC_DYN_MEM_CTRL_OFS 0x20
 #define EMC_SRMMC           (1 << 3)
-
+#define EMC_CTRL_REG (__force void __iomem *)\
+	(io_p2v(LPC32XX_EMC_BASE) + EMC_DYN_MEM_CTRL_OFS)
 static int __init lpc32xx_pm_init(void)
 {
 	/* Setup SDRAM self-refresh clock to automatically
 	   disable on start of self-refresh */
-	writel(readl(io_p2v(LPC32XX_EMC_BASE) + EMC_DYN_MEM_CTRL_OFS) |
-		EMC_SRMMC, io_p2v(LPC32XX_EMC_BASE) + EMC_DYN_MEM_CTRL_OFS);
+	writel(readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
 
 	/* Allocate some space for temporary IRAM storage */
 	iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_ATOMIC);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index a2b8e12..96d6d1b 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -38,7 +38,8 @@
 static struct plat_serial8250_port serial_std_platform_data[] = {
 #ifdef CONFIG_ARCH_LPC32XX_UART5_ENABLE
 	{
-		.membase        = (void *) io_p2v(LPC32XX_UART5_BASE),
+		.membase        =
+			(__force void __iomem *) io_p2v(LPC32XX_UART5_BASE),
 		.mapbase        = LPC32XX_UART5_BASE,
 		.irq		= IRQ_UART_IIR5,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
@@ -50,7 +51,8 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART3_ENABLE
 	{
-		.membase	= (void *) io_p2v(LPC32XX_UART3_BASE),
+		.membase	=
+			(__force void __iomem *) io_p2v(LPC32XX_UART3_BASE),
 		.mapbase        = LPC32XX_UART3_BASE,
 		.irq		= IRQ_UART_IIR3,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
@@ -62,7 +64,8 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART4_ENABLE
 	{
-		.membase	= (void *) io_p2v(LPC32XX_UART4_BASE),
+		.membase	=
+			(__force void __iomem *) io_p2v(LPC32XX_UART4_BASE),
 		.mapbase        = LPC32XX_UART4_BASE,
 		.irq		= IRQ_UART_IIR4,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
@@ -74,7 +77,8 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 #endif
 #ifdef CONFIG_ARCH_LPC32XX_UART6_ENABLE
 	{
-		.membase	= (void *) io_p2v(LPC32XX_UART6_BASE),
+		.membase	=
+			(__force void __iomem *) io_p2v(LPC32XX_UART6_BASE),
 		.mapbase        = LPC32XX_UART6_BASE,
 		.irq		= IRQ_UART_IIR6,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
@@ -144,7 +148,7 @@ void __init lpc32xx_serial_init(void)
 {
 	u32 tmp, clkmodes = 0;
 	struct clk *clk;
-	void *puart;
+	void __iomem *puart;
 	int i;
 
 	/* UART clocks are off, let clock driver manage them */
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 14/16] ARM: LPC32XX: Several small sparse warning fixed
       [not found] <LPC32XX architecture files (updated)>
                   ` (13 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 13/16] ARM: LPC32XX: Various fixes with readl/writel types wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 15/16] ARM: LPC32XX: Updated device IRQ names with LPC32XX identifier wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 16/16] ARM: LPC32XX: Fix sparse errors on LCD code wellsk40 at gmail.com
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Removed and extra "extern" and added an additional include to
define a function prototype. (sparse warnings)

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/gpiolib.c   |    1 +
 arch/arm/mach-lpc32xx/pm_events.c |    3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
index 13930d4..05556bd 100644
--- a/arch/arm/mach-lpc32xx/gpiolib.c
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -28,6 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
+#include "common.h"
 
 #define GPIOBASE io_p2v(LPC32XX_GPIO_BASE)
 
diff --git a/arch/arm/mach-lpc32xx/pm_events.c b/arch/arm/mach-lpc32xx/pm_events.c
index 835207d..671736c 100644
--- a/arch/arm/mach-lpc32xx/pm_events.c
+++ b/arch/arm/mach-lpc32xx/pm_events.c
@@ -370,8 +370,7 @@ void lpc32xx_event_disable(enum lpc32xx_events event_id)
 		events[event_id].reg);
 }
 
-extern int lpc32xx_event_set(enum lpc32xx_events event_id,
-	int high_edge)
+int lpc32xx_event_set(enum lpc32xx_events event_id, int high_edge)
 {
 	u32 tmp;
 
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 15/16] ARM: LPC32XX: Updated device IRQ names with LPC32XX identifier
       [not found] <LPC32XX architecture files (updated)>
                   ` (14 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 14/16] ARM: LPC32XX: Several small sparse warning fixed wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  2010-02-02 23:59 ` [PATCH 16/16] ARM: LPC32XX: Fix sparse errors on LCD code wellsk40 at gmail.com
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Added _LCP32XX identifier to IRQ names used in the arch area to
identify device specific IRQs.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/common.c            |    6 +-
 arch/arm/mach-lpc32xx/include/mach/irqs.h |  158 ++++++++++++++--------------
 arch/arm/mach-lpc32xx/irq.c               |    4 +-
 arch/arm/mach-lpc32xx/phy3250.c           |    4 +-
 arch/arm/mach-lpc32xx/serial.c            |    8 +-
 arch/arm/mach-lpc32xx/timer.c             |    2 +-
 6 files changed, 91 insertions(+), 91 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 1efa3d1..b925c09 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -63,19 +63,19 @@ struct platform_device watchdog_device = {
 static struct i2c_pnx_data i2c0_data = {
 	.name = I2C_CHIP_NAME "0",
 	.base = LPC32XX_I2C1_BASE,
-	.irq = IRQ_I2C_1,
+	.irq = IRQ_LPC32XX_I2C_1,
 };
 
 static struct i2c_pnx_data i2c1_data = {
 	.name = I2C_CHIP_NAME "1",
 	.base = LPC32XX_I2C2_BASE,
-	.irq = IRQ_I2C_2,
+	.irq = IRQ_LPC32XX_I2C_2,
 };
 
 static struct i2c_pnx_data i2c2_data = {
 	.name = "USB-I2C",
 	.base = LPC32XX_OTG_I2C_BASE,
-	.irq = IRQ_USB_I2C,
+	.irq = IRQ_LPC32XX_USB_I2C,
 };
 
 struct platform_device i2c0_device = {
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
index 157a26c..9ef2720 100644
--- a/arch/arm/mach-lpc32xx/include/mach/irqs.h
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -26,93 +26,93 @@
 /*
  * MIC interrupts
  */
-#define IRQ_SUB1IRQ		0
-#define IRQ_SUB2IRQ		1
-#define IRQ_PWM3		3
-#define IRQ_PWM4		4
-#define IRQ_HSTIMER		5
-#define IRQ_WATCH		6
-#define IRQ_UART_IIR3		7
-#define IRQ_UART_IIR4		8
-#define IRQ_UART_IIR5		9
-#define IRQ_UART_IIR6		10
-#define IRQ_FLASH		11
-#define IRQ_SD1			13
-#define IRQ_LCD			14
-#define IRQ_SD0			15
-#define IRQ_TIMER0		16
-#define IRQ_TIMER1		17
-#define IRQ_TIMER2		18
-#define IRQ_TIMER3		19
-#define IRQ_SSP0		20
-#define IRQ_SSP1		21
-#define IRQ_I2S0		22
-#define IRQ_I2S1		23
-#define IRQ_UART_IIR7		24
-#define IRQ_UART_IIR2		25
-#define IRQ_UART_IIR1		26
-#define IRQ_MSTIMER		27
-#define IRQ_DMA			28
-#define IRQ_ETHERNET		29
-#define IRQ_SUB1FIQ		30
-#define IRQ_SUB2FIQ		31
+#define IRQ_LPC32XX_SUB1IRQ		0
+#define IRQ_LPC32XX_SUB2IRQ		1
+#define IRQ_LPC32XX_PWM3		3
+#define IRQ_LPC32XX_PWM4		4
+#define IRQ_LPC32XX_HSTIMER		5
+#define IRQ_LPC32XX_WATCH		6
+#define IRQ_LPC32XX_UART_IIR3		7
+#define IRQ_LPC32XX_UART_IIR4		8
+#define IRQ_LPC32XX_UART_IIR5		9
+#define IRQ_LPC32XX_UART_IIR6		10
+#define IRQ_LPC32XX_FLASH		11
+#define IRQ_LPC32XX_SD1			13
+#define IRQ_LPC32XX_LCD			14
+#define IRQ_LPC32XX_SD0			15
+#define IRQ_LPC32XX_TIMER0		16
+#define IRQ_LPC32XX_TIMER1		17
+#define IRQ_LPC32XX_TIMER2		18
+#define IRQ_LPC32XX_TIMER3		19
+#define IRQ_LPC32XX_SSP0		20
+#define IRQ_LPC32XX_SSP1		21
+#define IRQ_LPC32XX_I2S0		22
+#define IRQ_LPC32XX_I2S1		23
+#define IRQ_LPC32XX_UART_IIR7		24
+#define IRQ_LPC32XX_UART_IIR2		25
+#define IRQ_LPC32XX_UART_IIR1		26
+#define IRQ_LPC32XX_MSTIMER		27
+#define IRQ_LPC32XX_DMA			28
+#define IRQ_LPC32XX_ETHERNET		29
+#define IRQ_LPC32XX_SUB1FIQ		30
+#define IRQ_LPC32XX_SUB2FIQ		31
 
 /*
  * SIC1 interrupts start at offset 32
  */
-#define IRQ_JTAG_COMM_TX	(32 + 1)
-#define IRQ_JTAG_COMM_RX	(32 + 2)
-#define IRQ_GPI_11		(32 + 4)
-#define IRQ_TS_P		(32 + 6)
-#define IRQ_TS_IRQ		(32 + 7)
-#define IRQ_TS_AUX		(32 + 8)
-#define IRQ_SPI2		(32 + 12)
-#define IRQ_PLLUSB		(32 + 13)
-#define IRQ_PLLHCLK		(32 + 14)
-#define IRQ_PLL397		(32 + 17)
-#define IRQ_I2C_2		(32 + 18)
-#define IRQ_I2C_1		(32 + 19)
-#define IRQ_RTC			(32 + 20)
-#define IRQ_KEY			(32 + 22)
-#define IRQ_SPI1		(32 + 23)
-#define IRQ_SW			(32 + 24)
-#define IRQ_USB_OTG_TIMER	(32 + 25)
-#define IRQ_USB_OTG_ATX		(32 + 26)
-#define IRQ_USB_HOST		(32 + 27)
-#define IRQ_USB_DEV_DMA		(32 + 28)
-#define IRQ_USB_DEV_LP		(32 + 29)
-#define IRQ_USB_DEV_HP		(32 + 30)
-#define IRQ_USB_I2C		(32 + 31)
+#define IRQ_LPC32XX_JTAG_COMM_TX	(32 + 1)
+#define IRQ_LPC32XX_JTAG_COMM_RX	(32 + 2)
+#define IRQ_LPC32XX_GPI_11		(32 + 4)
+#define IRQ_LPC32XX_TS_P		(32 + 6)
+#define IRQ_LPC32XX_TS_IRQ		(32 + 7)
+#define IRQ_LPC32XX_TS_AUX		(32 + 8)
+#define IRQ_LPC32XX_SPI2		(32 + 12)
+#define IRQ_LPC32XX_PLLUSB		(32 + 13)
+#define IRQ_LPC32XX_PLLHCLK		(32 + 14)
+#define IRQ_LPC32XX_PLL397		(32 + 17)
+#define IRQ_LPC32XX_I2C_2		(32 + 18)
+#define IRQ_LPC32XX_I2C_1		(32 + 19)
+#define IRQ_LPC32XX_RTC			(32 + 20)
+#define IRQ_LPC32XX_KEY			(32 + 22)
+#define IRQ_LPC32XX_SPI1		(32 + 23)
+#define IRQ_LPC32XX_SW			(32 + 24)
+#define IRQ_LPC32XX_USB_OTG_TIMER	(32 + 25)
+#define IRQ_LPC32XX_USB_OTG_ATX		(32 + 26)
+#define IRQ_LPC32XX_USB_HOST		(32 + 27)
+#define IRQ_LPC32XX_USB_DEV_DMA		(32 + 28)
+#define IRQ_LPC32XX_USB_DEV_LP		(32 + 29)
+#define IRQ_LPC32XX_USB_DEV_HP		(32 + 30)
+#define IRQ_LPC32XX_USB_I2C		(32 + 31)
 
 /*
  * SIC2 interrupts start at offset 64
  */
-#define IRQ_GPIO_00		(64 + 0)
-#define IRQ_GPIO_01		(64 + 1)
-#define IRQ_GPIO_02		(64 + 2)
-#define IRQ_GPIO_03		(64 + 3)
-#define IRQ_GPIO_04		(64 + 4)
-#define IRQ_GPIO_05		(64 + 5)
-#define IRQ_SPI2_DATAIN		(64 + 6)
-#define IRQ_U2_HCTS		(64 + 7)
-#define IRQ_P0_P1_IRQ		(64 + 8)
-#define IRQ_GPI_08		(64 + 9)
-#define IRQ_GPI_09		(64 + 10)
-#define IRQ_GPI_10		(64 + 11)
-#define IRQ_U7_HCTS		(64 + 12)
-#define IRQ_GPI_07		(64 + 15)
-#define IRQ_SDIO		(64 + 18)
-#define IRQ_U5_RX		(64 + 19)
-#define IRQ_SPI1_DATAIN		(64 + 20)
-#define IRQ_GPI_00		(64 + 22)
-#define IRQ_GPI_01		(64 + 23)
-#define IRQ_GPI_02		(64 + 24)
-#define IRQ_GPI_03		(64 + 25)
-#define IRQ_GPI_04		(64 + 26)
-#define IRQ_GPI_05		(64 + 27)
-#define IRQ_GPI_06		(64 + 28)
-#define IRQ_SYSCLK		(64 + 31)
+#define IRQ_LPC32XX_GPIO_00		(64 + 0)
+#define IRQ_LPC32XX_GPIO_01		(64 + 1)
+#define IRQ_LPC32XX_GPIO_02		(64 + 2)
+#define IRQ_LPC32XX_GPIO_03		(64 + 3)
+#define IRQ_LPC32XX_GPIO_04		(64 + 4)
+#define IRQ_LPC32XX_GPIO_05		(64 + 5)
+#define IRQ_LPC32XX_SPI2_DATAIN		(64 + 6)
+#define IRQ_LPC32XX_U2_HCTS		(64 + 7)
+#define IRQ_LPC32XX_P0_P1_IRQ		(64 + 8)
+#define IRQ_LPC32XX_GPI_08		(64 + 9)
+#define IRQ_LPC32XX_GPI_09		(64 + 10)
+#define IRQ_LPC32XX_GPI_10		(64 + 11)
+#define IRQ_LPC32XX_U7_HCTS		(64 + 12)
+#define IRQ_LPC32XX_GPI_07		(64 + 15)
+#define IRQ_LPC32XX_SDIO		(64 + 18)
+#define IRQ_LPC32XX_U5_RX		(64 + 19)
+#define IRQ_LPC32XX_SPI1_DATAIN		(64 + 20)
+#define IRQ_LPC32XX_GPI_00		(64 + 22)
+#define IRQ_LPC32XX_GPI_01		(64 + 23)
+#define IRQ_LPC32XX_GPI_02		(64 + 24)
+#define IRQ_LPC32XX_GPI_03		(64 + 25)
+#define IRQ_LPC32XX_GPI_04		(64 + 26)
+#define IRQ_LPC32XX_GPI_05		(64 + 27)
+#define IRQ_LPC32XX_GPI_06		(64 + 28)
+#define IRQ_LPC32XX_SYSCLK		(64 + 31)
 
-#define NR_IRQS			96
+#define NR_IRQS				96
 
 #endif
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index a3ea5cc..d583754 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -230,8 +230,8 @@ void __init lpc32xx_init_irq(void)
 		SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
 
 	/* mask all interrupts except SUBIRQA and SUBFIQ */
-	writel((1 << IRQ_SUB1IRQ) | (1 << IRQ_SUB2IRQ) |
-		(1 << IRQ_SUB1FIQ) | (1 << IRQ_SUB2FIQ),
+	writel((1 << IRQ_LPC32XX_SUB1IRQ) | (1 << IRQ_LPC32XX_SUB2IRQ) |
+		(1 << IRQ_LPC32XX_SUB1FIQ) | (1 << IRQ_LPC32XX_SUB2FIQ),
 		LPC32XX_INTC_MASK(io_p2v(LPC32XX_MIC_BASE)));
 	writel(0, LPC32XX_INTC_MASK(io_p2v(LPC32XX_SIC1_BASE)));
 	writel(0, LPC32XX_INTC_MASK(io_p2v(LPC32XX_SIC2_BASE)));
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bd59aa9..846bc33 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -193,7 +193,7 @@ static struct amba_device clcd_device = {
 		.flags			= IORESOURCE_MEM,
 	},
 	.dma_mask			= ~0,
-	.irq				= {IRQ_LCD, NO_IRQ},
+	.irq				= {IRQ_LPC32XX_LCD, NO_IRQ},
 };
 
 /*
@@ -241,7 +241,7 @@ static struct amba_device ssp0_device = {
 		.flags			= IORESOURCE_MEM,
 	},
 	.dma_mask			= ~0,
-	.irq				= {IRQ_SSP0, NO_IRQ},
+	.irq				= {IRQ_LPC32XX_SSP0, NO_IRQ},
 };
 
 /* AT25 driver registration */
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index 96d6d1b..07522db 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -41,7 +41,7 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 		.membase        =
 			(__force void __iomem *) io_p2v(LPC32XX_UART5_BASE),
 		.mapbase        = LPC32XX_UART5_BASE,
-		.irq		= IRQ_UART_IIR5,
+		.irq		= IRQ_LPC32XX_UART_IIR5,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
@@ -54,7 +54,7 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 		.membase	=
 			(__force void __iomem *) io_p2v(LPC32XX_UART3_BASE),
 		.mapbase        = LPC32XX_UART3_BASE,
-		.irq		= IRQ_UART_IIR3,
+		.irq		= IRQ_LPC32XX_UART_IIR3,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
@@ -67,7 +67,7 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 		.membase	=
 			(__force void __iomem *) io_p2v(LPC32XX_UART4_BASE),
 		.mapbase        = LPC32XX_UART4_BASE,
-		.irq		= IRQ_UART_IIR4,
+		.irq		= IRQ_LPC32XX_UART_IIR4,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
@@ -80,7 +80,7 @@ static struct plat_serial8250_port serial_std_platform_data[] = {
 		.membase	=
 			(__force void __iomem *) io_p2v(LPC32XX_UART6_BASE),
 		.mapbase        = LPC32XX_UART6_BASE,
-		.irq		= IRQ_UART_IIR6,
+		.irq		= IRQ_LPC32XX_UART_IIR6,
 		.uartclk	= LPC32XX_MAIN_OSC_FREQ,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM32,
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index cd79017..2c53365 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -164,7 +164,7 @@ static void __init lpc32xx_timer_init(void)
 		LCP32XX_TIMER_MCR(TIMER0_IOBASE));
 
 	/* Setup tick interrupt */
-	setup_irq(IRQ_TIMER0, &lpc32xx_timer_irq);
+	setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
 
 	/* Setup the clockevent structure. */
 	lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 16/16] ARM: LPC32XX: Fix sparse errors on LCD code
       [not found] <LPC32XX architecture files (updated)>
                   ` (15 preceding siblings ...)
  2010-02-02 23:59 ` [PATCH 15/16] ARM: LPC32XX: Updated device IRQ names with LPC32XX identifier wellsk40 at gmail.com
@ 2010-02-02 23:59 ` wellsk40 at gmail.com
  16 siblings, 0 replies; 25+ messages in thread
From: wellsk40 at gmail.com @ 2010-02-02 23:59 UTC (permalink / raw)
  To: linux-arm-kernel

From: Kevin Wells <wellsk40@gmail.com>

Added __force and corrected line length to fix sparse errors
and meet coding requirements.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/phy3250.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 846bc33..c7a6d9f 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -88,7 +88,8 @@ static int lpc32xx_clcd_setup(struct clcd_fb *fb)
 	fb->fb.screen_base = (char __iomem *) NULL;
 #ifdef CONFIG_MACH_LPC32XX_IRAM_FOR_CLCD
 	if (PANEL_SIZE <= CONFIG_ARCH_LPC32XX_IRAM_SIZE) {
-		fb->fb.screen_base = (char __iomem *) io_p2v(LPC32XX_IRAM_BASE);
+		fb->fb.screen_base = (__force char __iomem *)
+			io_p2v(LPC32XX_IRAM_BASE);
 		fb->fb.fix.smem_start = (dma_addr_t) LPC32XX_IRAM_BASE;
 	}
 #endif
-- 
1.6.6

^ permalink raw reply related	[flat|nested] 25+ messages in thread
* [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata
  2010-02-02 23:59 ` [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata wellsk40 at gmail.com
@ 2010-02-03 10:08   ` Russell King - ARM Linux
  2010-02-03 19:25     ` Kevin Wells
  0 siblings, 1 reply; 25+ messages in thread
From: Russell King - ARM Linux @ 2010-02-03 10:08 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Feb 02, 2010 at 03:59:13PM -0800, wellsk40 at gmail.com wrote:
> From: Kevin Wells <wellsk40@gmail.com>
> 
> struct clk looksup[] should not be tagged with the __initdata
> attribute so system functions after bootup can use the clkdev
> support.

Can you roll this into your previous patch set please?

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 02/16] ARM: LPC32XX: removed extra include statement
  2010-02-02 23:59 ` [PATCH 02/16] ARM: LPC32XX: removed extra include statement wellsk40 at gmail.com
@ 2010-02-03 10:08   ` Russell King - ARM Linux
  0 siblings, 0 replies; 25+ messages in thread
From: Russell King - ARM Linux @ 2010-02-03 10:08 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Feb 02, 2010 at 03:59:14PM -0800, wellsk40 at gmail.com wrote:
> From: Kevin Wells <wellsk40@gmail.com>
> 
> The include of <mach/irqs.h> isn't needed in the entry-macro.S
> file.

Ditto.

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem *
  2010-02-02 23:59 ` [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem * wellsk40 at gmail.com
@ 2010-02-03 10:10   ` Russell King - ARM Linux
  2010-02-03 10:18   ` Russell King - ARM Linux
  1 sibling, 0 replies; 25+ messages in thread
From: Russell King - ARM Linux @ 2010-02-03 10:10 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Feb 02, 2010 at 03:59:22PM -0800, wellsk40 at gmail.com wrote:
> From: Kevin Wells <wellsk40@gmail.com>
> 
> Most defined registers addresses used for readl/writel were untyped.
> These have been changed to (void __iomem *).

Just arrange for io_p2v() to return a void __iomem pointer instead of
adding all these casts.  Virtual addresses should where-ever possible
be pointer like rather than integer like.

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem *
  2010-02-02 23:59 ` [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem * wellsk40 at gmail.com
  2010-02-03 10:10   ` Russell King - ARM Linux
@ 2010-02-03 10:18   ` Russell King - ARM Linux
  1 sibling, 0 replies; 25+ messages in thread
From: Russell King - ARM Linux @ 2010-02-03 10:18 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Feb 02, 2010 at 03:59:22PM -0800, wellsk40 at gmail.com wrote:
> diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
> index adc932b..93541f4 100644
> --- a/arch/arm/mach-lpc32xx/include/mach/platform.h
> +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
> @@ -23,6 +23,8 @@
>  #ifndef __ASM_ARCH_PLATFORM_H
>  #define __ASM_ARCH_PLATFORM_H
>  
> +#define IOMEM(x, y)			(__force void __iomem *)((x) + (y))

Hmm, I'd prefer if this wasn't soo different from the definitions found
in other platforms - so maybe one day we can move this to the arch level.

The best definition for it is:

#define IOMEM(x) ((void __iomem *)(unsigned long)(x))

which I believe avoids sparse complaints without having to resort to
__force.

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 13/16] ARM: LPC32XX: Various fixes with readl/writel types
  2010-02-02 23:59 ` [PATCH 13/16] ARM: LPC32XX: Various fixes with readl/writel types wellsk40 at gmail.com
@ 2010-02-03 10:20   ` Russell King - ARM Linux
  0 siblings, 0 replies; 25+ messages in thread
From: Russell King - ARM Linux @ 2010-02-03 10:20 UTC (permalink / raw)
  To: linux-arm-kernel

On Tue, Feb 02, 2010 at 03:59:25PM -0800, wellsk40 at gmail.com wrote:
>  	if (fb->fb.screen_base == NULL) {
> -		fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
> -			PANEL_SIZE, &dma, GFP_KERNEL);
> +		fb->fb.screen_base = (__force char __iomem *)
> +			dma_alloc_writecombine(&fb->dev->dev, PANEL_SIZE,
> +			&dma, GFP_KERNEL);

There are times when putting up with sparse complaints is the right thing
to do, and this is one situation where that is true.

>  		fb->fb.fix.smem_start = dma;
>  	}
>  
> @@ -130,7 +131,7 @@ static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
>  #endif
>  
>  	return dma_mmap_writecombine(&fb->dev->dev, vma,
> -				     fb->fb.screen_base,
> +				     (__force void *) fb->fb.screen_base,

Same here.

>  				     fb->fb.fix.smem_start,
>  				     fb->fb.fix.smem_len);
>  }
> @@ -140,11 +141,12 @@ static void lpc32xx_clcd_remove(struct clcd_fb *fb)
>  #ifdef CONFIG_MACH_LPC32XX_IRAM_FOR_CLCD
>  	if (PANEL_SIZE > CONFIG_ARCH_LPC32XX_IRAM_SIZE)
>  		dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
> -			fb->fb.screen_base, fb->fb.fix.smem_start);
> +			(__force void *) fb->fb.screen_base,
> +			fb->fb.fix.smem_start);

and here.

>  
>  #else
>  	dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
> -		fb->fb.screen_base, fb->fb.fix.smem_start);
> +		(__force void *) fb->fb.screen_base, fb->fb.fix.smem_start);

and here.

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata
  2010-02-03 10:08   ` Russell King - ARM Linux
@ 2010-02-03 19:25     ` Kevin Wells
  2010-02-04  9:59       ` Uwe Kleine-König
  0 siblings, 1 reply; 25+ messages in thread
From: Kevin Wells @ 2010-02-03 19:25 UTC (permalink / raw)
  To: linux-arm-kernel

> 
> On Tue, Feb 02, 2010 at 03:59:13PM -0800, wellsk40 at gmail.com wrote:
> > From: Kevin Wells <wellsk40@gmail.com>
> >
> > struct clk looksup[] should not be tagged with the __initdata
> > attribute so system functions after bootup can use the clkdev
> > support.
> 
> Can you roll this into your previous patch set please?

Hi Russell,

I'll fix the many more comments from the reviews and put up another
(hopefully last) set of patches that are sparse and bisect safe and
hopefully review safe. I would like to get these in patch tracker if
all goes good.

thanks,
Kevin

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata
  2010-02-03 19:25     ` Kevin Wells
@ 2010-02-04  9:59       ` Uwe Kleine-König
  0 siblings, 0 replies; 25+ messages in thread
From: Uwe Kleine-König @ 2010-02-04  9:59 UTC (permalink / raw)
  To: linux-arm-kernel

Hey Kevin,

On Wed, Feb 03, 2010 at 08:25:10PM +0100, Kevin Wells wrote:
> > 
> > On Tue, Feb 02, 2010 at 03:59:13PM -0800, wellsk40 at gmail.com wrote:
> > > From: Kevin Wells <wellsk40@gmail.com>
> > >
> > > struct clk looksup[] should not be tagged with the __initdata
> > > attribute so system functions after bootup can use the clkdev
> > > support.
s/looksup/lookups/

> > 
> > Can you roll this into your previous patch set please?
> 
> Hi Russell,
> 
> I'll fix the many more comments from the reviews and put up another
> (hopefully last) set of patches that are sparse and bisect safe and
> hopefully review safe. I would like to get these in patch tracker if
> all goes good.
Can you please make sure to have all mails in one thread?  That would
make it easier for me to find them all.

Thanks
Uwe

-- 
Pengutronix e.K.                              | Uwe Kleine-K?nig            |
Industrial Linux Solutions                    | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 11/16] ARM: LPC32XX: Converted interrupt registers to void __iomem *
  2010-02-02 23:59 ` [PATCH 11/16] ARM: LPC32XX: Converted interrupt registers " wellsk40 at gmail.com
@ 2010-02-04 10:05   ` Uwe Kleine-König
  0 siblings, 0 replies; 25+ messages in thread
From: Uwe Kleine-König @ 2010-02-04 10:05 UTC (permalink / raw)
  To: linux-arm-kernel

Hello Kevin,

On Tue, Feb 02, 2010 at 03:59:23PM -0800, wellsk40 at gmail.com wrote:
> From: Kevin Wells <wellsk40@gmail.com>
> 
> Added register access macros (similar to other register accesses).
> Updated irq handler to use new access macros.
> 
> Signed-off-by: Kevin Wells <wellsk40@gmail.com>
> ---
>  arch/arm/mach-lpc32xx/include/mach/entry-macro.S |    6 +-
>  arch/arm/mach-lpc32xx/include/mach/platform.h    |   12 ++--
>  arch/arm/mach-lpc32xx/irq.c                      |   66 +++++++++++-----------
>  3 files changed, 42 insertions(+), 42 deletions(-)
> 
> diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
> index 25f2adc..9626bac 100644
> --- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
> +++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
> @@ -39,7 +39,7 @@
>  	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
>  	/* Get MIC status first */
>  	ldr	\base, =IO_ADDRESS(LPC32XX_MIC_BASE)
> -	ldr	\irqstat, [\base, #LPC32XX_INTC_STAT]
> +	ldr	\irqstat, [\base, #8]
I consider this a step back.  What about

	ldr	\irqstat, [\base, #(LPC32XX_INTC_STAT - LPC32XX_MIC_BASE)]

?

Best regards
Uwe

-- 
Pengutronix e.K.                              | Uwe Kleine-K?nig            |
Industrial Linux Solutions                    | http://www.pengutronix.de/  |

^ permalink raw reply	[flat|nested] 25+ messages in thread
end of thread, other threads:[~2010-02-04 10:05 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
     [not found] <LPC32XX architecture files (updated)>
2010-02-02 23:59 ` LPC32XX arch updates from developer comments wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 01/16] ARM: LPC32XX: clock lookups array should not be tagged __initdata wellsk40 at gmail.com
2010-02-03 10:08   ` Russell King - ARM Linux
2010-02-03 19:25     ` Kevin Wells
2010-02-04  9:59       ` Uwe Kleine-König
2010-02-02 23:59 ` [PATCH 02/16] ARM: LPC32XX: removed extra include statement wellsk40 at gmail.com
2010-02-03 10:08   ` Russell King - ARM Linux
2010-02-02 23:59 ` [PATCH 03/16] ARM: LPC32XX: Added LPC32XX identifier to high level macro names wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 04/16] ARM: LPC32XX: Added LXP32XX identified to CLKPWR register field macros wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 05/16] ARM: LPC32XX: Added LPC32XX identifier to INTC " wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 06/16] ARM: LPC32XX: Added LPC32XX identifier to TIMER " wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 07/16] ARM: LPC32XX: Added LPC32XX identifier to UART " wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 08/16] ARM: LPC32XX: Added LPC32XX identifier to GPIO " wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 09/16] ARM: LPC32XX: LPC32XX macro name changes and local macro use wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 10/16] ARM: LPC32XX: Converted most register types to void __iomem * wellsk40 at gmail.com
2010-02-03 10:10   ` Russell King - ARM Linux
2010-02-03 10:18   ` Russell King - ARM Linux
2010-02-02 23:59 ` [PATCH 11/16] ARM: LPC32XX: Converted interrupt registers " wellsk40 at gmail.com
2010-02-04 10:05   ` Uwe Kleine-König
2010-02-02 23:59 ` [PATCH 12/16] ARM: LPC32XX: Watchdog reset type and sparse fixes wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 13/16] ARM: LPC32XX: Various fixes with readl/writel types wellsk40 at gmail.com
2010-02-03 10:20   ` Russell King - ARM Linux
2010-02-02 23:59 ` [PATCH 14/16] ARM: LPC32XX: Several small sparse warning fixed wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 15/16] ARM: LPC32XX: Updated device IRQ names with LPC32XX identifier wellsk40 at gmail.com
2010-02-02 23:59 ` [PATCH 16/16] ARM: LPC32XX: Fix sparse errors on LCD code wellsk40 at gmail.com

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