From: wellsk40@gmail.com (wellsk40 at gmail.com)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 02/13] ARM: LPC32XX: Debug and IRQ macros
Date: Fri, 19 Feb 2010 15:25:58 -0800 [thread overview]
Message-ID: <1266621969-28847-3-git-send-email-wellsk40@gmail.com> (raw)
In-Reply-To: <1266621969-28847-1-git-send-email-wellsk40@gmail.com>
From: Kevin Wells <wellsk40@gmail.com>
Debug (printascii) and IRQ handler macros for the LPC32XX
architecture
Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
arch/arm/mach-lpc32xx/include/mach/debug-macro.S | 54 ++++++++++++++++++++++
arch/arm/mach-lpc32xx/include/mach/entry-macro.S | 47 +++++++++++++++++++
2 files changed, 101 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
new file mode 100644
index 0000000..66b7acc
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#define LPC32XX_UART_DLL_FIFO_OFS 0x00
+#define LPC32XX_UART_LSR_OFS 0x14
+
+#define LPC32XX_UART_DEBUG_BASE LPC32XX_UART5_BASE
+
+/*
+ * Debug output is hardcoded to standard UART 5
+*/
+
+ .macro addruart,rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ ldreq \rx, =LPC32XX_UART_DEBUG_BASE @ physical
+ ldrne \rx, =IO_ADDRESS(LPCLPC32XX_UART_DEBUG_BASE) @ virtual
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #LPC32XX_UART_DLL_FIFO_OFS]
+ .endm
+
+ .macro busyuart,rd,rx
+1002:
+ ldr \rd, [\rx, #LPC32XX_UART_LSR_OFS]
+ tst \rd, #(1 << 6)
+ beq 1002b
+ .endm
+
+ .macro waituart,rd,rx
+1001:
+ ldr \rd, [\rx, #LPC32XX_UART_LSR_OFS]
+ tst \rd, #(1 << 5)
+ beq 1001b
+ .endm
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
new file mode 100644
index 0000000..870227c
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+/*
+ * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
+ * as set if an interrupt is pending.
+ */
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
+ clz \irqnr, \irqstat
+ rsb \irqnr, \irqnr, #31
+ teq \irqstat, #0
+ .endm
+
+ .macro irq_prio_table
+ .endm
+
--
1.6.6
next prev parent reply other threads:[~2010-02-19 23:25 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-02-19 23:25 LPC32XX architecture files (updated v4) wellsk40 at gmail.com
2010-02-19 23:25 ` [PATCH 01/13] ARM: LPC32XX: Initial architecture header files wellsk40 at gmail.com
2010-02-20 16:12 ` Uwe Kleine-König
[not found] ` <a08234131002201112x66a595c4j235bf1a31aef4f92@mail.gmail.com>
2010-02-20 19:14 ` Kevin Wells
2010-02-20 19:17 ` Kevin Wells
2010-02-22 21:41 ` Kevin Wells
2010-02-23 8:02 ` Uwe Kleine-König
2010-02-19 23:25 ` wellsk40 at gmail.com [this message]
2010-02-19 23:25 ` [PATCH 03/13] ARM: LPC32XX: Clock driver wellsk40 at gmail.com
2010-02-20 16:33 ` Russell King - ARM Linux
2010-02-23 21:28 ` Kevin Wells
2010-02-19 23:26 ` [PATCH 04/13] ARM: LPC32XX: GPIO, timer, and IRQ drivers wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 05/13] ARM: LPC32XX: System suspend support wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 06/13] ARM: LPC32XX: Serial support code wellsk40 at gmail.com
2010-02-20 16:34 ` Russell King - ARM Linux
2010-02-19 23:26 ` [PATCH 07/13] ARM: LPC32XX: Misc support functions wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 08/13] ARM: LPC32XX: Phytec 3250 platform support wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 09/13] ARM: LPC32XX: Arch config menu supoport and makefiles wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 10/13] ARM: LPC32XX: Default PHY3250 kernel config (ramdisk) wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 11/13] ARM: Add support for the LPC32XX arch wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 12/13] i2c: " wellsk40 at gmail.com
2010-02-19 23:26 ` [PATCH 13/13] WATCHDOG: " wellsk40 at gmail.com
-- strict thread matches above, loose matches on Subject: below --
2010-02-26 23:53 LPC32XX architecture files (updated v5) wellsk40 at gmail.com
2010-02-26 23:53 ` [PATCH 02/13] ARM: LPC32XX: Debug and IRQ macros wellsk40 at gmail.com
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