From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] arm: invalidate TLBs when enabling mmu
Date: Tue, 09 Mar 2010 16:45:34 +0000 [thread overview]
Message-ID: <1268153134.1000.14.camel@e102109-lin.cambridge.arm.com> (raw)
In-Reply-To: <1268143623-22361-3-git-send-email-saeed@marvell.com>
On Tue, 2010-03-09 at 14:07 +0000, Saeed Bishara wrote:
> Signed-off-by: Saeed Bishara <saeed@marvell.com>
> ---
> arch/arm/boot/compressed/head.S | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/head.S
> b/arch/arm/boot/compressed/head.S
> index 4fddc50..a1ab79f 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -489,6 +489,7 @@ __armv7_mmu_cache_on:
> mcr p15, 0, r0, c1, c0, 0 @ load control
> register
> mrc p15, 0, r0, c1, c0, 0 @ and read it back
> mov r0, #0
> + mcr p15, 0, r0, c8, c7, 0 @ invalidate I,D TLBs
> mcr p15, 0, r0, c7, c5, 4 @ ISB
> mov pc, r12
The TLB invalidating is done earlier in the __armv7_mmu_cache_on
function, why do you need to do it again?
--
Catalin
next prev parent reply other threads:[~2010-03-09 16:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-09 14:07 [PATCH 0/2] arm: fix kexec for ARMv7 Saeed Bishara
2010-03-09 14:07 ` [PATCH 1/2] arm: disable L2 cache in the v7 finish function Saeed Bishara
2010-03-09 14:07 ` [PATCH 2/2] arm: invalidate TLBs when enabling mmu Saeed Bishara
2010-03-09 16:45 ` Catalin Marinas [this message]
2010-04-14 17:49 ` Eric Miao
2010-04-14 17:56 ` Bryan Wu
2010-04-14 18:27 ` Russell King - ARM Linux
2010-04-15 12:24 ` Eric Miao
2010-04-15 12:24 ` Eric Miao
2010-04-15 22:36 ` Russell King - ARM Linux
2010-03-09 16:43 ` [PATCH 1/2] arm: disable L2 cache in the v7 finish function Catalin Marinas
2010-03-10 21:55 ` Tony Lindgren
2010-03-10 21:53 ` Tony Lindgren
2010-03-19 19:54 ` Woodruff, Richard
2010-03-22 21:00 ` Tony Lindgren
2010-03-24 8:27 ` Eric Miao
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