[PATCH 0/6] davinci fixes for 2.6.34-rc

[PATCH 0/6] davinci fixes for 2.6.34-rc

[Kevin Hilman]

This series of davinci fixes is targeted for the next 2.6.34-rc,
and are also available in the 'davinci-fixes' branch of:

git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git

Kevin


Brian Niebuhr (1):
  davinci: edma: clear events in edma_start()

Kevin Hilman (4):
  davinci: timers: don't enable timer until clocksource is initialized
  davinci: DM365: fix duplicate default IRQ priorities
  davinci: misc cleanups from sparse
  davinci: sparse: gpio: void casting

Sekhar Nori (1):
  davinci: da8xx/omap-l1: fix build error when CONFIG_DAVINCI_MUX is
    undefined

 arch/arm/mach-davinci/board-dm644x-evm.c   |    2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c  |    2 +-
 arch/arm/mach-davinci/board-sffsdr.c       |    2 +-
 arch/arm/mach-davinci/cdce949.c            |    1 +
 arch/arm/mach-davinci/clock.c              |    1 +
 arch/arm/mach-davinci/devices.c            |    2 +
 arch/arm/mach-davinci/dm355.c              |    2 +-
 arch/arm/mach-davinci/dm365.c              |    3 +-
 arch/arm/mach-davinci/dm644x.c             |    4 +-
 arch/arm/mach-davinci/dm646x.c             |    6 ++--
 arch/arm/mach-davinci/dma.c                |    3 +-
 arch/arm/mach-davinci/gpio.c               |   41 +++++++++++++++++-----------
 arch/arm/mach-davinci/include/mach/da8xx.h |    4 +++
 arch/arm/mach-davinci/include/mach/gpio.h  |    8 +++---
 arch/arm/mach-davinci/mux.c                |    1 +
 arch/arm/mach-davinci/time.c               |    6 +++-
 16 files changed, 54 insertions(+), 34 deletions(-)

[PATCH 1/6] davinci: timers: don't enable timer until clocksource is initialized

[Kevin Hilman]

On da830, when the same timer is used for clocksource and clockevent,
the timer can be started before the clockevent is
registered/initialzed.  This creates a window where a timer
interrupt might fire before the clockevent handler has been
setup and causes a crash.

This patch moves the actual enable/start of the timer after
the clockevent has ben registered.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/time.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 42d985b..9e0b106 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -253,8 +253,6 @@ static void __init timer_init(void)
 			irq = USING_COMPARE(t) ? dtip[i].cmp_irq : irq;
 			setup_irq(irq, &t->irqaction);
 		}
-
-		timer32_config(&timers[i]);
 	}
 }
 
@@ -331,6 +329,7 @@ static void __init davinci_timer_init(void)
 	unsigned int clocksource_id;
 	static char err[] __initdata = KERN_ERR
 		"%s: can't register clocksource!\n";
+	int i;
 
 	clockevent_id = soc_info->timer_info->clockevent_id;
 	clocksource_id = soc_info->timer_info->clocksource_id;
@@ -389,6 +388,9 @@ static void __init davinci_timer_init(void)
 
 	clockevent_davinci.cpumask = cpumask_of(0);
 	clockevents_register_device(&clockevent_davinci);
+
+	for (i=0; i< ARRAY_SIZE(timers); i++)
+		timer32_config(&timers[i]);
 }
 
 struct sys_timer davinci_timer = {
-- 
1.7.0.2

[PATCH 2/6] davinci: da8xx/omap-l1: fix build error when CONFIG_DAVINCI_MUX is undefined

[Kevin Hilman]

From: Sekhar Nori <nsekhar@ti.com>

The da8xx/omap-l1 boards refuse to build when CONFIG_DAVINCI_MUX is undefined
because arch/arm/mach-davinci/mux.c:da8xx_pinmux_setup() is not defined.

This patch fixes this issue. This is build tested with davinci_all_defconfig
and da8xx_omapl_defconfig and boot tested on DA830 EVM.

Reported-by: Shanmuga Sundaram Mahendran <shanmuga@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/include/mach/da8xx.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index cc9be7f..b87a6ba 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -144,6 +144,10 @@ extern const short da850_mmcsd0_pins[];
 extern const short da850_nand_pins[];
 extern const short da850_nor_pins[];
 
+#ifdef CONFIG_DAVINCI_MUX
 int da8xx_pinmux_setup(const short pins[]);
+#else
+static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
+#endif
 
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
-- 
1.7.0.2

[PATCH 3/6] davinci: edma: clear events in edma_start()

[Kevin Hilman]

From: Brian Niebuhr <bniebuhr3@gmail.com>

This patch fixes an issue where a DMA channel can erroneously process an
event generated by a previous transfer.  A failure case is where DMA is
being used for SPI transmit and receive channels on OMAP L138.  In this
case there is a single bit that controls all event generation from the
SPI peripheral.  Therefore it is possible that between when edma_stop()
has been called for the transmit channel on a previous transfer and
edma_start() is called for the transmit channel on a subsequent transfer,
that a transmit event has been generated.

The fix is to clear events in edma_start().  This prevents false events
from being processed when events are enabled for that channel.

Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/dma.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 15dd886..260485c 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -1266,7 +1266,8 @@ int edma_start(unsigned channel)
 		/* EDMA channel with event association */
 		pr_debug("EDMA: ER%d %08x\n", j,
 			edma_shadow0_read_array(ctlr, SH_ER, j));
-		/* Clear any pending error */
+		/* Clear any pending event or error */
+		edma_write_array(ctlr, EDMA_ECR, j, mask);
 		edma_write_array(ctlr, EDMA_EMCR, j, mask);
 		/* Clear any SER */
 		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
-- 
1.7.0.2

[PATCH 4/6] davinci: DM365: fix duplicate default IRQ priorities

[Kevin Hilman]

IRQ 29 has two possible interrupts DDRINT and RTC, but having both in
the default priority table is confusing (and triggers a warning from
sparse.)

This patch removes the lower priority DDRINT from the default priority
table leaving the RTC setting as the default.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/dm365.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 27772e1..0d6ee58 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -758,7 +758,6 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 	[IRQ_MMCINT]			= 7,
 	[IRQ_DM365_MMCINT1]		= 7,
 	[IRQ_DM365_PWMINT3]		= 7,
-	[IRQ_DDRINT]			= 4,
 	[IRQ_AEMIFINT]			= 2,
 	[IRQ_DM365_SDIOINT1]		= 2,
 	[IRQ_TINT0_TINT12]		= 7,
-- 
1.7.0.2

[PATCH 5/6] davinci: misc cleanups from sparse

[Kevin Hilman]

- Convert data/functions to static
- include headers for missing declarations
- pointer cleanups:  struct foo *__iomem f --> struct foo __iomem *f;

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/board-dm644x-evm.c  |    2 +-
 arch/arm/mach-davinci/board-neuros-osd2.c |    2 +-
 arch/arm/mach-davinci/board-sffsdr.c      |    2 +-
 arch/arm/mach-davinci/cdce949.c           |    1 +
 arch/arm/mach-davinci/clock.c             |    1 +
 arch/arm/mach-davinci/devices.c           |    2 ++
 arch/arm/mach-davinci/dm355.c             |    2 +-
 arch/arm/mach-davinci/dm365.c             |    2 +-
 arch/arm/mach-davinci/dm644x.c            |    4 ++--
 arch/arm/mach-davinci/dm646x.c            |    6 +++---
 arch/arm/mach-davinci/gpio.c              |   24 ++++++++++++------------
 arch/arm/mach-davinci/include/mach/gpio.h |    8 ++++----
 arch/arm/mach-davinci/mux.c               |    1 +
 13 files changed, 31 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 976e11b..95cef1f 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -111,7 +111,7 @@ static struct platform_device davinci_evm_norflash_device = {
  * It may used instead of the (default) NOR chip to boot, using TI's
  * tools to install the secondary boot loader (UBL) and U-Boot.
  */
-struct mtd_partition davinci_evm_nandflash_partition[] = {
+static struct mtd_partition davinci_evm_nandflash_partition[] = {
 	/* Bootloader layout depends on whose u-boot is installed, but we
 	 * can hide all the details.
 	 *  - block 0 for u-boot environment ... in mainline u-boot
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index bd9ca07..1fadc68 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -60,7 +60,7 @@
 
 #define NAND_BLOCK_SIZE		SZ_128K
 
-struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
+static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
 	{
 		/* UBL (a few copies) plus U-Boot */
 		.name		= "bootloader",
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 08d373b..a7cf810 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -48,7 +48,7 @@
 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
 
-struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
+static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
 	/* U-Boot Environment: Block 0
 	 * UBL:                Block 1
 	 * U-Boot:             Blocks 6-7 (256 kb)
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
index aec3756..ba8b12b 100644
--- a/arch/arm/mach-davinci/cdce949.c
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -19,6 +19,7 @@
 #include <linux/i2c.h>
 
 #include <mach/clock.h>
+#include <mach/cdce949.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index bf6218e..058c77f 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -22,6 +22,7 @@
 
 #include <mach/hardware.h>
 
+#include <mach/clock.h>
 #include <mach/psc.h>
 #include <mach/cputype.h>
 #include "clock.h"
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 1479496..ef28080 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -23,6 +23,8 @@
 #include <mach/mmc.h>
 #include <mach/time.h>
 
+#include "clock.h"
+
 #define DAVINCI_I2C_BASE	     0x01C21000
 #define DAVINCI_MMCSD0_BASE	     0x01E10000
 #define DM355_MMCSD0_BASE	     0x01E11000
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 3dc0a88..5efce70 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -798,7 +798,7 @@ static void __iomem *dm355_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm355_timer_info = {
+static struct davinci_timer_info dm355_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0d6ee58..871be5a 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1010,7 +1010,7 @@ static void __iomem *dm365_psc_bases[] = {
 	IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 };
 
-struct davinci_timer_info dm365_timer_info = {
+static struct davinci_timer_info dm365_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 2f2ae8b..23cbe9d 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -277,7 +277,7 @@ static struct clk timer2_clk = {
 	.usecount = 1,              /* REVISIT: why cant' this be disabled? */
 };
 
-struct clk_lookup dm644x_clks[] = {
+static struct clk_lookup dm644x_clks[] = {
 	CLK(NULL, "ref", &ref_clk),
 	CLK(NULL, "pll1", &pll1_clk),
 	CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -687,7 +687,7 @@ static void __iomem *dm644x_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm644x_timer_info = {
+static struct davinci_timer_info dm644x_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 893baf4..b67b997 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -311,7 +311,7 @@ static struct clk vpif1_clk = {
 	.flags = ALWAYS_ENABLED,
 };
 
-struct clk_lookup dm646x_clks[] = {
+static struct clk_lookup dm646x_clks[] = {
 	CLK(NULL, "ref", &ref_clk),
 	CLK(NULL, "aux", &aux_clkin),
 	CLK(NULL, "pll1", &pll1_clk),
@@ -797,7 +797,7 @@ static void __iomem *dm646x_psc_bases[] = {
  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
  * T1_TOP: Timer 1, top   :  <unused>
  */
-struct davinci_timer_info dm646x_timer_info = {
+static struct davinci_timer_info dm646x_timer_info = {
 	.timers		= davinci_timer_instance,
 	.clockevent_id	= T0_BOT,
 	.clocksource_id	= T0_TOP,
@@ -867,7 +867,7 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
 	.sram_len		= SZ_32K,
 };
 
-void __init dm646x_init_ide()
+void __init dm646x_init_ide(void)
 {
 	davinci_cfg_reg(DM646X_ATAEN);
 	platform_device_register(&ide_dev);
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 744755b..3f77062 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -24,14 +24,14 @@ static DEFINE_SPINLOCK(gpio_lock);
 
 struct davinci_gpio {
 	struct gpio_chip	chip;
-	struct gpio_controller	*__iomem regs;
+	struct gpio_controller	__iomem *regs;
 	int			irq_base;
 };
 
 static struct davinci_gpio chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
 
 /* create a non-inlined version */
-static struct gpio_controller __iomem * __init gpio2controller(unsigned gpio)
+static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
 {
 	return __gpio_to_controller(gpio);
 }
@@ -48,7 +48,7 @@ static int __init davinci_gpio_irq_setup(void);
 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
 
 	spin_lock(&gpio_lock);
@@ -70,7 +70,7 @@ static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 
 	return (1 << offset) & __raw_readl(&g->in_data);
 }
@@ -79,7 +79,7 @@ static int
 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 	u32 temp;
 	u32 mask = 1 << offset;
 
@@ -99,7 +99,7 @@ static void
 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
 	struct davinci_gpio *d = container_of(chip, struct davinci_gpio, chip);
-	struct gpio_controller *__iomem g = d->regs;
+	struct gpio_controller __iomem *g = d->regs;
 
 	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
 }
@@ -161,7 +161,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -170,7 +170,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -186,7 +186,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +215,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -276,7 +276,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller *__iomem g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -305,7 +305,7 @@ static int __init davinci_gpio_irq_setup(void)
 	u32		binten = 0;
 	unsigned	ngpio, bank_irq;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
-	struct gpio_controller	*__iomem g;
+	struct gpio_controller	__iomem *g;
 
 	ngpio = soc_info->gpio_num;
 
diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h
index f3b8ef8..0099e6e 100644
--- a/arch/arm/mach-davinci/include/mach/gpio.h
+++ b/arch/arm/mach-davinci/include/mach/gpio.h
@@ -67,10 +67,10 @@ struct gpio_controller {
  *
  * These are NOT part of the cross-platform GPIO interface
  */
-static inline struct gpio_controller *__iomem
+static inline struct gpio_controller __iomem *
 __gpio_to_controller(unsigned gpio)
 {
-	void *__iomem ptr;
+	void __iomem *ptr;
 	void __iomem *base = davinci_soc_info.gpio_base;
 
 	if (gpio < 32 * 1)
@@ -102,7 +102,7 @@ static inline u32 __gpio_mask(unsigned gpio)
 static inline void gpio_set_value(unsigned gpio, int value)
 {
 	if (__builtin_constant_p(value) && gpio < DAVINCI_N_GPIO) {
-		struct gpio_controller	*__iomem g;
+		struct gpio_controller	__iomem *g;
 		u32			mask;
 
 		g = __gpio_to_controller(gpio);
@@ -128,7 +128,7 @@ static inline void gpio_set_value(unsigned gpio, int value)
  */
 static inline int gpio_get_value(unsigned gpio)
 {
-	struct gpio_controller	*__iomem g;
+	struct gpio_controller	__iomem *g;
 
 	if (!__builtin_constant_p(gpio) || gpio >= DAVINCI_N_GPIO)
 		return __gpio_get_value(gpio);
diff --git a/arch/arm/mach-davinci/mux.c b/arch/arm/mach-davinci/mux.c
index f757e83..c942c89 100644
--- a/arch/arm/mach-davinci/mux.c
+++ b/arch/arm/mach-davinci/mux.c
@@ -21,6 +21,7 @@
 
 #include <mach/mux.h>
 #include <mach/common.h>
+#include <mach/da8xx.h>
 
 /*
  * Sets the DAVINCI MUX register based on the table
-- 
1.7.0.2

[PATCH 6/6] davinci: sparse: gpio: void casting

[Kevin Hilman]

Cleanup usage of void pointers when using genirq.  genirq API
takes and returns void *, where this GPIO API is using those
as __iomem pointers.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-davinci/gpio.c |   27 ++++++++++++++++++---------
 1 files changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 3f77062..5476ad1 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -36,6 +36,15 @@ static struct gpio_controller __iomem __init *gpio2controller(unsigned gpio)
 	return __gpio_to_controller(gpio);
 }
 
+static inline struct gpio_controller __iomem *irq2controller(int irq)
+{
+	struct gpio_controller __iomem *g;
+
+	g = (__force struct gpio_controller __iomem *)get_irq_chip_data(irq);
+
+	return g;
+}
+
 static int __init davinci_gpio_irq_setup(void);
 
 /*--------------------------------------------------------------------------*/
@@ -161,7 +170,7 @@ pure_initcall(davinci_gpio_setup);
 
 static void gpio_irq_disable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	__raw_writel(mask, &g->clr_falling);
@@ -170,7 +179,7 @@ static void gpio_irq_disable(unsigned irq)
 
 static void gpio_irq_enable(unsigned irq)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 	unsigned status = irq_desc[irq].status;
 
@@ -186,7 +195,7 @@ static void gpio_irq_enable(unsigned irq)
 
 static int gpio_irq_type(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -215,7 +224,7 @@ static struct irq_chip gpio_irqchip = {
 static void
 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = 0xffff;
 
 	/* we only care about one bank */
@@ -276,7 +285,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 
 static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
 {
-	struct gpio_controller __iomem *g = get_irq_chip_data(irq);
+	struct gpio_controller __iomem *g = irq2controller(irq);
 	u32 mask = (u32) get_irq_data(irq);
 
 	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
@@ -362,7 +371,7 @@ static int __init davinci_gpio_irq_setup(void)
 		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
 			set_irq_chip(irq, &gpio_irqchip_unbanked);
 			set_irq_data(irq, (void *) __gpio_mask(gpio));
-			set_irq_chip_data(irq, g);
+			set_irq_chip_data(irq, (__force void *) g);
 			irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
 		}
 
@@ -385,12 +394,12 @@ static int __init davinci_gpio_irq_setup(void)
 
 		/* set up all irqs in this bank */
 		set_irq_chained_handler(bank_irq, gpio_irq_handler);
-		set_irq_chip_data(bank_irq, g);
-		set_irq_data(bank_irq, (void *)irq);
+		set_irq_chip_data(bank_irq, (__force void *) g);
+		set_irq_data(bank_irq, (void *) irq);
 
 		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
 			set_irq_chip(irq, &gpio_irqchip);
-			set_irq_chip_data(irq, g);
+			set_irq_chip_data(irq, (__force void *) g);
 			set_irq_data(irq, (void *) __gpio_mask(gpio));
 			set_irq_handler(irq, handle_simple_irq);
 			set_irq_flags(irq, IRQF_VALID);
-- 
1.7.0.2

[PATCH 3/6] davinci: edma: clear events in edma_start()

[stanley.miao]

This patch causes that the sound can not work normally on OMAP_L138.

Stanley.

Kevin Hilman wrote:
> From: Brian Niebuhr <bniebuhr3@gmail.com>
>
> This patch fixes an issue where a DMA channel can erroneously process an
> event generated by a previous transfer.  A failure case is where DMA is
> being used for SPI transmit and receive channels on OMAP L138.  In this
> case there is a single bit that controls all event generation from the
> SPI peripheral.  Therefore it is possible that between when edma_stop()
> has been called for the transmit channel on a previous transfer and
> edma_start() is called for the transmit channel on a subsequent transfer,
> that a transmit event has been generated.
>
> The fix is to clear events in edma_start().  This prevents false events
> from being processed when events are enabled for that channel.
>
> Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com>
> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
> ---
>  arch/arm/mach-davinci/dma.c |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
> index 15dd886..260485c 100644
> --- a/arch/arm/mach-davinci/dma.c
> +++ b/arch/arm/mach-davinci/dma.c
> @@ -1266,7 +1266,8 @@ int edma_start(unsigned channel)
>  		/* EDMA channel with event association */
>  		pr_debug("EDMA: ER%d %08x\n", j,
>  			edma_shadow0_read_array(ctlr, SH_ER, j));
> -		/* Clear any pending error */
> +		/* Clear any pending event or error */
> +		edma_write_array(ctlr, EDMA_ECR, j, mask);
>  		edma_write_array(ctlr, EDMA_EMCR, j, mask);
>  		/* Clear any SER */
>  		edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
>   

[PATCH 3/6] davinci: edma: clear events in edma_start()

[Kevin Hilman]

[please don't top post, moved your reply below original...]

"stanley.miao" <stanley.miao@windriver.com> writes:

> Kevin Hilman wrote:
>> From: Brian Niebuhr <bniebuhr3@gmail.com>
>>
>> This patch fixes an issue where a DMA channel can erroneously process an
>> event generated by a previous transfer.  A failure case is where DMA is
>> being used for SPI transmit and receive channels on OMAP L138.  In this
>> case there is a single bit that controls all event generation from the
>> SPI peripheral.  Therefore it is possible that between when edma_stop()
>> has been called for the transmit channel on a previous transfer and
>> edma_start() is called for the transmit channel on a subsequent transfer,
>> that a transmit event has been generated.
>>
>> The fix is to clear events in edma_start().  This prevents false events
>> from being processed when events are enabled for that channel.
>>
>
> This patch causes that the sound can not work normally on OMAP_L138.
>

Can you describe "can not work normally"?  Does that mean simply does
not work, or works with pops & clicks etc.?

Just to clarify... how did you isolate it to this patch.

If you revert just this patch on current davinci git, do you have
working sound as you expect again?

Kevin

[PATCH 3/6] davinci: edma: clear events in edma_start()

[stanley.miao]

Kevin Hilman wrote:
> <snip>
>>>
>>>       
>> This patch causes that the sound can not work normally on OMAP_L138.
>>
>>     
>
> Can you describe "can not work normally"?  Does that mean simply does
> not work, or works with pops & clicks etc.?
>
> Just to clarify... how did you isolate it to this patch.
>
> If you revert just this patch on current davinci git, do you have
> working sound as you expect again?
>   
Below is the test result:

$/root> aplay audiodump.wav
Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100 
Hz, Stereo
aplay: pcm_write:1269: write error: Input/output error
$/root>

After revert it, the audio works fine.

Hi, Brian,

For the SPI issue, try this patch:
----------------------------------------
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -359,8 +359,10 @@ static void davinci_spi_dma_rx_callback(unsigned 
lch, u16 ch_status, void *data)
 
        if (ch_status == DMA_COMPLETE)
                edma_stop(davinci_spi_dma->dma_rx_channel);
-       else
+       else {
+               edma_stop(davinci_spi_dma->dma_rx_channel);
                edma_clean_channel(davinci_spi_dma->dma_rx_channel);
+       }
 
        complete(&davinci_spi_dma->dma_rx_completion);
        /* We must disable the DMA RX request */
@@ -380,8 +382,10 @@ static void davinci_spi_dma_tx_callback(unsigned 
lch, u16 ch_status, void *data)
 
        if (ch_status == DMA_COMPLETE)
                edma_stop(davinci_spi_dma->dma_tx_channel);
-       else
+       else {
+               edma_stop(davinci_spi_dma->dma_tx_channel);
                edma_clean_channel(davinci_spi_dma->dma_tx_channel);
+       }
 
        complete(&davinci_spi_dma->dma_tx_completion);
-------------------------------------------------

Stanley.

> Kevin
>
>   

[PATCH 3/6] davinci: edma: clear events in edma_start()

[Sudhakar Rajashekhara]

Hi Stanley,

On Tue, May 25, 2010 at 15:35:52, stanley.miao wrote:
> Kevin Hilman wrote:
> > <snip>
> >>>
> >>>       
> >> This patch causes that the sound can not work normally on OMAP_L138.
> >>
> >>     
> >
> > Can you describe "can not work normally"?  Does that mean simply does
> > not work, or works with pops & clicks etc.?
> >
> > Just to clarify... how did you isolate it to this patch.
> >
> > If you revert just this patch on current davinci git, do you have
> > working sound as you expect again?
> >   
> Below is the test result:
> 
> $/root> aplay audiodump.wav
> Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100 
> Hz, Stereo
> aplay: pcm_write:1269: write error: Input/output error
> $/root>
> 
> After revert it, the audio works fine.
> 

This patch works fine on DM644x which has McBSP but breaks audio on OMAP L138
(as you had mentioned) which has McASP. Ideally McBSP/McASP should start after
EDMA is started. If not then this patch clears the EDMA event which is actually
set by McBSP/McASP. As this patch is working fine on DM644x, I think there is
some issue in the audio driver which needs to be debugged.

Regards,
Sudhakar

[PATCH 3/6] davinci: edma: clear events in edma_start()

[Kevin Hilman]

"stanley.miao" <stanley.miao@windriver.com> writes:

> Kevin Hilman wrote:
>> <snip>
>>>>
>>>>       
>>> This patch causes that the sound can not work normally on OMAP_L138.
>>>
>>>     
>>
>> Can you describe "can not work normally"?  Does that mean simply does
>> not work, or works with pops & clicks etc.?
>>
>> Just to clarify... how did you isolate it to this patch.
>>
>> If you revert just this patch on current davinci git, do you have
>> working sound as you expect again?
>>   
> Below is the test result:
>
> $/root> aplay audiodump.wav
> Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100
> Hz, Stereo
> aplay: pcm_write:1269: write error: Input/output error
> $/root>
>
> After revert it, the audio works fine.

Thanks for clarifying.

Kevin

[PATCH 3/6] davinci: edma: clear events in edma_start()

[Kevin Hilman]

"Sudhakar Rajashekhara" <sudhakar.raj@ti.com> writes:

> Hi Stanley,
>
> On Tue, May 25, 2010 at 15:35:52, stanley.miao wrote:
>> Kevin Hilman wrote:
>> > <snip>
>> >>>
>> >>>       
>> >> This patch causes that the sound can not work normally on OMAP_L138.
>> >>
>> >>     
>> >
>> > Can you describe "can not work normally"?  Does that mean simply does
>> > not work, or works with pops & clicks etc.?
>> >
>> > Just to clarify... how did you isolate it to this patch.
>> >
>> > If you revert just this patch on current davinci git, do you have
>> > working sound as you expect again?
>> >   
>> Below is the test result:
>> 
>> $/root> aplay audiodump.wav
>> Playing WAVE 'audiodump.wav' : Signed 16 bit Little Endian, Rate 44100 
>> Hz, Stereo
>> aplay: pcm_write:1269: write error: Input/output error
>> $/root>
>> 
>> After revert it, the audio works fine.
>> 
>
> This patch works fine on DM644x which has McBSP but breaks audio on OMAP L138
> (as you had mentioned) which has McASP. Ideally McBSP/McASP should start after
> EDMA is started. If not then this patch clears the EDMA event which is actually
> set by McBSP/McASP. As this patch is working fine on DM644x, I think there is
> some issue in the audio driver which needs to be debugged.

In the mean time, I think it makes sense to revert $SUBJECT patch in
davinci git until the audio driver is debugged.

Kevin