[RFC] i.MX51 patches

[RFC] i.MX51 patches

[Sascha Hauer]

Hi all,

Here are some patches for review.

Sascha

The following changes since commit a3d3203e4bb40f253b1541e310dc0f9305be7c84:
  Linus Torvalds (1):
        Merge branch 'release' of git://git.kernel.org/.../lenb/linux-acpi-2.6

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git mx51

Sascha Hauer (5):
      i.MX51 Babbage: Add uncompress output
      i.MX51: Use correct clock for gpt
      i.MX51: map TZIC dynamically
      i.MX51: determine silicon revision dynamically
      i.MX51: remove NFC AXI static mapping

 arch/arm/mach-mx5/clock-mx51.c              |    2 +-
 arch/arm/mach-mx5/cpu.c                     |   53 +++++++++++++++++++++++++++
 arch/arm/mach-mx5/mm.c                      |   32 +++++++----------
 arch/arm/plat-mxc/include/mach/mx51.h       |   33 ++++++-----------
 arch/arm/plat-mxc/include/mach/uncompress.h |    4 ++
 5 files changed, 83 insertions(+), 41 deletions(-)

[PATCH 1/5] i.MX51 Babbage: Add uncompress output

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/uncompress.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 52e476a..b6d3d0f 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -66,6 +66,7 @@ static inline void flush(void)
 #define MX2X_UART1_BASE_ADDR	0x1000a000
 #define MX3X_UART1_BASE_ADDR	0x43F90000
 #define MX3X_UART2_BASE_ADDR	0x43F94000
+#define MX51_UART1_BASE_ADDR	0x73fbc000
 
 static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
@@ -101,6 +102,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 	case MACH_TYPE_MAGX_ZN5:
 		uart_base = MX3X_UART2_BASE_ADDR;
 		break;
+	case MACH_TYPE_MX51_BABBAGE:
+		uart_base = MX51_UART1_BASE_ADDR;
+		break;
 	default:
 		break;
 	}
-- 
1.7.0

[PATCH 2/5] i.MX51: Use correct clock for gpt

[Sascha Hauer]

The gpt uses the ipg clock, not ipg_perclk

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mx5/clock-mx51.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index be90c03..8f85f73 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -757,7 +757,7 @@ DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
 
 /* GPT */
 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
-	NULL,  NULL, &ipg_perclk, NULL);
+	NULL,  NULL, &ipg_clk, NULL);
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
 	NULL,  NULL, &ipg_clk, NULL);
 
-- 
1.7.0

[PATCH 3/5] i.MX51: map TZIC dynamically

[Sascha Hauer]

This looks cleaner and allows us to call mx51_revision
later when we can use ioremap to determine the silicon
revision dynamically.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mx5/mm.c                |   27 +++++++++++++--------------
 arch/arm/plat-mxc/include/mach/mx51.h |   11 +++--------
 2 files changed, 16 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index c21e18b..9fe7beb 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -35,11 +35,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
 		.length = MX51_DEBUG_SIZE,
 		.type = MT_DEVICE
 	}, {
-		.virtual = MX51_TZIC_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR),
-		.length = MX51_TZIC_SIZE,
-		.type = MT_DEVICE
-	}, {
 		.virtual = MX51_AIPS1_BASE_ADDR_VIRT,
 		.pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR),
 		.length = MX51_AIPS1_SIZE,
@@ -69,14 +64,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
  */
 void __init mx51_map_io(void)
 {
-	u32 tzic_addr;
-
-	if (mx51_revision() < MX51_CHIP_REV_2_0)
-		tzic_addr = 0x8FFFC000;
-	else
-		tzic_addr = 0xE0003000;
-	mxc_io_desc[2].pfn =  __phys_to_pfn(tzic_addr);
-
 	mxc_set_cpu_type(MXC_CPU_MX51);
 	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
 	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR));
@@ -85,5 +72,17 @@ void __init mx51_map_io(void)
 
 void __init mx51_init_irq(void)
 {
-	tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
+	unsigned long tzic_addr;
+	void __iomem *tzic_virt;
+
+	if (mx51_revision() < MX51_CHIP_REV_2_0)
+		tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
+	else
+		tzic_addr = MX51_TZIC_BASE_ADDR;
+
+	tzic_virt = ioremap(tzic_addr, SZ_16K);
+	if (!tzic_virt)
+		panic("unable to map TZIC interrupt controller\n");
+
+	tzic_init_irq(tzic_virt);
 }
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 771532b..f1396bd 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -14,7 +14,7 @@
  * FB100000	70000000	1M	SPBA 0
  * FB000000	73F00000	1M	AIPS 1
  * FB200000	83F00000	1M	AIPS 2
- * FA100000	8FFFC000	16K	TZIC (interrupt controller)
+ *		8FFFC000	16K	TZIC (interrupt controller)
  *         	90000000	256M	CSD0 SDRAM/DDR
  *         	A0000000	256M	CSD1 SDRAM/DDR
  *         	B0000000	128M	CS0 Flash
@@ -49,9 +49,8 @@
 #define MX51_GPU_BASE_ADDR		0x20000000
 #define MX51_GPU2D_BASE_ADDR		0xD0000000
 
-#define MX51_TZIC_BASE_ADDR		0x8FFFC000
-#define MX51_TZIC_BASE_ADDR_VIRT	0xFA100000
-#define MX51_TZIC_SIZE			SZ_16K
+#define MX51_TZIC_BASE_ADDR_TO1		0x8FFFC000
+#define MX51_TZIC_BASE_ADDR		0xE0000000
 
 #define MX51_DEBUG_BASE_ADDR		0x60000000
 #define MX51_DEBUG_BASE_ADDR_VIRT	0xFA200000
@@ -232,7 +231,6 @@
 #define MX51_IO_ADDRESS(x)					\
 	(void __iomem *)					\
 	(MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) :	\
-	MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :	\
@@ -246,9 +244,6 @@
 #define MX51_IRAM_IO_ADDRESS(x)  \
 	(((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
 
-#define MX51_TZIC_IO_ADDRESS(x)  \
-	(((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT)
-
 #define MX51_DEBUG_IO_ADDRESS(x)  \
 	(((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
 
-- 
1.7.0

[PATCH 4/5] i.MX51: determine silicon revision dynamically

[Sascha Hauer]

Freescale redboot passes the silicon revision via
ATAG_REVISION. Remove this bootloader dependency by
doing the same as redboot does in the Kernel.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mx5/cpu.c               |   53 +++++++++++++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/mx51.h |   13 ++++----
 2 files changed, 60 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 41c769f..2d37785 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -14,9 +14,62 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/module.h>
 #include <mach/hardware.h>
 #include <asm/io.h>
 
+static int cpu_silicon_rev = -1;
+
+#define SI_REV 0x48
+
+static void query_silicon_parameter(void)
+{
+	void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
+	u32 rev;
+
+	if (!rom) {
+		cpu_silicon_rev = -EINVAL;
+		return;
+	}
+
+	rev = readl(rom + SI_REV);
+	switch (rev) {
+	case 0x1:
+		cpu_silicon_rev = MX51_CHIP_REV_1_0;
+		break;
+	case 0x2:
+		cpu_silicon_rev = MX51_CHIP_REV_1_1;
+		break;
+	case 0x10:
+		cpu_silicon_rev = MX51_CHIP_REV_2_0;
+		break;
+	case 0x20:
+		cpu_silicon_rev = MX51_CHIP_REV_3_0;
+		break;
+	default:
+		cpu_silicon_rev = 0;
+	}
+
+	iounmap(rom);
+}
+
+/*
+ * Returns:
+ *	the silicon revision of the cpu
+ *	-EINVAL - not a mx51
+ */
+int mx51_revision(void)
+{
+	if (!cpu_is_mx51())
+		return -EINVAL;
+
+	if (cpu_silicon_rev == -1)
+		query_silicon_parameter();
+
+	return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx51_revision);
+
 static int __init post_cpu_init(void)
 {
 	unsigned int reg;
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index f1396bd..fd255a9 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -28,6 +28,12 @@
  */
 
 /*
+ * IROM
+ */
+#define MX51_IROM_BASE_ADDR		0x0
+#define MX51_IROM_SIZE			SZ_64K
+
+/*
  * IRAM
  */
 #define MX51_IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
@@ -438,12 +444,7 @@
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 
-extern unsigned int system_rev;
-
-static inline unsigned int mx51_revision(void)
-{
-	return system_rev;
-}
+extern int mx51_revision(void);
 #endif
 
 #endif	/*  __ASM_ARCH_MXC_MX51_H__ */
-- 
1.7.0

[PATCH 5/5] i.MX51: remove NFC AXI static mapping

[Sascha Hauer]

This area contains the Nand Flash controller registers. There
is no need to map them statically as the Nand driver uses ioremap().

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mx5/mm.c                |    5 -----
 arch/arm/plat-mxc/include/mach/mx51.h |    9 ++-------
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 9fe7beb..b7677ef 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -49,11 +49,6 @@ static struct map_desc mxc_io_desc[] __initdata = {
 		.pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
 		.length = MX51_AIPS2_SIZE,
 		.type = MT_DEVICE
-	}, {
-		.virtual = MX51_NFC_AXI_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR),
-		.length = MX51_NFC_AXI_SIZE,
-		.type = MT_DEVICE
 	},
 };
 
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index fd255a9..5aad344 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -23,7 +23,7 @@
  *         	C8000000	64M	CS3 Flash
  *         	CC000000	32M	CS4 SRAM
  *         	CE000000	32M	CS5 SRAM
- * F9000000	CFFF0000	64K	NFC (NAND Flash AXI)
+ *		CFFF0000	64K	NFC (NAND Flash AXI)
  *
  */
 
@@ -46,7 +46,6 @@
  * NFC
  */
 #define MX51_NFC_AXI_BASE_ADDR		0xCFFF0000	/* NAND flash AXI */
-#define MX51_NFC_AXI_BASE_ADDR_VIRT	0xF9000000
 #define MX51_NFC_AXI_SIZE		SZ_64K
 
 /*
@@ -240,8 +239,7 @@
 	MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :	\
-	MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) :	\
-	MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \
+	MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
 	0xDEADBEEF)
 
 /*
@@ -262,9 +260,6 @@
 #define MX51_AIPS2_IO_ADDRESS(x)  \
 	(((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
 
-#define MX51_NFC_AXI_IO_ADDRESS(x) \
-	(((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT)
-
 #define MX51_IS_MEM_DEVICE_NONSHARED(x)		0
 
 /*
-- 
1.7.0