* [PATCH V2 Resend 00/12] Adding Support for SPEAr Platform under ARM architecture
@ 2010-03-25 8:40 Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 01/12] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Following set of patches are for adding ST Microelctronics SPEAr Platform under
ARM architecture in Linux.
Hierarchy in SPEAr is as follows:
SPEAr (Platform)
- SPEAr3XX (3XX SOC series, based on ARM9)
- SPEAr300 (SOC)
- SPEAr300_EVB (Evaluation Board)
- SPEAr310 (SOC)
- SPEAr310_EVB (Evaluation Board)
- SPEAr320 (SOC)
- SPEAr320_EVB (Evaluation Board)
- SPEAr6XX (6XX SOC series, based on ARM9)
- SPEAr600 (SOC)
- SPEAr600_EVB (Evaluation Board)
- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
- SPEAr1300 (SOC)
Current patch will add support for SPEAr3XX and SPEAr6XX family. SPEAr13XX is
under development phase.
Changes from V1:
1. Changes done according to review comments
2. Added support for GPIO PL061
3. Removed unnecessary inclusions from defconfigs
4. Removed GPT driver. GPT code merged with time.c
5. Added support for pad multiplexing for spear
Viresh Kumar (12):
ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file
ST SPEAr: Added basic header files for SPEAr3xx machine family
ST SPEAr: Added basic header files for SPEAr6xx machine family
ST SPEAr: Added basic header files for SPEAr platform
ST SPEAr: Added clock framework for SPEAr platform and machines
ST SPEAr: Added source files for SPEAr platform
ST SPEAr: Added source files for SPEAr3xx machine family
ST SPEAr: Added source files for SPEAr6xx machine family
ST SPEAr: Added support for SPEAr platform and machines in arch/arm/
ST SPEAr: Added default configuration files for SPEAr machines
ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr
ST SPEAr: Adding gpio pad multiplexing support
Documentation/arm/00-INDEX | 2 +
Documentation/arm/SPEAr/overview.txt | 60 ++
MAINTAINERS | 40 ++
arch/arm/Kconfig | 13 +
arch/arm/Makefile | 5 +
arch/arm/configs/spear300_defconfig | 773 ++++++++++++++++++++
arch/arm/configs/spear310_defconfig | 775 +++++++++++++++++++++
arch/arm/configs/spear320_defconfig | 775 +++++++++++++++++++++
arch/arm/configs/spear600_defconfig | 760 ++++++++++++++++++++
arch/arm/include/asm/hardware/sp810.h | 59 ++
arch/arm/mach-spear3xx/Kconfig | 33 +
arch/arm/mach-spear3xx/Kconfig300 | 17 +
arch/arm/mach-spear3xx/Kconfig310 | 17 +
arch/arm/mach-spear3xx/Kconfig320 | 17 +
arch/arm/mach-spear3xx/Makefile | 26 +
arch/arm/mach-spear3xx/Makefile.boot | 3 +
arch/arm/mach-spear3xx/clock.c | 389 +++++++++++
arch/arm/mach-spear3xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear3xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear3xx/include/mach/entry-macro.S | 46 ++
arch/arm/mach-spear3xx/include/mach/generic.h | 205 ++++++
arch/arm/mach-spear3xx/include/mach/gpio.h | 19 +
arch/arm/mach-spear3xx/include/mach/hardware.h | 20 +
arch/arm/mach-spear3xx/include/mach/io.h | 19 +
arch/arm/mach-spear3xx/include/mach/irqs.h | 65 ++
arch/arm/mach-spear3xx/include/mach/memory.h | 19 +
arch/arm/mach-spear3xx/include/mach/misc_regs.h | 163 +++++
arch/arm/mach-spear3xx/include/mach/spear.h | 144 ++++
arch/arm/mach-spear3xx/include/mach/spear300.h | 67 ++
arch/arm/mach-spear3xx/include/mach/spear310.h | 46 ++
arch/arm/mach-spear3xx/include/mach/spear320.h | 70 ++
arch/arm/mach-spear3xx/include/mach/system.h | 19 +
arch/arm/mach-spear3xx/include/mach/timex.h | 19 +
arch/arm/mach-spear3xx/include/mach/uncompress.h | 19 +
arch/arm/mach-spear3xx/include/mach/vmalloc.h | 19 +
arch/arm/mach-spear3xx/spear300.c | 403 +++++++++++
arch/arm/mach-spear3xx/spear300_evb.c | 77 ++
arch/arm/mach-spear3xx/spear310.c | 154 ++++
arch/arm/mach-spear3xx/spear310_evb.c | 84 +++
arch/arm/mach-spear3xx/spear320.c | 399 +++++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 81 +++
arch/arm/mach-spear3xx/spear3xx.c | 548 +++++++++++++++
arch/arm/mach-spear6xx/Kconfig | 20 +
arch/arm/mach-spear6xx/Kconfig600 | 17 +
arch/arm/mach-spear6xx/Makefile | 12 +
arch/arm/mach-spear6xx/Makefile.boot | 3 +
arch/arm/mach-spear6xx/clock.c | 483 +++++++++++++
arch/arm/mach-spear6xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear6xx/include/mach/debug-macro.S | 14 +
arch/arm/mach-spear6xx/include/mach/entry-macro.S | 55 ++
arch/arm/mach-spear6xx/include/mach/generic.h | 45 ++
arch/arm/mach-spear6xx/include/mach/gpio.h | 19 +
arch/arm/mach-spear6xx/include/mach/hardware.h | 21 +
arch/arm/mach-spear6xx/include/mach/io.h | 20 +
arch/arm/mach-spear6xx/include/mach/irqs.h | 96 +++
arch/arm/mach-spear6xx/include/mach/memory.h | 19 +
arch/arm/mach-spear6xx/include/mach/misc_regs.h | 173 +++++
arch/arm/mach-spear6xx/include/mach/spear.h | 173 +++++
arch/arm/mach-spear6xx/include/mach/spear600.h | 21 +
arch/arm/mach-spear6xx/include/mach/system.h | 19 +
arch/arm/mach-spear6xx/include/mach/timex.h | 19 +
arch/arm/mach-spear6xx/include/mach/uncompress.h | 19 +
arch/arm/mach-spear6xx/include/mach/vmalloc.h | 19 +
arch/arm/mach-spear6xx/spear600.c | 25 +
arch/arm/mach-spear6xx/spear600_evb.c | 51 ++
arch/arm/mach-spear6xx/spear6xx.c | 158 +++++
arch/arm/plat-spear/Kconfig | 31 +
arch/arm/plat-spear/Makefile | 6 +
arch/arm/plat-spear/clock.c | 435 ++++++++++++
arch/arm/plat-spear/include/plat/clkdev.h | 20 +
arch/arm/plat-spear/include/plat/clock.h | 126 ++++
arch/arm/plat-spear/include/plat/debug-macro.S | 38 +
arch/arm/plat-spear/include/plat/gpio.h | 24 +
arch/arm/plat-spear/include/plat/io.h | 22 +
arch/arm/plat-spear/include/plat/memory.h | 20 +
arch/arm/plat-spear/include/plat/padmux.h | 92 +++
arch/arm/plat-spear/include/plat/system.h | 41 ++
arch/arm/plat-spear/include/plat/timex.h | 19 +
arch/arm/plat-spear/include/plat/uncompress.h | 43 ++
arch/arm/plat-spear/include/plat/vmalloc.h | 19 +
arch/arm/plat-spear/padmux.c | 164 +++++
arch/arm/plat-spear/time.c | 292 ++++++++
82 files changed, 9414 insertions(+), 0 deletions(-)
create mode 100644 Documentation/arm/SPEAr/overview.txt
create mode 100644 arch/arm/configs/spear300_defconfig
create mode 100644 arch/arm/configs/spear310_defconfig
create mode 100644 arch/arm/configs/spear320_defconfig
create mode 100644 arch/arm/configs/spear600_defconfig
create mode 100644 arch/arm/include/asm/hardware/sp810.h
create mode 100644 arch/arm/mach-spear3xx/Kconfig
create mode 100644 arch/arm/mach-spear3xx/Kconfig300
create mode 100644 arch/arm/mach-spear3xx/Kconfig310
create mode 100644 arch/arm/mach-spear3xx/Kconfig320
create mode 100644 arch/arm/mach-spear3xx/Makefile
create mode 100644 arch/arm/mach-spear3xx/Makefile.boot
create mode 100755 arch/arm/mach-spear3xx/clock.c
create mode 100644 arch/arm/mach-spear3xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear3xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear3xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/memory.h
create mode 100755 arch/arm/mach-spear3xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear300.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear310.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear320.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-spear3xx/spear300.c
create mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
create mode 100644 arch/arm/mach-spear3xx/spear310.c
create mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
create mode 100644 arch/arm/mach-spear3xx/spear320.c
create mode 100644 arch/arm/mach-spear3xx/spear320_evb.c
create mode 100644 arch/arm/mach-spear3xx/spear3xx.c
create mode 100644 arch/arm/mach-spear6xx/Kconfig
create mode 100644 arch/arm/mach-spear6xx/Kconfig600
create mode 100644 arch/arm/mach-spear6xx/Makefile
create mode 100644 arch/arm/mach-spear6xx/Makefile.boot
create mode 100755 arch/arm/mach-spear6xx/clock.c
create mode 100644 arch/arm/mach-spear6xx/include/mach/clkdev.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear6xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear6xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/io.h
create mode 100755 arch/arm/mach-spear6xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/memory.h
create mode 100755 arch/arm/mach-spear6xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/spear600.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/vmalloc.h
create mode 100644 arch/arm/mach-spear6xx/spear600.c
create mode 100644 arch/arm/mach-spear6xx/spear600_evb.c
create mode 100644 arch/arm/mach-spear6xx/spear6xx.c
create mode 100644 arch/arm/plat-spear/Kconfig
create mode 100644 arch/arm/plat-spear/Makefile
create mode 100755 arch/arm/plat-spear/clock.c
create mode 100644 arch/arm/plat-spear/include/plat/clkdev.h
create mode 100755 arch/arm/plat-spear/include/plat/clock.h
create mode 100644 arch/arm/plat-spear/include/plat/debug-macro.S
create mode 100644 arch/arm/plat-spear/include/plat/gpio.h
create mode 100644 arch/arm/plat-spear/include/plat/io.h
create mode 100644 arch/arm/plat-spear/include/plat/memory.h
create mode 100644 arch/arm/plat-spear/include/plat/padmux.h
create mode 100644 arch/arm/plat-spear/include/plat/system.h
create mode 100644 arch/arm/plat-spear/include/plat/timex.h
create mode 100644 arch/arm/plat-spear/include/plat/uncompress.h
create mode 100644 arch/arm/plat-spear/include/plat/vmalloc.h
create mode 100644 arch/arm/plat-spear/padmux.c
create mode 100644 arch/arm/plat-spear/time.c
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 01/12] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file
2010-03-25 8:40 [PATCH V2 Resend 00/12] Adding Support for SPEAr Platform under ARM architecture Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 02/12] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/include/asm/hardware/sp810.h | 59 +++++++++++++++++++++++++++++++++
1 files changed, 59 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/hardware/sp810.h
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
new file mode 100644
index 0000000..a101f10
--- /dev/null
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -0,0 +1,59 @@
+/*
+ * arch/arm/include/asm/hardware/sp810.h
+ *
+ * ARM PrimeXsys System Controller SP810 header file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARM_SP810_H
+#define __ASM_ARM_SP810_H
+
+#include <linux/io.h>
+
+/* sysctl registers offset */
+#define SCCTRL 0x000
+#define SCSYSSTAT 0x004
+#define SCIMCTRL 0x008
+#define SCIMSTAT 0x00C
+#define SCXTALCTRL 0x010
+#define SCPLLCTRL 0x014
+#define SCPLLFCTRL 0x018
+#define SCPERCTRL0 0x01C
+#define SCPERCTRL1 0x020
+#define SCPEREN 0x024
+#define SCPERDIS 0x028
+#define SCPERCLKEN 0x02C
+#define SCPERSTAT 0x030
+#define SCSYSID0 0xEE0
+#define SCSYSID1 0xEE4
+#define SCSYSID2 0xEE8
+#define SCSYSID3 0xEEC
+#define SCITCR 0xF00
+#define SCITIR0 0xF04
+#define SCITIR1 0xF08
+#define SCITOR 0xF0C
+#define SCCNTCTRL 0xF10
+#define SCCNTDATA 0xF14
+#define SCCNTSTEP 0xF18
+#define SCPERIPHID0 0xFE0
+#define SCPERIPHID1 0xFE4
+#define SCPERIPHID2 0xFE8
+#define SCPERIPHID3 0xFEC
+#define SCPCELLID0 0xFF0
+#define SCPCELLID1 0xFF4
+#define SCPCELLID2 0xFF8
+#define SCPCELLID3 0xFFC
+
+static inline void sysctl_soft_reset(void __iomem *base)
+{
+ /* writing any value to SCSYSSTAT reg will reset system */
+ writel(0, base + SCSYSSTAT);
+}
+
+#endif /* __ASM_ARM_SP810_H */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 02/12] ST SPEAr: Added basic header files for SPEAr3xx machine family
2010-03-25 8:40 ` [PATCH V2 Resend 01/12] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 03/12] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/debug-macro.S | 14 ++
arch/arm/mach-spear3xx/include/mach/entry-macro.S | 46 ++++++
arch/arm/mach-spear3xx/include/mach/generic.h | 58 ++++++++
arch/arm/mach-spear3xx/include/mach/gpio.h | 19 +++
arch/arm/mach-spear3xx/include/mach/hardware.h | 20 +++
arch/arm/mach-spear3xx/include/mach/io.h | 19 +++
arch/arm/mach-spear3xx/include/mach/irqs.h | 65 ++++++++
arch/arm/mach-spear3xx/include/mach/memory.h | 19 +++
arch/arm/mach-spear3xx/include/mach/misc_regs.h | 163 +++++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/spear.h | 144 ++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/spear300.h | 67 +++++++++
arch/arm/mach-spear3xx/include/mach/spear310.h | 46 ++++++
arch/arm/mach-spear3xx/include/mach/spear320.h | 70 +++++++++
arch/arm/mach-spear3xx/include/mach/system.h | 19 +++
arch/arm/mach-spear3xx/include/mach/timex.h | 19 +++
arch/arm/mach-spear3xx/include/mach/uncompress.h | 19 +++
arch/arm/mach-spear3xx/include/mach/vmalloc.h | 19 +++
17 files changed, 826 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear3xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear3xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear3xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/io.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/memory.h
create mode 100755 arch/arm/mach-spear3xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear300.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear310.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/spear320.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear3xx/include/mach/vmalloc.h
diff --git a/arch/arm/mach-spear3xx/include/mach/debug-macro.S b/arch/arm/mach-spear3xx/include/mach/debug-macro.S
new file mode 100644
index 0000000..590519f
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
new file mode 100644
index 0000000..947625d
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <mach/spear.h>
+#include <asm/hardware/vic.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \base, =VA_SPEAR3XX_ML1_VIC_BASE
+ ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
+ teq \irqstat, #0
+ beq 1001f @ this will set/reset
+ @ zero register
+ /*
+ * Following code will find bit position of least significang
+ * bit set in irqstat, using following equation
+ * least significant bit set in n = (n & ~(n-1))
+ */
+ sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
+ mvn \tmp, \tmp @ tmp = ~tmp
+ and \irqstat, \irqstat, \tmp @ irqstat &= tmp
+ /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
+ clz \tmp, \irqstat @ tmp = leading zeros
+ rsb \irqnr, \tmp, #0x1F @ irqnr = 32 - tmp - 1
+
+1001: /* EQ will be set if no irqs pending */
+ .endm
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
new file mode 100644
index 0000000..aeea845
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -0,0 +1,58 @@
+/*
+ * arch/arm/mach-spear3xx/generic.h
+ *
+ * SPEAr3XX machine family generic header file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+
+/*
+ * Each GPT has 2 timer channels
+ * Following GPT channels will be used as clock source and clockevent
+ */
+#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
+#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
+#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
+
+/* Add spear3xx family device structure declarations here */
+extern struct amba_device gpio_device;
+extern struct amba_device uart_device;
+extern struct sys_timer spear_sys_timer;
+
+/* Add spear3xx family function declarations here */
+void __init spear3xx_map_io(void);
+void __init spear3xx_init_irq(void);
+void __init spear3xx_init(void);
+void __init spear300_init(void);
+void __init spear310_init(void);
+void __init spear320_init(void);
+void __init clk_init(void);
+
+/* Add spear300 machine device structure declarations here */
+#ifdef CONFIG_MACH_SPEAR300
+extern struct amba_device gpio1_device;
+#endif /* CONFIG_MACH_SPEAR300 */
+
+/* Add spear310 machine device structure declarations here */
+#ifdef CONFIG_MACH_SPEAR310
+#endif /* CONFIG_MACH_SPEAR310 */
+
+/* Add spear320 machine device structure declarations here */
+#ifdef CONFIG_MACH_SPEAR320
+#endif /* CONFIG_MACH_SPEAR320 */
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/gpio.h b/arch/arm/mach-spear3xx/include/mach/gpio.h
new file mode 100644
index 0000000..451b208
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/gpio.h
+ *
+ * GPIO macros for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
new file mode 100644
index 0000000..4a86e6a
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/hardware.h
+ *
+ * Hardware definitions for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+/* Vitual to physical translation of statically mapped space */
+#define IO_ADDRESS(x) (x | 0xF0000000)
+
+#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/io.h b/arch/arm/mach-spear3xx/include/mach/io.h
new file mode 100644
index 0000000..30cff8a
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/io.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/io.h
+ *
+ * IO definitions for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+#endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
new file mode 100644
index 0000000..fe980e0
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -0,0 +1,65 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* IRQ definitions */
+#define IRQ_HW_ACCEL_MOD_0 0
+#define IRQ_INTRCOMM_RAS_ARM 1
+#define IRQ_CPU_GPT1_1 2
+#define IRQ_CPU_GPT1_2 3
+#define IRQ_BASIC_GPT1_1 4
+#define IRQ_BASIC_GPT1_2 5
+#define IRQ_BASIC_GPT2_1 6
+#define IRQ_BASIC_GPT2_2 7
+#define IRQ_BASIC_DMA 8
+#define IRQ_BASIC_SMI 9
+#define IRQ_BASIC_RTC 10
+#define IRQ_BASIC_GPIO 11
+#define IRQ_BASIC_WDT 12
+#define IRQ_DDR_CONTROLLER 13
+#define IRQ_SYS_ERROR 14
+#define IRQ_WAKEUP_RCV 15
+#define IRQ_JPEG 16
+#define IRQ_IRDA 17
+#define IRQ_ADC 18
+#define IRQ_UART 19
+#define IRQ_SSP 20
+#define IRQ_I2C 21
+#define IRQ_MAC_1 22
+#define IRQ_MAC_2 23
+#define IRQ_USB_DEV 24
+#define IRQ_USB_H_OHCI_0 25
+#define IRQ_USB_H_EHCI_0 26
+#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0
+#define IRQ_USB_H_OHCI_1 27
+#define IRQ_GEN_RAS_1 28
+#define IRQ_GEN_RAS_2 29
+#define IRQ_GEN_RAS_3 30
+#define IRQ_HW_ACCEL_MOD_1 31
+#define IRQ_VIC_END 32
+
+#define SPEAR_GPIO_INT_BASE IRQ_VIC_END
+
+#ifdef CONFIG_MACH_SPEAR300
+#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
+#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
+#else
+#define SPEAR_GPIO_INT_END (SPEAR_GPIO_INT_BASE + 8)
+#endif
+
+#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
+#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/memory.h b/arch/arm/mach-spear3xx/include/mach/memory.h
new file mode 100644
index 0000000..5173522
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/memory.h
+ *
+ * Memory map for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#include <plat/memory.h>
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
new file mode 100755
index 0000000..38d767a
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -0,0 +1,163 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/misc_regs.h
+ *
+ * Miscellaneous registers definitions for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MISC_REGS_H
+#define __MACH_MISC_REGS_H
+
+#include <mach/spear.h>
+
+#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE
+
+#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000))
+#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004))
+#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008))
+#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C))
+#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010))
+#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014))
+/* PLL_CTR register masks */
+#define PLL_ENABLE 2
+#define PLL_MODE_SHIFT 4
+#define PLL_MODE_MASK 0x3
+#define PLL_MODE_NORMAL 0
+#define PLL_MODE_FRACTION 1
+#define PLL_MODE_DITH_DSB 2
+#define PLL_MODE_DITH_SSB 3
+
+#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018))
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT 0
+#define PLL_DIV_N_MASK 0xFF
+#define PLL_DIV_P_SHIFT 8
+#define PLL_DIV_P_MASK 0x7
+#define PLL_NORM_FDBK_M_SHIFT 24
+#define PLL_NORM_FDBK_M_MASK 0xFF
+#define PLL_DITH_FDBK_M_SHIFT 16
+#define PLL_DITH_FDBK_M_MASK 0xFFFF
+
+#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C))
+#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020))
+#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024))
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT 10
+#define PLL_HCLK_RATIO_MASK 0x3
+#define HCLK_PCLK_RATIO_SHIFT 8
+#define HCLK_PCLK_RATIO_MASK 0x3
+
+#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028))
+/* PERIP_CLK_CFG register masks */
+#define UART_CLK_SHIFT 4
+#define UART_CLK_MASK 0x1
+#define FIRDA_CLK_SHIFT 5
+#define FIRDA_CLK_MASK 0x3
+#define GPT0_CLK_SHIFT 8
+#define GPT1_CLK_SHIFT 11
+#define GPT2_CLK_SHIFT 12
+#define GPT_CLK_MASK 0x1
+#define AUX_CLK_PLL3_MASK 0
+#define AUX_CLK_PLL1_MASK 1
+
+#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C))
+/* PERIP1_CLK_ENB register masks */
+#define UART_CLK_ENB 3
+#define SSP_CLK_ENB 5
+#define I2C_CLK_ENB 7
+#define JPEG_CLK_ENB 8
+#define FIRDA_CLK_ENB 10
+#define GPT1_CLK_ENB 11
+#define GPT2_CLK_ENB 12
+#define ADC_CLK_ENB 15
+#define RTC_CLK_ENB 17
+#define GPIO_CLK_ENB 18
+#define DMA_CLK_ENB 19
+#define SMI_CLK_ENB 21
+#define GMAC_CLK_ENB 23
+#define USBD_CLK_ENB 24
+#define USBH_CLK_ENB 25
+#define C3_CLK_ENB 31
+
+#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030))
+#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034))
+#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038))
+/* PERIP1_SOF_RST register masks */
+#define JPEG_SOF_RST 8
+
+#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C))
+#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040))
+#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044))
+#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048))
+#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C))
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT 0
+#define GPT_MSCALE_MASK 0xFFF
+#define GPT_NSCALE_SHIFT 12
+#define GPT_NSCALE_MASK 0xF
+
+#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050))
+#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054))
+#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C))
+#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060))
+#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064))
+#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068))
+#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C))
+#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070))
+#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074))
+#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078))
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_EQ_SEL_SHIFT 30
+#define AUX_EQ_SEL_MASK 1
+#define AUX_EQ1_SEL 0
+#define AUX_EQ2_SEL 1
+#define AUX_XSCALE_SHIFT 16
+#define AUX_XSCALE_MASK 0xFFF
+#define AUX_YSCALE_SHIFT 0
+#define AUX_YSCALE_MASK 0xFFF
+
+#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C))
+#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080))
+#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084))
+#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088))
+#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C))
+#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090))
+#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094))
+#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098))
+#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C))
+#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0))
+#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4))
+#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8))
+#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC))
+#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0))
+#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4))
+#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8))
+#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC))
+#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0))
+#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4))
+#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8))
+#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC))
+#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0))
+#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4))
+#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8))
+#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC))
+#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0))
+#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4))
+#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8))
+#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC))
+#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100))
+#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104))
+#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108))
+#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C))
+#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110))
+#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114))
+#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118))
+#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C))
+
+#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
new file mode 100644
index 0000000..dcca856
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -0,0 +1,144 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/spear.h
+ *
+ * SPEAr3xx Machine family specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR3XX_H
+#define __MACH_SPEAR3XX_H
+
+#include <mach/hardware.h>
+#include <mach/spear300.h>
+#include <mach/spear310.h>
+#include <mach/spear320.h>
+
+#define SPEAR3XX_ML_SDRAM_BASE 0x00000000
+#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000
+
+#define SPEAR3XX_ICM9_BASE 0xC0000000
+#define SPEAR3XX_ICM9_SIZE 0x10000000
+
+/* ICM1 - Low speed connection */
+#define SPEAR3XX_ICM1_2_BASE 0xD0000000
+#define SPEAR3XX_ICM1_2_SIZE 0x10000000
+
+#define SPEAR3XX_ICM1_UART_BASE 0xD0000000
+#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
+#define SPEAR3XX_ICM1_UART_SIZE 0x00080000
+
+#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000
+#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000
+
+#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000
+#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000
+
+#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000
+#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000
+
+#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000
+#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000
+
+#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000
+#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000
+
+#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000
+#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000
+
+/* ICM2 - Application Subsystem */
+#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000
+#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000
+
+#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000
+#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000
+
+/* ICM4 - High Speed Connection */
+#define SPEAR3XX_ICM4_BASE 0xE0000000
+#define SPEAR3XX_ICM4_SIZE 0x08000000
+
+#define SPEAR3XX_ICM4_MII_BASE 0xE0800000
+#define SPEAR3XX_ICM4_MII_SIZE 0x00800000
+
+#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000
+#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000
+
+#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000
+#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000
+
+#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000
+#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000
+
+#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000
+#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000
+
+#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000
+#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000
+
+#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000
+#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000
+
+#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000
+#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000
+
+/* ML1 - Multi Layer CPU Subsystem */
+#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000
+#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000
+
+#define SPEAR3XX_ML1_TMR_BASE 0xF0000000
+#define SPEAR3XX_ML1_TMR_SIZE 0x00100000
+
+#define SPEAR3XX_ML1_VIC_BASE 0xF1100000
+#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
+#define SPEAR3XX_ML1_VIC_SIZE 0x00100000
+
+/* ICM3 - Basic Subsystem */
+#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000
+#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000
+
+#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000
+#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000
+
+#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000
+#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000
+
+#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
+#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
+
+#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000
+#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000
+
+#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000
+#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000
+
+#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000
+#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000
+
+#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000
+#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000
+
+#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000
+#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
+#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000
+
+#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000
+#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
+#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000
+
+#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000
+#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
+#define VA_SPEAR_DBG_UART_BASE VA_SPEAR3XX_ICM1_UART_BASE
+
+/* Sysctl base for spear platform */
+#define SPEAR_SYS_CTRL_BASE SPEAR3XX_ICM3_SYS_CTRL_BASE
+#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR3XX_ICM3_SYS_CTRL_BASE
+
+#endif /* __MACH_SPEAR3XX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
new file mode 100644
index 0000000..40c16f3
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -0,0 +1,67 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/spear300.h
+ *
+ * SPEAr300 Machine specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR300
+
+#ifndef __MACH_SPEAR300_H
+#define __MACH_SPEAR300_H
+
+/* Base address of various IPs */
+#define SPEAR300_TELECOM_BASE 0x50000000
+#define SPEAR300_TELECOM_SIZE 0x10000000
+
+#define SPEAR300_CLCD_BASE 0x60000000
+#define SPEAR300_CLCD_SIZE 0x10000000
+
+#define SPEAR300_SDIO_BASE 0x70000000
+#define SPEAR300_SDIO_SIZE 0x10000000
+
+#define SPEAR300_NAND_0_BASE 0x80000000
+#define SPEAR300_NAND_0_SIZE 0x04000000
+
+#define SPEAR300_NAND_1_BASE 0x84000000
+#define SPEAR300_NAND_1_SIZE 0x04000000
+
+#define SPEAR300_NAND_2_BASE 0x88000000
+#define SPEAR300_NAND_2_SIZE 0x04000000
+
+#define SPEAR300_NAND_3_BASE 0x8c000000
+#define SPEAR300_NAND_3_SIZE 0x04000000
+
+#define SPEAR300_NOR_0_BASE 0x90000000
+#define SPEAR300_NOR_0_SIZE 0x01000000
+
+#define SPEAR300_NOR_1_BASE 0x91000000
+#define SPEAR300_NOR_1_SIZE 0x01000000
+
+#define SPEAR300_NOR_2_BASE 0x92000000
+#define SPEAR300_NOR_2_SIZE 0x01000000
+
+#define SPEAR300_NOR_3_BASE 0x93000000
+#define SPEAR300_NOR_3_SIZE 0x01000000
+
+#define SPEAR300_FSMC_BASE 0x94000000
+#define SPEAR300_FSMC_SIZE 0x05000000
+
+#define SPEAR300_SOC_CONFIG_BASE 0x99000000
+#define SPEAR300_SOC_CONFIG_SIZE 0x00000008
+
+#define SPEAR300_KEYBOARD_BASE 0xA0000000
+#define SPEAR300_KEYBOARD_SIZE 0x09000000
+
+#define SPEAR300_GPIO_BASE 0xA9000000
+#define SPEAR300_GPIO_SIZE 0x07000000
+
+#endif /* __MACH_SPEAR300_H */
+
+#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
new file mode 100644
index 0000000..d4f58d6
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/spear310.h
+ *
+ * SPEAr310 Machine specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR310
+
+#ifndef __MACH_SPEAR310_H
+#define __MACH_SPEAR310_H
+
+#define SPEAR310_NAND_BASE 0x40000000
+#define SPEAR310_NAND_SIZE 0x04000000
+
+#define SPEAR310_FSMC_BASE 0x44000000
+#define SPEAR310_FSMC_SIZE 0x01000000
+
+#define SPEAR310_UART1_BASE 0xB2000000
+#define SPEAR310_UART2_BASE 0xB2080000
+#define SPEAR310_UART3_BASE 0xB2100000
+#define SPEAR310_UART4_BASE 0xB2180000
+#define SPEAR310_UART5_BASE 0xB2200000
+#define SPEAR310_UART_SIZE 0x00080000
+
+#define SPEAR310_HDLC_BASE 0xB2800000
+#define SPEAR310_HDLC_SIZE 0x00800000
+
+#define SPEAR310_RS485_0_BASE 0xB3000000
+#define SPEAR310_RS485_0_SIZE 0x00800000
+
+#define SPEAR310_RS485_1_BASE 0xB3800000
+#define SPEAR310_RS485_1_SIZE 0x00800000
+
+#define SPEAR310_SOC_CONFIG_BASE 0xB4000000
+#define SPEAR310_SOC_CONFIG_SIZE 0x00000070
+
+#endif /* __MACH_SPEAR310_H */
+
+#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
new file mode 100644
index 0000000..e8ad2ed
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -0,0 +1,70 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/spear320.h
+ *
+ * SPEAr320 Machine specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR320
+
+#ifndef __MACH_SPEAR320_H
+#define __MACH_SPEAR320_H
+
+#define SPEAR320_EMI_CTRL_BASE 0x40000000
+#define SPEAR320_EMI_CTRL_SIZE 0x08000000
+
+#define SPEAR320_FSMC_BASE 0x4C000000
+#define SPEAR320_FSMC_SIZE 0x01000000
+
+#define SPEAR320_I2S_BASE 0x60000000
+#define SPEAR320_I2S_SIZE 0x10000000
+
+#define SPEAR320_SDIO_BASE 0x70000000
+#define SPEAR320_SDIO_SIZE 0x10000000
+
+#define SPEAR320_CLCD_BASE 0x90000000
+#define SPEAR320_CLCD_SIZE 0x10000000
+
+#define SPEAR320_PAR_PORT_BASE 0xA0000000
+#define SPEAR320_PAR_PORT_SIZE 0x01000000
+
+#define SPEAR320_CAN0_BASE 0xA1000000
+#define SPEAR320_CAN0_SIZE 0x01000000
+
+#define SPEAR320_CAN1_BASE 0xA2000000
+#define SPEAR320_CAN1_SIZE 0x01000000
+
+#define SPEAR320_UART1_BASE 0xA3000000
+#define SPEAR320_UART2_BASE 0xA4000000
+#define SPEAR320_UART_SIZE 0x01000000
+
+#define SPEAR320_SSP0_BASE 0xA5000000
+#define SPEAR320_SSP0_SIZE 0x01000000
+
+#define SPEAR320_SSP1_BASE 0xA6000000
+#define SPEAR320_SSP1_SIZE 0x01000000
+
+#define SPEAR320_I2C_BASE 0xA7000000
+#define SPEAR320_I2C_SIZE 0x01000000
+
+#define SPEAR320_PWM_BASE 0xA8000000
+#define SPEAR320_PWM_SIZE 0x01000000
+
+#define SPEAR320_SMII0_BASE 0xAA000000
+#define SPEAR320_SMII0_SIZE 0x01000000
+
+#define SPEAR320_SMII1_BASE 0xAB000000
+#define SPEAR320_SMII1_SIZE 0x01000000
+
+#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
+#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
+
+#endif /* __MACH_SPEAR320_H */
+
+#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/include/mach/system.h b/arch/arm/mach-spear3xx/include/mach/system.h
new file mode 100644
index 0000000..92cee63
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/system.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/system.h
+ *
+ * SPEAr3xx Machine family specific architecture functions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <plat/system.h>
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/timex.h b/arch/arm/mach-spear3xx/include/mach/timex.h
new file mode 100644
index 0000000..a38cc9d
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/timex.h
+ *
+ * SPEAr3XX machine family specific timex definitions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#include <plat/timex.h>
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/uncompress.h b/arch/arm/mach-spear3xx/include/mach/uncompress.h
new file mode 100644
index 0000000..53ba8bb
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/vmalloc.h b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
new file mode 100644
index 0000000..df977b3
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/vmalloc.h
+ *
+ * Defining Vmalloc area for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#include <plat/vmalloc.h>
+
+#endif /* __MACH_VMALLOC_H */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 03/12] ST SPEAr: Added basic header files for SPEAr6xx machine family
2010-03-25 8:40 ` [PATCH V2 Resend 02/12] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 04/12] ST SPEAr: Added basic header files for SPEAr platform Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
---
arch/arm/mach-spear6xx/include/mach/debug-macro.S | 14 ++
arch/arm/mach-spear6xx/include/mach/entry-macro.S | 55 +++++++
arch/arm/mach-spear6xx/include/mach/generic.h | 45 ++++++
arch/arm/mach-spear6xx/include/mach/gpio.h | 19 +++
arch/arm/mach-spear6xx/include/mach/hardware.h | 21 +++
arch/arm/mach-spear6xx/include/mach/io.h | 20 +++
arch/arm/mach-spear6xx/include/mach/irqs.h | 96 ++++++++++++
arch/arm/mach-spear6xx/include/mach/memory.h | 19 +++
arch/arm/mach-spear6xx/include/mach/misc_regs.h | 173 +++++++++++++++++++++
arch/arm/mach-spear6xx/include/mach/spear.h | 173 +++++++++++++++++++++
arch/arm/mach-spear6xx/include/mach/spear600.h | 21 +++
arch/arm/mach-spear6xx/include/mach/system.h | 19 +++
arch/arm/mach-spear6xx/include/mach/timex.h | 19 +++
arch/arm/mach-spear6xx/include/mach/uncompress.h | 19 +++
arch/arm/mach-spear6xx/include/mach/vmalloc.h | 19 +++
15 files changed, 732 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear6xx/include/mach/debug-macro.S
create mode 100644 arch/arm/mach-spear6xx/include/mach/entry-macro.S
create mode 100644 arch/arm/mach-spear6xx/include/mach/generic.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/gpio.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/hardware.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/io.h
create mode 100755 arch/arm/mach-spear6xx/include/mach/irqs.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/memory.h
create mode 100755 arch/arm/mach-spear6xx/include/mach/misc_regs.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/spear.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/spear600.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/system.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/timex.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/uncompress.h
create mode 100644 arch/arm/mach-spear6xx/include/mach/vmalloc.h
diff --git a/arch/arm/mach-spear6xx/include/mach/debug-macro.S b/arch/arm/mach-spear6xx/include/mach/debug-macro.S
new file mode 100644
index 0000000..0f3ea39
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/debug-macro.S
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-spear6xx/include/mach/entry-macro.S b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
new file mode 100644
index 0000000..9eaecae
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/entry-macro.S
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/hardware.h>
+#include <mach/spear.h>
+#include <asm/hardware/vic.h>
+
+ .macro disable_fiq
+ .endm
+
+ .macro get_irqnr_preamble, base, tmp
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE
+ ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
+ mov \irqnr, #0
+ teq \irqstat, #0
+ bne 1001f
+ ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE
+ ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status
+ teq \irqstat, #0
+ beq 1002f @ this will set/reset
+ @ zero register
+ mov \irqnr, #32
+1001:
+ /*
+ * Following code will find bit position of least significang
+ * bit set in irqstat, using following equation
+ * least significant bit set in n = (n & ~(n-1))
+ */
+ sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
+ mvn \tmp, \tmp @ tmp = ~tmp
+ and \irqstat, \irqstat, \tmp @ irqstat &= tmp
+ /* Now, irqstat is = bit no. of 1st bit set in vic irq status */
+ clz \tmp, \irqstat @ tmp = leading zeros
+
+ rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1
+ add \irqnr, \irqnr, \tmp
+
+1002: /* EQ will be set if no irqs pending */
+ .endm
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
new file mode 100644
index 0000000..16205a5
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/generic.h
+ *
+ * SPEAr6XX machine family specific generic header file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GENERIC_H
+#define __MACH_GENERIC_H
+
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+
+/*
+ * Each GPT has 2 timer channels
+ * Following GPT channels will be used as clock source and clockevent
+ */
+#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE
+#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
+#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
+
+/* Add spear6xx family device structure declarations here */
+extern struct amba_device gpio_device[];
+extern struct amba_device uart_device[];
+extern struct sys_timer spear_sys_timer;
+
+/* Add spear6xx family function declarations here */
+void __init spear6xx_map_io(void);
+void __init spear6xx_init_irq(void);
+void __init spear6xx_init(void);
+void __init spear600_init(void);
+void __init clk_init(void);
+
+/* Add spear600 machine device structure declarations here */
+
+#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/gpio.h b/arch/arm/mach-spear6xx/include/mach/gpio.h
new file mode 100644
index 0000000..3a789db
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/gpio.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/gpio.h
+ *
+ * GPIO macros for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
new file mode 100644
index 0000000..7545116
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/hardware.h
+ *
+ * Hardware definitions for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_HARDWARE_H
+#define __MACH_HARDWARE_H
+
+/* Vitual to physical translation of statically mapped space */
+#define IO_ADDRESS(x) (x | 0xF0000000)
+
+#endif /* __MACH_HARDWARE_H */
+
diff --git a/arch/arm/mach-spear6xx/include/mach/io.h b/arch/arm/mach-spear6xx/include/mach/io.h
new file mode 100644
index 0000000..fb7c106
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/io.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/io.h
+ *
+ * IO definitions for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IO_H
+#define __MACH_IO_H
+
+#include <plat/io.h>
+
+#endif /* __MACH_IO_H */
+
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
new file mode 100755
index 0000000..08a3abc
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -0,0 +1,96 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* IRQ definitions */
+/* VIC 1 */
+#define IRQ_INTRCOMM_SW_IRQ 0
+#define IRQ_INTRCOMM_CPU_1 1
+#define IRQ_INTRCOMM_CPU_2 2
+#define IRQ_INTRCOMM_RAS2A11_1 3
+#define IRQ_INTRCOMM_RAS2A11_2 4
+#define IRQ_INTRCOMM_RAS2A12_1 5
+#define IRQ_INTRCOMM_RAS2A12_2 6
+#define IRQ_GEN_RAS_0 7
+#define IRQ_GEN_RAS_1 8
+#define IRQ_GEN_RAS_2 9
+#define IRQ_GEN_RAS_3 10
+#define IRQ_GEN_RAS_4 11
+#define IRQ_GEN_RAS_5 12
+#define IRQ_GEN_RAS_6 13
+#define IRQ_GEN_RAS_7 14
+#define IRQ_GEN_RAS_8 15
+#define IRQ_CPU_GPT1_1 16
+#define IRQ_CPU_GPT1_2 17
+#define IRQ_LOCAL_GPIO 18
+#define IRQ_PLL_UNLOCK 19
+#define IRQ_JPEG 20
+#define IRQ_FSMC 21
+#define IRQ_IRDA 22
+#define IRQ_RESERVED 23
+#define IRQ_UART_0 24
+#define IRQ_UART_1 25
+#define IRQ_SSP_1 26
+#define IRQ_SSP_2 27
+#define IRQ_I2C 28
+#define IRQ_GEN_RAS_9 29
+#define IRQ_GEN_RAS_10 30
+#define IRQ_GEN_RAS_11 31
+
+/* VIC 2 */
+#define IRQ_APPL_GPT1_1 32
+#define IRQ_APPL_GPT1_2 33
+#define IRQ_APPL_GPT2_1 34
+#define IRQ_APPL_GPT2_2 35
+#define IRQ_APPL_GPIO 36
+#define IRQ_APPL_SSP 37
+#define IRQ_APPL_ADC 38
+#define IRQ_APPL_RESERVED 39
+#define IRQ_AHB_EXP_MASTER 40
+#define IRQ_DDR_CONTROLLER 41
+#define IRQ_BASIC_DMA 42
+#define IRQ_BASIC_RESERVED1 43
+#define IRQ_BASIC_SMI 44
+#define IRQ_BASIC_CLCD 45
+#define IRQ_EXP_AHB_1 46
+#define IRQ_EXP_AHB_2 47
+#define IRQ_BASIC_GPT1_1 48
+#define IRQ_BASIC_GPT1_2 49
+#define IRQ_BASIC_RTC 50
+#define IRQ_BASIC_GPIO 51
+#define IRQ_BASIC_WDT 52
+#define IRQ_BASIC_RESERVED 53
+#define IRQ_AHB_EXP_SLAVE 54
+#define IRQ_GMAC_1 55
+#define IRQ_GMAC_2 56
+#define IRQ_USB_DEV 57
+#define IRQ_USB_H_OHCI_0 58
+#define IRQ_USB_H_EHCI_0 59
+#define IRQ_USB_H_OHCI_1 60
+#define IRQ_USB_H_EHCI_1 61
+#define IRQ_EXP_AHB_3 62
+#define IRQ_EXP_AHB_4 63
+
+#define IRQ_VIC_END 64
+
+#define SPEAR_GPIO_INT_BASE IRQ_VIC_END
+#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE
+#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
+#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
+#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
+#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
+#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/memory.h b/arch/arm/mach-spear6xx/include/mach/memory.h
new file mode 100644
index 0000000..781f088
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/memory.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/memory.h
+ *
+ * Memory map for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MEMORY_H
+#define __MACH_MEMORY_H
+
+#include <plat/memory.h>
+
+#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
new file mode 100755
index 0000000..0390803
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/misc_regs.h
+ *
+ * Miscellaneous registers definitions for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_MISC_REGS_H
+#define __MACH_MISC_REGS_H
+
+#include <mach/spear.h>
+
+#define MISC_BASE VA_SPEAR6XX_ICM3_MISC_REG_BASE
+
+#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000))
+#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004))
+#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008))
+#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C))
+#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010))
+#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014))
+/* PLL_CTR register masks */
+#define PLL_ENABLE 2
+#define PLL_MODE_SHIFT 4
+#define PLL_MODE_MASK 0x3
+#define PLL_MODE_NORMAL 0
+#define PLL_MODE_FRACTION 1
+#define PLL_MODE_DITH_DSB 2
+#define PLL_MODE_DITH_SSB 3
+
+#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018))
+/* PLL FRQ register masks */
+#define PLL_DIV_N_SHIFT 0
+#define PLL_DIV_N_MASK 0xFF
+#define PLL_DIV_P_SHIFT 8
+#define PLL_DIV_P_MASK 0x7
+#define PLL_NORM_FDBK_M_SHIFT 24
+#define PLL_NORM_FDBK_M_MASK 0xFF
+#define PLL_DITH_FDBK_M_SHIFT 16
+#define PLL_DITH_FDBK_M_MASK 0xFFFF
+
+#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C))
+#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020))
+#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024))
+/* CORE CLK CFG register masks */
+#define PLL_HCLK_RATIO_SHIFT 10
+#define PLL_HCLK_RATIO_MASK 0x3
+#define HCLK_PCLK_RATIO_SHIFT 8
+#define HCLK_PCLK_RATIO_MASK 0x3
+
+#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028))
+/* PERIP_CLK_CFG register masks */
+#define CLCD_CLK_SHIFT 2
+#define CLCD_CLK_MASK 0x3
+#define UART_CLK_SHIFT 4
+#define UART_CLK_MASK 0x1
+#define FIRDA_CLK_SHIFT 5
+#define FIRDA_CLK_MASK 0x3
+#define GPT0_CLK_SHIFT 8
+#define GPT1_CLK_SHIFT 10
+#define GPT2_CLK_SHIFT 11
+#define GPT3_CLK_SHIFT 12
+#define GPT_CLK_MASK 0x1
+#define AUX_CLK_PLL3_MASK 0
+#define AUX_CLK_PLL1_MASK 1
+
+#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C))
+/* PERIP1_CLK_ENB register masks */
+#define UART0_CLK_ENB 3
+#define UART1_CLK_ENB 4
+#define SSP0_CLK_ENB 5
+#define SSP1_CLK_ENB 6
+#define I2C_CLK_ENB 7
+#define JPEG_CLK_ENB 8
+#define FSMC_CLK_ENB 9
+#define FIRDA_CLK_ENB 10
+#define GPT2_CLK_ENB 11
+#define GPT3_CLK_ENB 12
+#define GPIO2_CLK_ENB 13
+#define SSP2_CLK_ENB 14
+#define ADC_CLK_ENB 15
+#define GPT1_CLK_ENB 11
+#define RTC_CLK_ENB 17
+#define GPIO1_CLK_ENB 18
+#define DMA_CLK_ENB 19
+#define SMI_CLK_ENB 21
+#define CLCD_CLK_ENB 22
+#define GMAC_CLK_ENB 23
+#define USBD_CLK_ENB 24
+#define USBH0_CLK_ENB 25
+#define USBH1_CLK_ENB 26
+
+#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030))
+#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034))
+#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038))
+/* PERIP1_SOF_RST register masks */
+#define JPEG_SOF_RST 8
+
+#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C))
+#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040))
+#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044))
+#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048))
+#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C))
+/* gpt synthesizer register masks */
+#define GPT_MSCALE_SHIFT 0
+#define GPT_MSCALE_MASK 0xFFF
+#define GPT_NSCALE_SHIFT 12
+#define GPT_NSCALE_MASK 0xF
+
+#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050))
+#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054))
+#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C))
+#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060))
+#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064))
+#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068))
+#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C))
+#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070))
+#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074))
+#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078))
+/* aux clk synthesiser register masks for irda to ras4 */
+#define AUX_EQ_SEL_SHIFT 30
+#define AUX_EQ_SEL_MASK 1
+#define AUX_EQ1_SEL 0
+#define AUX_EQ2_SEL 1
+#define AUX_XSCALE_SHIFT 16
+#define AUX_XSCALE_MASK 0xFFF
+#define AUX_YSCALE_SHIFT 0
+#define AUX_YSCALE_MASK 0xFFF
+
+#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C))
+#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080))
+#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084))
+#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088))
+#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C))
+#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090))
+#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094))
+#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098))
+#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C))
+#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0))
+#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4))
+#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8))
+#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC))
+#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0))
+#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4))
+#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8))
+#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC))
+#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0))
+#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4))
+#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8))
+#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC))
+#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0))
+#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4))
+#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8))
+#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC))
+#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0))
+#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4))
+#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8))
+#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC))
+#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100))
+#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104))
+#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108))
+#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C))
+#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110))
+#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114))
+#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118))
+#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C))
+
+#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
new file mode 100644
index 0000000..a835f5b
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/spear.h
+ *
+ * SPEAr6xx Machine family specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SPEAR6XX_H
+#define __MACH_SPEAR6XX_H
+
+#include <mach/hardware.h>
+#include <mach/spear600.h>
+
+#define SPEAR6XX_ML_SDRAM_BASE 0x00000000
+#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000
+
+/* ICM1 - Low speed connection */
+#define SPEAR6XX_ICM1_BASE 0xD0000000
+#define SPEAR6XX_ICM1_SIZE 0x08000000
+
+#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000
+#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
+#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000
+
+#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000
+#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000
+
+#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000
+#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000
+
+#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000
+#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000
+
+#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000
+#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000
+
+#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000
+#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000
+
+#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000
+#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000
+
+#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000
+#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000
+
+#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000
+#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000
+
+#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000
+#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000
+
+/* ICM2 - Application Subsystem */
+#define SPEAR6XX_ICM2_BASE 0xD8000000
+#define SPEAR6XX_ICM2_SIZE 0x08000000
+
+#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000
+#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000
+
+#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000
+#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000
+
+#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000
+#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000
+
+#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000
+#define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000
+
+#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000
+#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000
+
+/* ML-1, 2 - Multi Layer CPU Subsystem */
+#define SPEAR6XX_ML_CPU_BASE 0xF0000000
+#define SPEAR6XX_ML_CPU_SIZE 0x08000000
+
+#define SPEAR6XX_CPU_TMR_BASE 0xF0000000
+#define SPEAR6XX_CPU_TMR_SIZE 0x00100000
+
+#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000
+#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000
+
+#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000
+#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
+#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000
+
+#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000
+#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
+#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000
+
+/* ICM3 - Basic Subsystem */
+#define SPEAR6XX_ICM3_BASE 0xF8000000
+#define SPEAR6XX_ICM3_SIZE 0x08000000
+
+#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000
+#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000
+
+#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000
+#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000
+
+#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000
+#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000
+
+#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000
+#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000
+
+#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000
+#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000
+
+#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000
+#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000
+
+#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000
+#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000
+
+#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000
+#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000
+
+#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000
+#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000
+
+#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000
+#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
+#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000
+
+#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000
+#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
+#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000
+
+/* ICM4 - High Speed Connection */
+#define SPEAR6XX_ICM4_BASE 0xE0000000
+#define SPEAR6XX_ICM4_SIZE 0x08000000
+
+#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000
+#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000
+
+#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000
+#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000
+
+#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000
+#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000
+
+#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000
+#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000
+
+#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000
+#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000
+
+#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000
+#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000
+
+#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000
+#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000
+
+#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000
+#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000
+
+#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000
+#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000
+
+/* Debug uart for linux, will be used for debug and uncompress messages */
+#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
+#define VA_SPEAR_DBG_UART_BASE VA_SPEAR6XX_ICM1_UART0_BASE
+
+/* Sysctl base for spear platform */
+#define SPEAR_SYS_CTRL_BASE SPEAR6XX_ICM3_SYS_CTRL_BASE
+#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR6XX_ICM3_SYS_CTRL_BASE
+
+#endif /* __MACH_SPEAR6XX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
new file mode 100644
index 0000000..c068cc5
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/spear600.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-spear66xx/include/mach/spear600.h
+ *
+ * SPEAr600 Machine specific definition
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifdef CONFIG_MACH_SPEAR600
+
+#ifndef __MACH_SPEAR600_H
+#define __MACH_SPEAR600_H
+
+#endif /* __MACH_SPEAR600_H */
+
+#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/include/mach/system.h b/arch/arm/mach-spear6xx/include/mach/system.h
new file mode 100644
index 0000000..0b1d2be
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/system.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/system.h
+ *
+ * SPEAr6xx Machine family specific architecture functions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_SYSTEM_H
+#define __MACH_SYSTEM_H
+
+#include <plat/system.h>
+
+#endif /* __MACH_SYSTEM_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/timex.h b/arch/arm/mach-spear6xx/include/mach/timex.h
new file mode 100644
index 0000000..ac1c5b0
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/timex.h
+ *
+ * SPEAr6XX machine family specific timex definitions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#include <plat/timex.h>
+
+#endif /* __MACH_TIMEX_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/uncompress.h b/arch/arm/mach-spear6xx/include/mach/uncompress.h
new file mode 100644
index 0000000..77f0765
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/uncompress.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/vmalloc.h b/arch/arm/mach-spear6xx/include/mach/vmalloc.h
new file mode 100644
index 0000000..4a0b56c
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/vmalloc.h
+ *
+ * Defining Vmalloc area for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#include <plat/vmalloc.h>
+
+#endif /* __MACH_VMALLOC_H */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 04/12] ST SPEAr: Added basic header files for SPEAr platform
2010-03-25 8:40 ` [PATCH V2 Resend 03/12] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/plat-spear/include/plat/debug-macro.S | 38 +++++++++++++++++++++
arch/arm/plat-spear/include/plat/gpio.h | 24 +++++++++++++
arch/arm/plat-spear/include/plat/io.h | 22 ++++++++++++
arch/arm/plat-spear/include/plat/memory.h | 20 +++++++++++
arch/arm/plat-spear/include/plat/system.h | 41 ++++++++++++++++++++++
arch/arm/plat-spear/include/plat/timex.h | 19 ++++++++++
arch/arm/plat-spear/include/plat/uncompress.h | 43 ++++++++++++++++++++++++
arch/arm/plat-spear/include/plat/vmalloc.h | 19 ++++++++++
8 files changed, 226 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-spear/include/plat/debug-macro.S
create mode 100644 arch/arm/plat-spear/include/plat/gpio.h
create mode 100644 arch/arm/plat-spear/include/plat/io.h
create mode 100644 arch/arm/plat-spear/include/plat/memory.h
create mode 100644 arch/arm/plat-spear/include/plat/system.h
create mode 100644 arch/arm/plat-spear/include/plat/timex.h
create mode 100644 arch/arm/plat-spear/include/plat/uncompress.h
create mode 100644 arch/arm/plat-spear/include/plat/vmalloc.h
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
new file mode 100644
index 0000000..1670734
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/plat-spear/include/plat/debug-macro.S
+ *
+ * Debugging macro include header for spear platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/amba/serial.h>
+#include <mach/spear.h>
+
+ .macro addruart, rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ moveq \rx, =SPEAR_DBG_UART_BASE @ Physical base
+ movne \rx, =VA_SPEAR_DBG_UART_BASE @ Virtual base
+ .endm
+
+ .macro senduart, rd, rx
+ strb \rd, [\rx, #UART01x_DR] @ ASC_TX_BUFFER
+ .endm
+
+ .macro waituart, rd, rx
+1001: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER
+ tst \rd, #UART01x_FR_TXFF @ TX_FULL
+ bne 1001b
+ .endm
+
+ .macro busyuart, rd, rx
+1002: ldr \rd, [\rx, #UART01x_FR] @ FLAG REGISTER
+ tst \rd, #UART011_FR_TXFE @ TX_EMPTY
+ beq 1002b
+ .endm
diff --git a/arch/arm/plat-spear/include/plat/gpio.h b/arch/arm/plat-spear/include/plat/gpio.h
new file mode 100644
index 0000000..b857c91
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/gpio.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/plat-spear/include/plat/gpio.h
+ *
+ * GPIO macros for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_GPIO_H
+#define __PLAT_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+#define gpio_cansleep __gpio_cansleep
+#define gpio_to_irq __gpio_to_irq
+
+#endif /* __PLAT_GPIO_H */
diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
new file mode 100644
index 0000000..4d4ba82
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/plat-spear/include/plat/io.h
+ *
+ * IO definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_IO_H
+#define __PLAT_IO_H
+
+#define IO_SPACE_LIMIT 0xFFFFFFFF
+
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif /* __PLAT_IO_H */
diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h
new file mode 100644
index 0000000..27a4aba
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/memory.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-spear/include/plat/memory.h
+ *
+ * Memory map for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_MEMORY_H
+#define __PLAT_MEMORY_H
+
+/* Physical DRAM offset */
+#define PHYS_OFFSET UL(0x00000000)
+
+#endif /* __PLAT_MEMORY_H */
diff --git a/arch/arm/plat-spear/include/plat/system.h b/arch/arm/plat-spear/include/plat/system.h
new file mode 100644
index 0000000..55a4e40
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/system.h
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/plat-spear/include/plat/system.h
+ *
+ * SPEAr platform specific architecture functions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_SYSTEM_H
+#define __PLAT_SYSTEM_H
+
+#include <asm/hardware/sp810.h>
+#include <linux/io.h>
+#include <mach/spear.h>
+
+static inline void arch_idle(void)
+{
+ /*
+ * This should do all the clock switching
+ * and wait for interrupt tricks
+ */
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ if (mode == 's') {
+ /* software reset, Jump into ROM at address 0 */
+ cpu_reset(0);
+ } else {
+ /* hardware reset, Use on-chip reset capability */
+ sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
+ }
+}
+
+#endif /* __PLAT_SYSTEM_H */
diff --git a/arch/arm/plat-spear/include/plat/timex.h b/arch/arm/plat-spear/include/plat/timex.h
new file mode 100644
index 0000000..914d09d
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/timex.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/plat-spear/include/plat/timex.h
+ *
+ * SPEAr platform specific timex definitions
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_TIMEX_H
+#define __PLAT_TIMEX_H
+
+#define CLOCK_TICK_RATE 48000000
+
+#endif /* __PLAT_TIMEX_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
new file mode 100644
index 0000000..99ba678
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -0,0 +1,43 @@
+/*
+ * arch/arm/plat-spear/include/plat/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/amba/serial.h>
+#include <mach/spear.h>
+
+#ifndef __PLAT_UNCOMPRESS_H
+#define __PLAT_UNCOMPRESS_H
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+ void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
+
+ while (readl(base + UART01x_FR) & UART01x_FR_TXFF)
+ barrier();
+
+ writel(c, base + UART01x_DR);
+}
+
+static inline void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif /* __PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
new file mode 100644
index 0000000..09e9372
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/plat-spear/include/plat/vmalloc.h
+ *
+ * Defining Vmalloc area for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_VMALLOC_H
+#define __PLAT_VMALLOC_H
+
+#define VMALLOC_END 0xF0000000
+
+#endif /* __PLAT_VMALLOC_H */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines
2010-03-25 8:40 ` [PATCH V2 Resend 04/12] ST SPEAr: Added basic header files for SPEAr platform Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 06/12] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR
2010-04-14 10:36 ` [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines Russell King - ARM Linux
0 siblings, 2 replies; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Clock framework for SPEAr is based upon clkdev framework for ARM
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/clock.c | 389 +++++++++++++++++++++
arch/arm/mach-spear3xx/include/mach/clkdev.h | 19 +
arch/arm/mach-spear6xx/clock.c | 483 ++++++++++++++++++++++++++
arch/arm/mach-spear6xx/include/mach/clkdev.h | 19 +
arch/arm/plat-spear/clock.c | 435 +++++++++++++++++++++++
arch/arm/plat-spear/include/plat/clkdev.h | 20 +
arch/arm/plat-spear/include/plat/clock.h | 126 +++++++
7 files changed, 1491 insertions(+), 0 deletions(-)
create mode 100755 arch/arm/mach-spear3xx/clock.c
create mode 100644 arch/arm/mach-spear3xx/include/mach/clkdev.h
create mode 100755 arch/arm/mach-spear6xx/clock.c
create mode 100644 arch/arm/mach-spear6xx/include/mach/clkdev.h
create mode 100755 arch/arm/plat-spear/clock.c
create mode 100644 arch/arm/plat-spear/include/plat/clkdev.h
create mode 100755 arch/arm/plat-spear/include/plat/clock.h
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
new file mode 100755
index 0000000..39f6ccf
--- /dev/null
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -0,0 +1,389 @@
+/*
+ * arch/arm/mach-spear3xx/clock.c
+ *
+ * SPEAr3xx machines clock framework source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <mach/misc_regs.h>
+#include <plat/clock.h>
+
+/* root clks */
+/* 32 KHz oscillator clock */
+static struct clk osc_32k_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 32000,
+};
+
+/* 24 MHz oscillator clock */
+static struct clk osc_24m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 24000000,
+};
+
+/* clock derived from 32 KHz osc clk */
+/* rtc clock */
+static struct clk rtc_clk = {
+ .pclk = &osc_32k_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = RTC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from 24 MHz osc clk */
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+};
+
+/* PLL1 clock */
+static struct clk pll1_clk = {
+ .pclk = &osc_24m_clk,
+ .en_reg = PLL1_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .recalc = &pll1_clk_recalc,
+ .private_data = &pll1_config,
+};
+
+/* PLL3 48 MHz clock */
+static struct clk pll3_48m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc_24m_clk,
+ .rate = 48000000,
+};
+
+/* watch dog timer clock */
+static struct clk wdt_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc_24m_clk,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from pll1 clk */
+/* cpu clock */
+static struct clk cpu_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .recalc = &follow_parent,
+};
+
+/* ahb configuration structure */
+static struct bus_clk_config ahb_config = {
+ .reg = CORE_CLK_CFG,
+ .mask = PLL_HCLK_RATIO_MASK,
+ .shift = PLL_HCLK_RATIO_SHIFT,
+};
+
+/* ahb clock */
+static struct clk ahb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .recalc = &bus_clk_recalc,
+ .private_data = &ahb_config,
+};
+
+/* uart configurations */
+static struct aux_clk_config uart_config = {
+ .synth_reg = UART_CLK_SYNT,
+};
+
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_mask = AUX_CLK_PLL3_MASK,
+ .scalable = 0,
+ },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+ .pclk_info = uart_pclk_info,
+ .pclk_count = ARRAY_SIZE(uart_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = UART_CLK_MASK,
+};
+
+/* uart clock */
+static struct clk uart_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UART_CLK_ENB,
+ .pclk_sel = &uart_pclk_sel,
+ .pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &aux_clk_recalc,
+ .private_data = &uart_config,
+};
+
+/* firda configurations */
+static struct aux_clk_config firda_config = {
+ .synth_reg = FIRDA_CLK_SYNT,
+};
+
+/* firda parents */
+static struct pclk_info firda_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_mask = AUX_CLK_PLL3_MASK,
+ .scalable = 0,
+ },
+};
+
+/* firda parent select structure */
+static struct pclk_sel firda_pclk_sel = {
+ .pclk_info = firda_pclk_info,
+ .pclk_count = ARRAY_SIZE(firda_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = FIRDA_CLK_MASK,
+};
+
+/* firda clock */
+static struct clk firda_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = FIRDA_CLK_ENB,
+ .pclk_sel = &firda_pclk_sel,
+ .pclk_sel_shift = FIRDA_CLK_SHIFT,
+ .recalc = &aux_clk_recalc,
+ .private_data = &firda_config,
+};
+
+/* gpt parents */
+static struct pclk_info gpt_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_mask = AUX_CLK_PLL3_MASK,
+ .scalable = 0,
+ },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt_pclk_sel = {
+ .pclk_info = gpt_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt0 configurations */
+static struct aux_clk_config gpt0_config = {
+ .synth_reg = PRSC1_CLK_CFG,
+};
+
+/* gpt0 timer clock */
+static struct clk gpt0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .recalc = &gpt_clk_recalc,
+ .private_data = &gpt0_config,
+};
+
+/* gpt1 configurations */
+static struct aux_clk_config gpt1_config = {
+ .synth_reg = PRSC2_CLK_CFG,
+};
+
+/* gpt1 timer clock */
+static struct clk gpt1_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT1_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT1_CLK_SHIFT,
+ .recalc = &gpt_clk_recalc,
+ .private_data = &gpt1_config,
+};
+
+/* gpt2 configurations */
+static struct aux_clk_config gpt2_config = {
+ .synth_reg = PRSC3_CLK_CFG,
+};
+
+/* gpt2 timer clock */
+static struct clk gpt2_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT2_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT2_CLK_SHIFT,
+ .recalc = &gpt_clk_recalc,
+ .private_data = &gpt2_config,
+};
+
+/* clock derived from pll3 clk */
+/* usbh clock */
+static struct clk usbh_clk = {
+ .pclk = &pll3_48m_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBH_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* usbd clock */
+static struct clk usbd_clk = {
+ .pclk = &pll3_48m_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clcd clock */
+static struct clk clcd_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll3_48m_clk,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from ahb clk */
+/* apb configuration structure */
+static struct bus_clk_config apb_config = {
+ .reg = CORE_CLK_CFG,
+ .mask = HCLK_PCLK_RATIO_MASK,
+ .shift = HCLK_PCLK_RATIO_SHIFT,
+};
+
+/* apb clock */
+static struct clk apb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ahb_clk,
+ .recalc = &bus_clk_recalc,
+ .private_data = &apb_config,
+};
+
+/* i2c clock */
+static struct clk i2c_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2C_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* dma clock */
+static struct clk dma_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* jpeg clock */
+static struct clk jpeg_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = JPEG_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gmac clock */
+static struct clk gmac_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GMAC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SMI_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* c3 clock */
+static struct clk c3_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = C3_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from apb clk */
+/* adc clock */
+static struct clk adc_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = ADC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp clock */
+static struct clk ssp_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio clock */
+static struct clk gpio_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* array of all spear 3xx clock lookups */
+static struct clk_lookup spear_clk_lookups[] = {
+ /* root clks */
+ { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
+ { .con_id = "osc_24m_clk", .clk = &osc_24m_clk},
+ /* clock derived from 32 KHz osc clk */
+ { .dev_id = "rtc", .clk = &rtc_clk},
+ /* clock derived from 24 MHz osc clk */
+ { .con_id = "pll1_clk", .clk = &pll1_clk},
+ { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
+ { .dev_id = "wdt", .clk = &wdt_clk},
+ /* clock derived from pll1 clk */
+ { .con_id = "cpu_clk", .clk = &cpu_clk},
+ { .con_id = "ahb_clk", .clk = &ahb_clk},
+ { .dev_id = "uart", .clk = &uart_clk},
+ { .dev_id = "firda", .clk = &firda_clk},
+ { .dev_id = "gpt0", .clk = &gpt0_clk},
+ { .dev_id = "gpt1", .clk = &gpt1_clk},
+ { .dev_id = "gpt2", .clk = &gpt2_clk},
+ /* clock derived from pll3 clk */
+ { .dev_id = "usbh", .clk = &usbh_clk},
+ { .dev_id = "usbd", .clk = &usbd_clk},
+ { .dev_id = "clcd", .clk = &clcd_clk},
+ /* clock derived from ahb clk */
+ { .con_id = "apb_clk", .clk = &apb_clk},
+ { .dev_id = "i2c", .clk = &i2c_clk},
+ { .dev_id = "dma", .clk = &dma_clk},
+ { .dev_id = "jpeg", .clk = &jpeg_clk},
+ { .dev_id = "gmac", .clk = &gmac_clk},
+ { .dev_id = "smi", .clk = &smi_clk},
+ { .dev_id = "c3", .clk = &c3_clk},
+ /* clock derived from apb clk */
+ { .dev_id = "adc", .clk = &adc_clk},
+ { .dev_id = "ssp", .clk = &ssp_clk},
+ { .dev_id = "gpio", .clk = &gpio_clk},
+};
+
+void __init clk_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ recalc_root_clocks();
+}
diff --git a/arch/arm/mach-spear3xx/include/mach/clkdev.h b/arch/arm/mach-spear3xx/include/mach/clkdev.h
new file mode 100644
index 0000000..a3d0733
--- /dev/null
+++ b/arch/arm/mach-spear3xx/include/mach/clkdev.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/clkdev.h
+ *
+ * Clock Dev framework definitions for SPEAr3xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#include <plat/clkdev.h>
+
+#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
new file mode 100755
index 0000000..13e27c7
--- /dev/null
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -0,0 +1,483 @@
+/*
+ * arch/arm/mach-spear6xx/clock.c
+ *
+ * SPEAr6xx machines clock framework source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <mach/misc_regs.h>
+#include <plat/clock.h>
+
+/* root clks */
+/* 32 KHz oscillator clock */
+static struct clk osc_32k_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 32000,
+};
+
+/* 30 MHz oscillator clock */
+static struct clk osc_30m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .rate = 30000000,
+};
+
+/* clock derived from 32 KHz osc clk */
+/* rtc clock */
+static struct clk rtc_clk = {
+ .pclk = &osc_32k_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = RTC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from 30 MHz osc clk */
+/* pll1 configuration structure */
+static struct pll_clk_config pll1_config = {
+ .mode_reg = PLL1_CTR,
+ .cfg_reg = PLL1_FRQ,
+};
+
+/* PLL1 clock */
+static struct clk pll1_clk = {
+ .pclk = &osc_30m_clk,
+ .en_reg = PLL1_CTR,
+ .en_reg_bit = PLL_ENABLE,
+ .recalc = &pll1_clk_recalc,
+ .private_data = &pll1_config,
+};
+
+/* PLL3 48 MHz clock */
+static struct clk pll3_48m_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc_30m_clk,
+ .rate = 48000000,
+};
+
+/* watch dog timer clock */
+static struct clk wdt_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &osc_30m_clk,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from pll1 clk */
+/* cpu clock */
+static struct clk cpu_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .recalc = &follow_parent,
+};
+
+/* ahb configuration structure */
+static struct bus_clk_config ahb_config = {
+ .reg = CORE_CLK_CFG,
+ .mask = PLL_HCLK_RATIO_MASK,
+ .shift = PLL_HCLK_RATIO_SHIFT,
+};
+
+/* ahb clock */
+static struct clk ahb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &pll1_clk,
+ .recalc = &bus_clk_recalc,
+ .private_data = &ahb_config,
+};
+
+/* uart parents */
+static struct pclk_info uart_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_mask = AUX_CLK_PLL3_MASK,
+ .scalable = 0,
+ },
+};
+
+/* uart parent select structure */
+static struct pclk_sel uart_pclk_sel = {
+ .pclk_info = uart_pclk_info,
+ .pclk_count = ARRAY_SIZE(uart_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = UART_CLK_MASK,
+};
+
+/* uart configurations */
+static struct aux_clk_config uart_config = {
+ .synth_reg = UART_CLK_SYNT,
+};
+
+/* uart0 clock */
+static struct clk uart0_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UART0_CLK_ENB,
+ .pclk_sel = &uart_pclk_sel,
+ .pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &aux_clk_recalc,
+ .private_data = &uart_config,
+};
+
+/* uart1 clock */
+static struct clk uart1_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = UART1_CLK_ENB,
+ .pclk_sel = &uart_pclk_sel,
+ .pclk_sel_shift = UART_CLK_SHIFT,
+ .recalc = &aux_clk_recalc,
+ .private_data = &uart_config,
+};
+
+/* firda configurations */
+static struct aux_clk_config firda_config = {
+ .synth_reg = FIRDA_CLK_SYNT,
+};
+
+/* firda parents */
+static struct pclk_info firda_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_mask = AUX_CLK_PLL3_MASK,
+ .scalable = 0,
+ },
+};
+
+/* firda parent select structure */
+static struct pclk_sel firda_pclk_sel = {
+ .pclk_info = firda_pclk_info,
+ .pclk_count = ARRAY_SIZE(firda_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = FIRDA_CLK_MASK,
+};
+
+/* firda clock */
+static struct clk firda_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = FIRDA_CLK_ENB,
+ .pclk_sel = &firda_pclk_sel,
+ .pclk_sel_shift = FIRDA_CLK_SHIFT,
+ .recalc = &aux_clk_recalc,
+ .private_data = &firda_config,
+};
+
+/* clcd configurations */
+static struct aux_clk_config clcd_config = {
+ .synth_reg = CLCD_CLK_SYNT,
+};
+
+/* clcd parents */
+static struct pclk_info clcd_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_mask = AUX_CLK_PLL3_MASK,
+ .scalable = 0,
+ },
+};
+
+/* clcd parent select structure */
+static struct pclk_sel clcd_pclk_sel = {
+ .pclk_info = clcd_pclk_info,
+ .pclk_count = ARRAY_SIZE(clcd_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = CLCD_CLK_MASK,
+};
+
+/* clcd clock */
+static struct clk clcd_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = CLCD_CLK_ENB,
+ .pclk_sel = &clcd_pclk_sel,
+ .pclk_sel_shift = CLCD_CLK_SHIFT,
+ .recalc = &aux_clk_recalc,
+ .private_data = &clcd_config,
+};
+
+/* gpt parents */
+static struct pclk_info gpt_pclk_info[] = {
+ {
+ .pclk = &pll1_clk,
+ .pclk_mask = AUX_CLK_PLL1_MASK,
+ .scalable = 1,
+ }, {
+ .pclk = &pll3_48m_clk,
+ .pclk_mask = AUX_CLK_PLL3_MASK,
+ .scalable = 0,
+ },
+};
+
+/* gpt parent select structure */
+static struct pclk_sel gpt_pclk_sel = {
+ .pclk_info = gpt_pclk_info,
+ .pclk_count = ARRAY_SIZE(gpt_pclk_info),
+ .pclk_sel_reg = PERIP_CLK_CFG,
+ .pclk_sel_mask = GPT_CLK_MASK,
+};
+
+/* gpt0_1 configurations */
+static struct aux_clk_config gpt0_1_config = {
+ .synth_reg = PRSC1_CLK_CFG,
+};
+
+/* gpt0 ARM1 subsystem timer clock */
+static struct clk gpt0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT0_CLK_SHIFT,
+ .recalc = &gpt_clk_recalc,
+ .private_data = &gpt0_1_config,
+};
+
+/* gpt1 timer clock */
+static struct clk gpt1_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT1_CLK_SHIFT,
+ .recalc = &gpt_clk_recalc,
+ .private_data = &gpt0_1_config,
+};
+
+/* gpt2 configurations */
+static struct aux_clk_config gpt2_config = {
+ .synth_reg = PRSC2_CLK_CFG,
+};
+
+/* gpt2 timer clock */
+static struct clk gpt2_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT2_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT2_CLK_SHIFT,
+ .recalc = &gpt_clk_recalc,
+ .private_data = &gpt2_config,
+};
+
+/* gpt3 configurations */
+static struct aux_clk_config gpt3_config = {
+ .synth_reg = PRSC3_CLK_CFG,
+};
+
+/* gpt3 timer clock */
+static struct clk gpt3_clk = {
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPT3_CLK_ENB,
+ .pclk_sel = &gpt_pclk_sel,
+ .pclk_sel_shift = GPT3_CLK_SHIFT,
+ .recalc = &gpt_clk_recalc,
+ .private_data = &gpt3_config,
+};
+
+/* clock derived from pll3 clk */
+/* usbh0 clock */
+static struct clk usbh0_clk = {
+ .pclk = &pll3_48m_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBH0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* usbh1 clock */
+static struct clk usbh1_clk = {
+ .pclk = &pll3_48m_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBH1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* usbd clock */
+static struct clk usbd_clk = {
+ .pclk = &pll3_48m_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = USBD_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from ahb clk */
+/* apb configuration structure */
+static struct bus_clk_config apb_config = {
+ .reg = CORE_CLK_CFG,
+ .mask = HCLK_PCLK_RATIO_MASK,
+ .shift = HCLK_PCLK_RATIO_SHIFT,
+};
+
+/* apb clock */
+static struct clk apb_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &ahb_clk,
+ .recalc = &bus_clk_recalc,
+ .private_data = &apb_config,
+};
+
+/* i2c clock */
+static struct clk i2c_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = I2C_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* dma clock */
+static struct clk dma_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = DMA_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* jpeg clock */
+static struct clk jpeg_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = JPEG_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gmac clock */
+static struct clk gmac_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GMAC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* smi clock */
+static struct clk smi_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SMI_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* fsmc clock */
+static struct clk fsmc_clk = {
+ .pclk = &ahb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = FSMC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* clock derived from apb clk */
+/* adc clock */
+static struct clk adc_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = ADC_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp0 clock */
+static struct clk ssp0_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP0_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp1 clock */
+static struct clk ssp1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* ssp2 clock */
+static struct clk ssp2_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = SSP2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio0 ARM subsystem clock */
+static struct clk gpio0_clk = {
+ .flags = ALWAYS_ENABLED,
+ .pclk = &apb_clk,
+ .recalc = &follow_parent,
+};
+
+/* gpio1 clock */
+static struct clk gpio1_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO1_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* gpio2 clock */
+static struct clk gpio2_clk = {
+ .pclk = &apb_clk,
+ .en_reg = PERIP1_CLK_ENB,
+ .en_reg_bit = GPIO2_CLK_ENB,
+ .recalc = &follow_parent,
+};
+
+/* array of all spear 6xx clock lookups */
+static struct clk_lookup spear_clk_lookups[] = {
+ /* root clks */
+ { .con_id = "osc_32k_clk", .clk = &osc_32k_clk},
+ { .con_id = "osc_30m_clk", .clk = &osc_30m_clk},
+ /* clock derived from 32 KHz os clk */
+ { .dev_id = "rtc", .clk = &rtc_clk},
+ /* clock derived from 30 MHz os clk */
+ { .con_id = "pll1_clk", .clk = &pll1_clk},
+ { .con_id = "pll3_48m_clk", .clk = &pll3_48m_clk},
+ { .dev_id = "wdt", .clk = &wdt_clk},
+ /* clock derived from pll1 clk */
+ { .con_id = "cpu_clk", .clk = &cpu_clk},
+ { .con_id = "ahb_clk", .clk = &ahb_clk},
+ { .dev_id = "uart0", .clk = &uart0_clk},
+ { .dev_id = "uart1", .clk = &uart1_clk},
+ { .dev_id = "firda", .clk = &firda_clk},
+ { .dev_id = "clcd", .clk = &clcd_clk},
+ { .dev_id = "gpt0", .clk = &gpt0_clk},
+ { .dev_id = "gpt1", .clk = &gpt1_clk},
+ { .dev_id = "gpt2", .clk = &gpt2_clk},
+ { .dev_id = "gpt3", .clk = &gpt3_clk},
+ /* clock derived from pll3 clk */
+ { .dev_id = "usbh0", .clk = &usbh0_clk},
+ { .dev_id = "usbh1", .clk = &usbh1_clk},
+ { .dev_id = "usbd", .clk = &usbd_clk},
+ /* clock derived from ahb clk */
+ { .con_id = "apb_clk", .clk = &apb_clk},
+ { .dev_id = "i2c", .clk = &i2c_clk},
+ { .dev_id = "dma", .clk = &dma_clk},
+ { .dev_id = "jpeg", .clk = &jpeg_clk},
+ { .dev_id = "gmac", .clk = &gmac_clk},
+ { .dev_id = "smi", .clk = &smi_clk},
+ { .dev_id = "fsmc", .clk = &fsmc_clk},
+ /* clock derived from apb clk */
+ { .dev_id = "adc", .clk = &adc_clk},
+ { .dev_id = "ssp0", .clk = &ssp0_clk},
+ { .dev_id = "ssp1", .clk = &ssp1_clk},
+ { .dev_id = "ssp2", .clk = &ssp2_clk},
+ { .dev_id = "gpio0", .clk = &gpio0_clk},
+ { .dev_id = "gpio1", .clk = &gpio1_clk},
+ { .dev_id = "gpio2", .clk = &gpio2_clk},
+};
+
+void __init clk_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
+ clk_register(&spear_clk_lookups[i]);
+
+ recalc_root_clocks();
+}
diff --git a/arch/arm/mach-spear6xx/include/mach/clkdev.h b/arch/arm/mach-spear6xx/include/mach/clkdev.h
new file mode 100644
index 0000000..05676bf
--- /dev/null
+++ b/arch/arm/mach-spear6xx/include/mach/clkdev.h
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear6xx/include/mach/clkdev.h
+ *
+ * Clock Dev framework definitions for SPEAr6xx machine family
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#include <plat/clkdev.h>
+
+#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
new file mode 100755
index 0000000..ee4f90e
--- /dev/null
+++ b/arch/arm/plat-spear/clock.c
@@ -0,0 +1,435 @@
+/*
+ * arch/arm/plat-spear/clock.c
+ *
+ * Clock framework for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/bug.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <mach/misc_regs.h>
+#include <plat/clock.h>
+
+static DEFINE_SPINLOCK(clocks_lock);
+static LIST_HEAD(root_clks);
+
+static void propagate_rate(struct list_head *);
+
+static int generic_clk_enable(struct clk *clk)
+{
+ unsigned int val;
+
+ if (!clk->en_reg)
+ return -EFAULT;
+
+ val = readl(clk->en_reg);
+ if (unlikely(clk->flags & RESET_TO_ENABLE))
+ val &= ~(1 << clk->en_reg_bit);
+ else
+ val |= 1 << clk->en_reg_bit;
+
+ writel(val, clk->en_reg);
+
+ return 0;
+}
+
+static void generic_clk_disable(struct clk *clk)
+{
+ unsigned int val;
+
+ if (!clk->en_reg)
+ return;
+
+ val = readl(clk->en_reg);
+ if (unlikely(clk->flags & RESET_TO_ENABLE))
+ val |= 1 << clk->en_reg_bit;
+ else
+ val &= ~(1 << clk->en_reg_bit);
+
+ writel(val, clk->en_reg);
+}
+
+/* generic clk ops */
+static struct clkops generic_clkops = {
+ .enable = generic_clk_enable,
+ .disable = generic_clk_disable,
+};
+
+/*
+ * clk_enable - inform the system when the clock source should be running.
+ * @clk: clock source
+ *
+ * If the clock can not be enabled/disabled, this should return success.
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+ int ret = 0;
+
+ if (!clk || IS_ERR(clk))
+ return -EFAULT;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ if (clk->usage_count == 0) {
+ if (clk->ops && clk->ops->enable)
+ ret = clk->ops->enable(clk);
+ }
+ clk->usage_count++;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/*
+ * clk_disable - inform the system when the clock source is no longer required.
+ * @clk: clock source
+ *
+ * Inform the system that a clock source is no longer required by
+ * a driver and may be shut down.
+ *
+ * Implementation detail: if the clock source is shared between
+ * multiple drivers, clk_enable() calls must be balanced by the
+ * same number of clk_disable() calls for the clock source to be
+ * disabled.
+ */
+void clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+
+ if (!clk || IS_ERR(clk))
+ return;
+
+ WARN_ON(clk->usage_count == 0);
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ clk->usage_count--;
+ if (clk->usage_count == 0) {
+ if (clk->ops && clk->ops->disable)
+ clk->ops->disable(clk);
+ }
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+/**
+ * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
+ * This is only valid once the clock source has been enabled.
+ * @clk: clock source
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+ unsigned long flags, rate;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ rate = clk->rate;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/**
+ * clk_set_parent - set the parent clock source for this clock
+ * @clk: clock source
+ * @parent: parent clock source
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ int i, found = 0, val = 0;
+ unsigned long flags;
+
+ if (!clk || IS_ERR(clk) || !parent || IS_ERR(parent))
+ return -EFAULT;
+ if (clk->usage_count)
+ return -EBUSY;
+ if (!clk->pclk_sel)
+ return -EPERM;
+ if (clk->pclk == parent)
+ return 0;
+
+ for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
+ if (clk->pclk_sel->pclk_info[i].pclk == parent) {
+ found = 1;
+ break;
+ }
+ }
+
+ if (!found)
+ return -EINVAL;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ /* reflect parent change in hardware */
+ val = readl(clk->pclk_sel->pclk_sel_reg);
+ val &= ~(clk->pclk_sel->pclk_sel_mask << clk->pclk_sel_shift);
+ val |= clk->pclk_sel->pclk_info[i].pclk_mask << clk->pclk_sel_shift;
+ writel(val, clk->pclk_sel->pclk_sel_reg);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ /* reflect parent change in software */
+ clk->recalc(clk);
+ propagate_rate(&clk->children);
+ return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/* registers clock in platform clock framework */
+void clk_register(struct clk_lookup *cl)
+{
+ struct clk *clk = cl->clk;
+ unsigned long flags;
+
+ if (!clk || IS_ERR(clk))
+ return;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+
+ INIT_LIST_HEAD(&clk->children);
+ if (clk->flags & ALWAYS_ENABLED)
+ clk->ops = NULL;
+ else if (!clk->ops)
+ clk->ops = &generic_clkops;
+
+ /* root clock don't have any parents */
+ if (!clk->pclk && !clk->pclk_sel) {
+ list_add(&clk->sibling, &root_clks);
+ /* add clocks with only one parent to parent's children list */
+ } else if (clk->pclk && !clk->pclk_sel) {
+ list_add(&clk->sibling, &clk->pclk->children);
+ } else {
+ /* add clocks with > 1 parent to 1st parent's children list */
+ list_add(&clk->sibling,
+ &clk->pclk_sel->pclk_info[0].pclk->children);
+ }
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ /* add clock to arm clockdev framework */
+ clkdev_add(cl);
+}
+
+/**
+ * propagate_rate - recalculate and propagate all clocks in list head
+ *
+ * Recalculates all root clocks in list head, which if the clock's .recalc is
+ * set correctly, should also propagate their rates.
+ */
+static void propagate_rate(struct list_head *lhead)
+{
+ struct clk *clkp, *_temp;
+
+ list_for_each_entry_safe(clkp, _temp, lhead, sibling) {
+ if (clkp->recalc)
+ clkp->recalc(clkp);
+ propagate_rate(&clkp->children);
+ }
+}
+
+/* returns current programmed clocks clock info structure */
+static struct pclk_info *pclk_info_get(struct clk *clk)
+{
+ unsigned int mask, i;
+ unsigned long flags;
+ struct pclk_info *info = NULL;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ mask = (readl(clk->pclk_sel->pclk_sel_reg) >> clk->pclk_sel_shift)
+ & clk->pclk_sel->pclk_sel_mask;
+
+ for (i = 0; i < clk->pclk_sel->pclk_count; i++) {
+ if (clk->pclk_sel->pclk_info[i].pclk_mask == mask)
+ info = &clk->pclk_sel->pclk_info[i];
+ }
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ return info;
+}
+
+/*
+ * Set pclk as cclk's parent and add clock sibling node to current parents
+ * children list
+ */
+static void change_parent(struct clk *cclk, struct clk *pclk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ list_del(&cclk->sibling);
+ list_add(&cclk->sibling, &pclk->children);
+
+ cclk->pclk = pclk;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * calculates current programmed rate of pll1
+ *
+ * In normal mode
+ * rate = (2 * M[15:8] * Fin)/(N * 2^P)
+ *
+ * In Dithered mode
+ * rate = (2 * M[15:0] * Fin)/(256 * N * 2^P)
+ */
+void pll1_clk_recalc(struct clk *clk)
+{
+ struct pll_clk_config *config = clk->private_data;
+ unsigned int num = 2, den = 0, val, mode = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ mode = (readl(config->mode_reg) >> PLL_MODE_SHIFT) &
+ PLL_MODE_MASK;
+
+ val = readl(config->cfg_reg);
+ /* calculate denominator */
+ den = (val >> PLL_DIV_P_SHIFT) & PLL_DIV_P_MASK;
+ den = 1 << den;
+ den *= (val >> PLL_DIV_N_SHIFT) & PLL_DIV_N_MASK;
+
+ /* calculate numerator & denominator */
+ if (!mode) {
+ /* Normal mode */
+ num *= (val >> PLL_NORM_FDBK_M_SHIFT) & PLL_NORM_FDBK_M_MASK;
+ } else {
+ /* Dithered mode */
+ num *= (val >> PLL_DITH_FDBK_M_SHIFT) & PLL_DITH_FDBK_M_MASK;
+ den *= 256;
+ }
+
+ clk->rate = (((clk->pclk->rate/10000) * num) / den) * 10000;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/* calculates current programmed rate of ahb or apb bus */
+void bus_clk_recalc(struct clk *clk)
+{
+ struct bus_clk_config *config = clk->private_data;
+ unsigned int div;
+ unsigned long flags;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ div = ((readl(config->reg) >> config->shift) & config->mask) + 1;
+ clk->rate = (unsigned long)clk->pclk->rate / div;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * calculates current programmed rate of auxiliary synthesizers
+ * used by: UART, FIRDA
+ *
+ * Fout from synthesizer can be given from two equations:
+ * Fout1 = (Fin * X/Y)/2
+ * Fout2 = Fin * X/Y
+ *
+ * Selection of eqn 1 or 2 is programmed in register
+ */
+void aux_clk_recalc(struct clk *clk)
+{
+ struct aux_clk_config *config = clk->private_data;
+ struct pclk_info *pclk_info = NULL;
+ unsigned int num = 1, den = 1, val, eqn;
+ unsigned long flags;
+
+ /* get current programmed parent */
+ pclk_info = pclk_info_get(clk);
+ if (!pclk_info) {
+ spin_lock_irqsave(&clocks_lock, flags);
+ clk->pclk = NULL;
+ clk->rate = 0;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ return;
+ }
+
+ change_parent(clk, pclk_info->pclk);
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ if (pclk_info->scalable) {
+ val = readl(config->synth_reg);
+
+ eqn = (val >> AUX_EQ_SEL_SHIFT) & AUX_EQ_SEL_MASK;
+ if (eqn == AUX_EQ1_SEL)
+ den *= 2;
+
+ /* calculate numerator */
+ num = (val >> AUX_XSCALE_SHIFT) & AUX_XSCALE_MASK;
+
+ /* calculate denominator */
+ den *= (val >> AUX_YSCALE_SHIFT) & AUX_YSCALE_MASK;
+ val = (((clk->pclk->rate/10000) * num) / den) * 10000;
+ } else
+ val = clk->pclk->rate;
+
+ clk->rate = val;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * calculates current programmed rate of gpt synthesizers
+ * Fout from synthesizer can be given from below equations:
+ * Fout= Fin/((2 ^ (N+1)) * (M+1))
+ */
+void gpt_clk_recalc(struct clk *clk)
+{
+ struct aux_clk_config *config = clk->private_data;
+ struct pclk_info *pclk_info = NULL;
+ unsigned int div = 1, val;
+ unsigned long flags;
+
+ pclk_info = pclk_info_get(clk);
+ if (!pclk_info) {
+ spin_lock_irqsave(&clocks_lock, flags);
+ clk->pclk = NULL;
+ clk->rate = 0;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ return;
+ }
+
+ change_parent(clk, pclk_info->pclk);
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ if (pclk_info->scalable) {
+ val = readl(config->synth_reg);
+ div += (val >> GPT_MSCALE_SHIFT) & GPT_MSCALE_MASK;
+ div *= 1 << (((val >> GPT_NSCALE_SHIFT) & GPT_NSCALE_MASK) + 1);
+ }
+
+ clk->rate = (unsigned long)clk->pclk->rate / div;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/*
+ * Used for clocks that always have same value as the parent clock divided by a
+ * fixed divisor
+ */
+void follow_parent(struct clk *clk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ clk->rate = clk->pclk->rate;
+ spin_unlock_irqrestore(&clocks_lock, flags);
+}
+
+/**
+ * recalc_root_clocks - recalculate and propagate all root clocks
+ *
+ * Recalculates all root clocks (clocks with no parent), which if the
+ * clock's .recalc is set correctly, should also propagate their rates.
+ */
+void recalc_root_clocks(void)
+{
+ propagate_rate(&root_clks);
+}
diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h
new file mode 100644
index 0000000..a2d0112
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/clkdev.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/plat-spear/include/plat/clkdev.h
+ *
+ * Clock Dev framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_CLKDEV_H
+#define __PLAT_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif /* __PLAT_CLKDEV_H */
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
new file mode 100755
index 0000000..298bafc
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -0,0 +1,126 @@
+/*
+ * arch/arm/plat-spear/include/plat/clock.h
+ *
+ * Clock framework definitions for SPEAr platform
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_CLOCK_H
+#define __PLAT_CLOCK_H
+
+#include <linux/list.h>
+#include <asm/clkdev.h>
+#include <linux/types.h>
+
+/* clk structure flags */
+#define ALWAYS_ENABLED (1 << 0) /* clock always enabled */
+#define RESET_TO_ENABLE (1 << 1) /* reset register bit to enable clk */
+
+/**
+ * struct clkops - clock operations
+ * @enable: pointer to clock enable function
+ * @disable: pointer to clock disable function
+ */
+struct clkops {
+ int (*enable) (struct clk *);
+ void (*disable) (struct clk *);
+};
+
+/**
+ * struct pclk_info - parents info
+ * @pclk: pointer to parent clk
+ * @pclk_mask: value to be written for selecting this parent
+ * @scalable: Is parent scalable (1 - YES, 0 - NO)
+ */
+struct pclk_info {
+ struct clk *pclk;
+ u8 pclk_mask;
+ u8 scalable;
+};
+
+/**
+ * struct pclk_sel - parents selection configuration
+ * @pclk_info: pointer to array of parent clock info
+ * @pclk_count: number of parents
+ * @pclk_sel_reg: register for selecting a parent
+ * @pclk_sel_mask: mask for selecting parent (can be used to clear bits also)
+ */
+struct pclk_sel {
+ struct pclk_info *pclk_info;
+ u8 pclk_count;
+ unsigned int *pclk_sel_reg;
+ unsigned int pclk_sel_mask;
+};
+
+/**
+ * struct clk - clock structure
+ * @usage_count: num of users who enabled this clock
+ * @flags: flags for clock properties
+ * @rate: programmed clock rate in Hz
+ * @en_reg: clk enable/disable reg
+ * @en_reg_bit: clk enable/disable bit
+ * @ops: clk enable/disable ops - generic_clkops selected if NULL
+ * @recalc: pointer to clock rate recalculate function
+ * @pclk: current parent clk
+ * @pclk_sel: pointer to parent selection structure
+ * @pclk_sel_shift: register shift for selecting parent of this clock
+ * @children: list for childrens or this clock
+ * @sibling: node for list of clocks having same parents
+ * @private_data: clock specific private data
+ */
+struct clk {
+ unsigned int usage_count;
+ unsigned int flags;
+ unsigned long rate;
+ unsigned int *en_reg;
+ u8 en_reg_bit;
+ const struct clkops *ops;
+ void (*recalc) (struct clk *);
+
+ struct clk *pclk;
+ struct pclk_sel *pclk_sel;
+ unsigned int pclk_sel_shift;
+
+ struct list_head children;
+ struct list_head sibling;
+ void *private_data;
+};
+
+/* pll configuration structure */
+struct pll_clk_config {
+ unsigned int *mode_reg;
+ unsigned int *cfg_reg;
+};
+
+/* ahb and apb bus configuration structure */
+struct bus_clk_config {
+ unsigned int *reg;
+ unsigned int mask;
+ unsigned int shift;
+};
+
+/*
+ * Aux clk configuration structure: applicable to GPT, UART and FIRDA
+ */
+struct aux_clk_config {
+ unsigned int *synth_reg;
+};
+
+/* platform specific clock functions */
+void clk_register(struct clk_lookup *cl);
+void recalc_root_clocks(void);
+
+/* clock recalc functions */
+void follow_parent(struct clk *clk);
+void pll1_clk_recalc(struct clk *clk);
+void bus_clk_recalc(struct clk *clk);
+void gpt_clk_recalc(struct clk *clk);
+void aux_clk_recalc(struct clk *clk);
+
+#endif /* __PLAT_CLOCK_H */
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 06/12] ST SPEAr: Added source files for SPEAr platform
2010-03-25 8:40 ` [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 07/12] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR
2010-04-14 10:36 ` [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines Russell King - ARM Linux
1 sibling, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
---
arch/arm/plat-spear/Kconfig | 31 +++++
arch/arm/plat-spear/Makefile | 6 +
arch/arm/plat-spear/time.c | 292 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 329 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/plat-spear/Kconfig
create mode 100644 arch/arm/plat-spear/Makefile
create mode 100644 arch/arm/plat-spear/time.c
diff --git a/arch/arm/plat-spear/Kconfig b/arch/arm/plat-spear/Kconfig
new file mode 100644
index 0000000..1bb3dbc
--- /dev/null
+++ b/arch/arm/plat-spear/Kconfig
@@ -0,0 +1,31 @@
+#
+# SPEAr Platform configuration file
+#
+
+if PLAT_SPEAR
+
+choice
+ prompt "ST SPEAr Family"
+ default ARCH_SPEAR3XX
+
+config ARCH_SPEAR3XX
+ bool "SPEAr3XX"
+ select ARM_VIC
+ select CPU_ARM926T
+ help
+ Supports for ARM's SPEAR3XX family
+
+config ARCH_SPEAR6XX
+ bool "SPEAr6XX"
+ select ARM_VIC
+ select CPU_ARM926T
+ help
+ Supports for ARM's SPEAR6XX family
+
+endchoice
+
+# Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear3xx/Kconfig"
+source "arch/arm/mach-spear6xx/Kconfig"
+
+endif
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
new file mode 100644
index 0000000..96f9ac3
--- /dev/null
+++ b/arch/arm/plat-spear/Makefile
@@ -0,0 +1,6 @@
+#
+# SPEAr Platform specific Makefile
+#
+
+# Common support
+obj-y := clock.o time.o
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
new file mode 100644
index 0000000..a1025d3
--- /dev/null
+++ b/arch/arm/plat-spear/time.c
@@ -0,0 +1,292 @@
+/*
+ * arch/arm/plat-spear/time.c
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Shiraz Hashim<shiraz.hashim@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/time.h>
+#include <linux/irq.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/spear.h>
+#include <mach/generic.h>
+
+/*
+ * We would use TIMER0 and TIMER1 as clockevent and clocksource.
+ * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
+ * they share same functional clock. Any change in one's functional clock will
+ * also affect other timer.
+ */
+
+#define CLKEVT 0 /* gpt0, channel0 as clockevent */
+#define CLKSRC 1 /* gpt0, channel1 as clocksource */
+
+/* Register offsets, x is channel number */
+#define CR(x) ((x) * 0x80 + 0x80)
+#define IR(x) ((x) * 0x80 + 0x84)
+#define LOAD(x) ((x) * 0x80 + 0x88)
+#define COUNT(x) ((x) * 0x80 + 0x8C)
+
+/* Reg bit definitions */
+#define CTRL_INT_ENABLE 0x0100
+#define CTRL_ENABLE 0x0020
+#define CTRL_ONE_SHOT 0x0010
+
+#define CTRL_PRESCALER1 0x0
+#define CTRL_PRESCALER2 0x1
+#define CTRL_PRESCALER4 0x2
+#define CTRL_PRESCALER8 0x3
+#define CTRL_PRESCALER16 0x4
+#define CTRL_PRESCALER32 0x5
+#define CTRL_PRESCALER64 0x6
+#define CTRL_PRESCALER128 0x7
+#define CTRL_PRESCALER256 0x8
+
+#define INT_STATUS 0x1
+
+static __iomem void *gpt_base;
+static struct clk *gpt_clk;
+
+static void clockevent_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk_event_dev);
+static int clockevent_next_event(unsigned long evt,
+ struct clock_event_device *clk_event_dev);
+
+/*
+ * Following clocksource_set_clock and clockevent_set_clock picked
+ * from arch/mips/kernel/time.c
+ */
+
+void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
+{
+ u64 temp;
+ u32 shift;
+
+ /* Find a shift value */
+ for (shift = 32; shift > 0; shift--) {
+ temp = (u64) NSEC_PER_SEC << shift;
+ do_div(temp, clock);
+ if ((temp >> 32) == 0)
+ break;
+ }
+ cs->shift = shift;
+ cs->mult = (u32) temp;
+}
+
+void __init clockevent_set_clock(struct clock_event_device *cd,
+ unsigned int clock)
+{
+ u64 temp;
+ u32 shift;
+
+ /* Find a shift value */
+ for (shift = 32; shift > 0; shift--) {
+ temp = (u64) clock << shift;
+ do_div(temp, NSEC_PER_SEC);
+ if ((temp >> 32) == 0)
+ break;
+ }
+ cd->shift = shift;
+ cd->mult = (u32) temp;
+}
+
+static cycle_t clocksource_read_cycles(struct clocksource *cs)
+{
+ return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
+}
+
+static struct clocksource clksrc = {
+ .name = "tmr1",
+ .rating = 200, /* its a pretty decent clock */
+ .read = clocksource_read_cycles,
+ .mask = 0xFFFF, /* 16 bits */
+ .mult = 0, /* to be computed */
+ .shift = 0, /* to be computed */
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void spear_clocksource_init(void)
+{
+ u32 tick_rate;
+ u16 val;
+
+ /* program the prescaler (/256)*/
+ writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
+
+ /* find out actual clock driving Timer */
+ tick_rate = clk_get_rate(gpt_clk);
+ tick_rate >>= CTRL_PRESCALER256;
+
+ writew(0xFFFF, gpt_base + LOAD(CLKSRC));
+
+ val = readw(gpt_base + CR(CLKSRC));
+ val &= ~CTRL_ONE_SHOT; /* autoreload mode */
+ val |= CTRL_ENABLE ;
+ writew(val, gpt_base + CR(CLKSRC));
+
+ clocksource_set_clock(&clksrc, tick_rate);
+
+ /* register the clocksource */
+ clocksource_register(&clksrc);
+}
+
+static struct clock_event_device clkevt = {
+ .name = "tmr0",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = clockevent_set_mode,
+ .set_next_event = clockevent_next_event,
+ .shift = 0, /* to be computed */
+};
+
+static void clockevent_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk_event_dev)
+{
+ u32 period;
+ u16 val;
+
+ /* stop the timer */
+ val = readw(gpt_base + CR(CLKEVT));
+ val &= ~CTRL_ENABLE;
+ writew(val, gpt_base + CR(CLKEVT));
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ period = clk_get_rate(gpt_clk) / HZ;
+ period >>= CTRL_PRESCALER16;
+ writew(period, gpt_base + LOAD(CLKEVT));
+
+ val = readw(gpt_base + CR(CLKEVT));
+ val &= ~CTRL_ONE_SHOT;
+ val |= CTRL_ENABLE | CTRL_INT_ENABLE;
+ writew(val, gpt_base + CR(CLKEVT));
+
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ val = readw(gpt_base + CR(CLKEVT));
+ val |= CTRL_ONE_SHOT;
+ writew(val, gpt_base + CR(CLKEVT));
+
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_RESUME:
+
+ break;
+ default:
+ pr_err("Invalid mode requested\n");
+ break;
+ }
+}
+
+static int clockevent_next_event(unsigned long cycles,
+ struct clock_event_device *clk_event_dev)
+{
+ u16 val;
+
+ writew(cycles, gpt_base + LOAD(CLKEVT));
+
+ val = readw(gpt_base + CR(CLKEVT));
+ val |= CTRL_ENABLE | CTRL_INT_ENABLE;
+ writew(val, gpt_base + CR(CLKEVT));
+
+ return 0;
+}
+
+static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = &clkevt;
+
+ writew(INT_STATUS, gpt_base + IR(CLKEVT));
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction spear_timer_irq = {
+ .name = "timer",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = spear_timer_interrupt
+};
+
+static void __init spear_clockevent_init(void)
+{
+ u32 tick_rate;
+
+ /* program the prescaler */
+ writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
+
+ tick_rate = clk_get_rate(gpt_clk);
+ tick_rate >>= CTRL_PRESCALER16;
+
+ clockevent_set_clock(&clkevt, tick_rate);
+
+ clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
+ &clkevt);
+ clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
+
+ clkevt.cpumask = cpumask_of(0);
+
+ clockevents_register_device(&clkevt);
+
+ setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq);
+}
+
+void __init spear_setup_timer(void)
+{
+ struct clk *pll3_clk;
+
+ if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) {
+ pr_err("%s:cannot get IO addr\n", __func__);
+ return;
+ }
+
+ gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K);
+ if (!gpt_base) {
+ pr_err("%s:ioremap failed for gpt\n", __func__);
+ goto err_mem;
+ }
+
+ gpt_clk = clk_get_sys("gpt0", NULL);
+ if (!gpt_clk) {
+ pr_err("%s:couldn't get clk for gpt\n", __func__);
+ goto err_iomap;
+ }
+
+ pll3_clk = clk_get(NULL, "pll3_48m_clk");
+ if (!pll3_clk) {
+ pr_err("%s:couldn't get PLL3 as parent for gpt\n", __func__);
+ goto err_iomap;
+ }
+
+ clk_set_parent(gpt_clk, pll3_clk);
+
+ spear_clockevent_init();
+ spear_clocksource_init();
+
+ return;
+
+err_iomap:
+ iounmap(gpt_base);
+
+err_mem:
+ release_mem_region(SPEAR_GPT0_BASE, SZ_1K);
+}
+
+struct sys_timer spear_sys_timer = {
+ .init = spear_setup_timer,
+};
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 07/12] ST SPEAr: Added source files for SPEAr3xx machine family
2010-03-25 8:40 ` [PATCH V2 Resend 06/12] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 08/12] ST SPEAr: Added source files for SPEAr6xx " Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/Kconfig | 33 +++++++++++
arch/arm/mach-spear3xx/Kconfig300 | 17 ++++++
arch/arm/mach-spear3xx/Kconfig310 | 17 ++++++
arch/arm/mach-spear3xx/Kconfig320 | 17 ++++++
arch/arm/mach-spear3xx/Makefile | 26 +++++++++
arch/arm/mach-spear3xx/Makefile.boot | 3 +
arch/arm/mach-spear3xx/spear300.c | 45 +++++++++++++++
arch/arm/mach-spear3xx/spear300_evb.c | 55 ++++++++++++++++++
arch/arm/mach-spear3xx/spear310.c | 25 ++++++++
arch/arm/mach-spear3xx/spear310_evb.c | 54 +++++++++++++++++
arch/arm/mach-spear3xx/spear320.c | 25 ++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 54 +++++++++++++++++
arch/arm/mach-spear3xx/spear3xx.c | 101 +++++++++++++++++++++++++++++++++
13 files changed, 472 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear3xx/Kconfig
create mode 100644 arch/arm/mach-spear3xx/Kconfig300
create mode 100644 arch/arm/mach-spear3xx/Kconfig310
create mode 100644 arch/arm/mach-spear3xx/Kconfig320
create mode 100644 arch/arm/mach-spear3xx/Makefile
create mode 100644 arch/arm/mach-spear3xx/Makefile.boot
create mode 100644 arch/arm/mach-spear3xx/spear300.c
create mode 100644 arch/arm/mach-spear3xx/spear300_evb.c
create mode 100644 arch/arm/mach-spear3xx/spear310.c
create mode 100644 arch/arm/mach-spear3xx/spear310_evb.c
create mode 100644 arch/arm/mach-spear3xx/spear320.c
create mode 100644 arch/arm/mach-spear3xx/spear320_evb.c
create mode 100644 arch/arm/mach-spear3xx/spear3xx.c
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
new file mode 100644
index 0000000..20d1317
--- /dev/null
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -0,0 +1,33 @@
+#
+# SPEAr3XX Machine configuration file
+#
+
+if ARCH_SPEAR3XX
+
+choice
+ prompt "SPEAr3XX Family"
+ default MACH_SPEAR300
+
+config MACH_SPEAR300
+ bool "SPEAr300"
+ help
+ Supports ST SPEAr300 Machine
+
+config MACH_SPEAR310
+ bool "SPEAr310"
+ help
+ Supports ST SPEAr310 Machine
+
+config MACH_SPEAR320
+ bool "SPEAr320"
+ help
+ Supports ST SPEAr320 Machine
+
+endchoice
+
+# Adding SPEAr3XX machine specific configuration files
+source "arch/arm/mach-spear3xx/Kconfig300"
+source "arch/arm/mach-spear3xx/Kconfig310"
+source "arch/arm/mach-spear3xx/Kconfig320"
+
+endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300
new file mode 100644
index 0000000..c519a05
--- /dev/null
+++ b/arch/arm/mach-spear3xx/Kconfig300
@@ -0,0 +1,17 @@
+#
+# SPEAr300 machine configuration file
+#
+
+if MACH_SPEAR300
+
+choice
+ prompt "SPEAr300 Boards"
+ default BOARD_SPEAR300_EVB
+
+config BOARD_SPEAR300_EVB
+ bool "SPEAr300 Evaluation Board"
+ help
+ Supports ST SPEAr300 Evaluation Board
+endchoice
+
+endif #MACH_SPEAR300
diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310
new file mode 100644
index 0000000..60e7442
--- /dev/null
+++ b/arch/arm/mach-spear3xx/Kconfig310
@@ -0,0 +1,17 @@
+#
+# SPEAr310 machine configuration file
+#
+
+if MACH_SPEAR310
+
+choice
+ prompt "SPEAr310 Boards"
+ default BOARD_SPEAR310_EVB
+
+config BOARD_SPEAR310_EVB
+ bool "SPEAr310 Evaluation Board"
+ help
+ Supports ST SPEAr310 Evaluation Board
+endchoice
+
+endif #MACH_SPEAR310
diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320
new file mode 100644
index 0000000..1c1d438
--- /dev/null
+++ b/arch/arm/mach-spear3xx/Kconfig320
@@ -0,0 +1,17 @@
+#
+# SPEAr320 machine configuration file
+#
+
+if MACH_SPEAR320
+
+choice
+ prompt "SPEAr320 Boards"
+ default BOARD_SPEAR320_EVB
+
+config BOARD_SPEAR320_EVB
+ bool "SPEAr320 Evaluation Board"
+ help
+ Supports ST SPEAr320 Evaluation Board
+endchoice
+
+endif #MACH_SPEAR320
diff --git a/arch/arm/mach-spear3xx/Makefile b/arch/arm/mach-spear3xx/Makefile
new file mode 100644
index 0000000..b248624
--- /dev/null
+++ b/arch/arm/mach-spear3xx/Makefile
@@ -0,0 +1,26 @@
+#
+# Makefile for SPEAr3XX machine series
+#
+
+# common files
+obj-y += spear3xx.o clock.o
+
+# spear300 specific files
+obj-$(CONFIG_MACH_SPEAR300) += spear300.o
+
+# spear300 boards files
+obj-$(CONFIG_BOARD_SPEAR300_EVB) += spear300_evb.o
+
+
+# spear310 specific files
+obj-$(CONFIG_MACH_SPEAR310) += spear310.o
+
+# spear310 boards files
+obj-$(CONFIG_BOARD_SPEAR310_EVB) += spear310_evb.o
+
+
+# spear320 specific files
+obj-$(CONFIG_MACH_SPEAR320) += spear320.o
+
+# spear320 boards files
+obj-$(CONFIG_BOARD_SPEAR320_EVB) += spear320_evb.o
diff --git a/arch/arm/mach-spear3xx/Makefile.boot b/arch/arm/mach-spear3xx/Makefile.boot
new file mode 100644
index 0000000..7a1f3c0
--- /dev/null
+++ b/arch/arm/mach-spear3xx/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
new file mode 100644
index 0000000..63aca8f
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -0,0 +1,45 @@
+/*
+ * arch/arm/mach-spear3xx/spear300.c
+ *
+ * SPEAr300 machine source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/amba/pl061.h>
+#include <linux/ptrace.h>
+#include <asm/irq.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Add spear300 specific devices here */
+/* arm gpio1 device registeration */
+static struct pl061_platform_data gpio1_plat_data = {
+ .gpio_base = 8,
+ .irq_base = SPEAR_GPIO1_INT_BASE,
+};
+
+struct amba_device gpio1_device = {
+ .dev = {
+ .init_name = "gpio1",
+ .platform_data = &gpio1_plat_data,
+ },
+ .res = {
+ .start = SPEAR300_GPIO_BASE,
+ .end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_GEN_RAS_1, NO_IRQ},
+};
+
+void __init spear300_init(void)
+{
+ /* call spear3xx family common init function */
+ spear3xx_init();
+}
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
new file mode 100644
index 0000000..1272a38
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -0,0 +1,55 @@
+/*
+ * arch/arm/mach-spear3xx/spear300_evb.c
+ *
+ * SPEAr300 evaluation board source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ /* spear3xx specific devices */
+ &gpio_device,
+ &uart_device,
+
+ /* spear300 specific devices */
+ &gpio1_device,
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+ /* spear3xx specific devices */
+
+ /* spear300 specific devices */
+};
+
+static void __init spear300_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear300 machine init function */
+ spear300_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear3xx_map_io,
+ .init_irq = spear3xx_init_irq,
+ .timer = &spear_sys_timer,
+ .init_machine = spear300_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
new file mode 100644
index 0000000..6eb62f9
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear3xx/spear310.c
+ *
+ * SPEAr310 machine source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/ptrace.h>
+#include <asm/irq.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Add spear310 specific devices here */
+
+void __init spear310_init(void)
+{
+ /* call spear3xx family common init function */
+ spear3xx_init();
+}
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
new file mode 100644
index 0000000..e781b2b
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-spear3xx/spear310_evb.c
+ *
+ * SPEAr310 evaluation board source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ /* spear3xx specific devices */
+ &gpio_device,
+ &uart_device,
+
+ /* spear310 specific devices */
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+ /* spear3xx specific devices */
+
+ /* spear310 specific devices */
+};
+
+static void __init spear310_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear310 machine init function */
+ spear310_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear3xx_map_io,
+ .init_irq = spear3xx_init_irq,
+ .timer = &spear_sys_timer,
+ .init_machine = spear310_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
new file mode 100644
index 0000000..72d4548
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear3xx/spear320.c
+ *
+ * SPEAr320 machine source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/ptrace.h>
+#include <asm/irq.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Add spear320 specific devices here */
+
+void __init spear320_init(void)
+{
+ /* call spear3xx family common init function */
+ spear3xx_init();
+}
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
new file mode 100644
index 0000000..85bc4d2
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-spear3xx/spear320_evb.c
+ *
+ * SPEAr320 evaluation board source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ /* spear3xx specific devices */
+ &gpio_device,
+ &uart_device,
+
+ /* spear320 specific devices */
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+ /* spear3xx specific devices */
+
+ /* spear320 specific devices */
+};
+
+static void __init spear320_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear320 machine init function */
+ spear320_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear3xx_map_io,
+ .init_irq = spear3xx_init_irq,
+ .timer = &spear_sys_timer,
+ .init_machine = spear320_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
new file mode 100644
index 0000000..82ebcd3
--- /dev/null
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mach-spear3xx/spear3xx.c
+ *
+ * SPEAr3XX machines common source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/amba/pl061.h>
+#include <linux/ptrace.h>
+#include <linux/io.h>
+#include <asm/hardware/vic.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Add spear3xx machines common devices here */
+/* gpio device registeration */
+static struct pl061_platform_data gpio_plat_data = {
+ .gpio_base = 0,
+ .irq_base = SPEAR_GPIO_INT_BASE,
+};
+
+struct amba_device gpio_device = {
+ .dev = {
+ .init_name = "gpio",
+ .platform_data = &gpio_plat_data,
+ },
+ .res = {
+ .start = SPEAR3XX_ICM3_GPIO_BASE,
+ .end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_BASIC_GPIO, NO_IRQ},
+};
+
+/* uart device registeration */
+struct amba_device uart_device = {
+ .dev = {
+ .init_name = "uart",
+ },
+ .res = {
+ .start = SPEAR3XX_ICM1_UART_BASE,
+ .end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART, NO_IRQ},
+};
+
+/* Do spear3xx familiy common initialization part here */
+void __init spear3xx_init(void)
+{
+ /* nothing to do for now */
+}
+
+/* This will initialize vic */
+void __init spear3xx_init_irq(void)
+{
+ vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
+}
+
+/* Following will create static virtual/physical mappings */
+struct map_desc spear3xx_io_desc[] __initdata = {
+ {
+ .virtual = VA_SPEAR3XX_ICM1_UART_BASE,
+ .pfn = __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
+ .length = SPEAR3XX_ICM1_UART_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR3XX_ML1_VIC_BASE,
+ .pfn = __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
+ .length = SPEAR3XX_ML1_VIC_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
+ .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
+ .length = SPEAR3XX_ICM3_SYS_CTRL_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR3XX_ICM3_MISC_REG_BASE,
+ .pfn = __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
+ .length = SPEAR3XX_ICM3_MISC_REG_SIZE,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear3xx_map_io(void)
+{
+ iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
+
+ /* This will initialize clock framework */
+ clk_init();
+}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 08/12] ST SPEAr: Added source files for SPEAr6xx machine family
2010-03-25 8:40 ` [PATCH V2 Resend 07/12] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 09/12] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear6xx/Kconfig | 20 ++++
arch/arm/mach-spear6xx/Kconfig600 | 17 ++++
arch/arm/mach-spear6xx/Makefile | 12 +++
arch/arm/mach-spear6xx/Makefile.boot | 3 +
arch/arm/mach-spear6xx/spear600.c | 25 +++++
arch/arm/mach-spear6xx/spear600_evb.c | 51 +++++++++++
arch/arm/mach-spear6xx/spear6xx.c | 158 +++++++++++++++++++++++++++++++++
7 files changed, 286 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-spear6xx/Kconfig
create mode 100644 arch/arm/mach-spear6xx/Kconfig600
create mode 100644 arch/arm/mach-spear6xx/Makefile
create mode 100644 arch/arm/mach-spear6xx/Makefile.boot
create mode 100644 arch/arm/mach-spear6xx/spear600.c
create mode 100644 arch/arm/mach-spear6xx/spear600_evb.c
create mode 100644 arch/arm/mach-spear6xx/spear6xx.c
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
new file mode 100644
index 0000000..bddba03
--- /dev/null
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -0,0 +1,20 @@
+#
+# SPEAr6XX Machine configuration file
+#
+
+if ARCH_SPEAR6XX
+
+choice
+ prompt "SPEAr6XX Family"
+ default MACH_SPEAR600
+
+config MACH_SPEAR600
+ bool "SPEAr600"
+ help
+ Supports ST SPEAr600 Machine
+endchoice
+
+# Adding SPEAr6XX machine specific configuration files
+source "arch/arm/mach-spear6xx/Kconfig600"
+
+endif #ARCH_SPEAR6XX
diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600
new file mode 100644
index 0000000..9e19f65
--- /dev/null
+++ b/arch/arm/mach-spear6xx/Kconfig600
@@ -0,0 +1,17 @@
+#
+# SPEAr600 machine configuration file
+#
+
+if MACH_SPEAR600
+
+choice
+ prompt "SPEAr600 Boards"
+ default BOARD_SPEAR600_EVB
+
+config BOARD_SPEAR600_EVB
+ bool "SPEAr600 Evaluation Board"
+ help
+ Supports ST SPEAr600 Evaluation Board
+endchoice
+
+endif #MACH_SPEAR600
diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
new file mode 100644
index 0000000..cc1a4d8
--- /dev/null
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -0,0 +1,12 @@
+#
+# Makefile for SPEAr6XX machine series
+#
+
+# common files
+obj-y += clock.o spear6xx.o
+
+# spear600 specific files
+obj-$(CONFIG_MACH_SPEAR600) += spear600.o
+
+# spear600 boards files
+obj-$(CONFIG_BOARD_SPEAR600_EVB) += spear600_evb.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
new file mode 100644
index 0000000..7a1f3c0
--- /dev/null
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-spear6xx/spear600.c b/arch/arm/mach-spear6xx/spear600.c
new file mode 100644
index 0000000..5c484c4
--- /dev/null
+++ b/arch/arm/mach-spear6xx/spear600.c
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-spear6xx/spear600.c
+ *
+ * SPEAr600 machine source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/ptrace.h>
+#include <asm/irq.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Add spear600 specific devices here */
+
+void __init spear600_init(void)
+{
+ /* call spear6xx family common init function */
+ spear6xx_init();
+}
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
new file mode 100644
index 0000000..daff8d0
--- /dev/null
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -0,0 +1,51 @@
+/*
+ * arch/arm/mach-spear6xx/spear600_evb.c
+ *
+ * SPEAr600 evaluation board source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+static struct amba_device *amba_devs[] __initdata = {
+ &gpio_device[0],
+ &gpio_device[1],
+ &gpio_device[2],
+ &uart_device[0],
+ &uart_device[1],
+};
+
+static struct platform_device *plat_devs[] __initdata = {
+};
+
+static void __init spear600_evb_init(void)
+{
+ unsigned int i;
+
+ /* call spear600 machine init function */
+ spear600_init();
+
+ /* Add Platform Devices */
+ platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
+
+ /* Add Amba Devices */
+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+ amba_device_register(amba_devs[i], &iomem_resource);
+}
+
+MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
+ .boot_params = 0x00000100,
+ .map_io = spear6xx_map_io,
+ .init_irq = spear6xx_init_irq,
+ .timer = &spear_sys_timer,
+ .init_machine = spear600_evb_init,
+MACHINE_END
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
new file mode 100644
index 0000000..b67e571
--- /dev/null
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -0,0 +1,158 @@
+/*
+ * arch/arm/mach-spear6xx/spear6xx.c
+ *
+ * SPEAr6XX machines common source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Rajeev Kumar<rajeev-dlh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/types.h>
+#include <linux/amba/pl061.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/io.h>
+#include <asm/hardware/vic.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <mach/irqs.h>
+#include <mach/generic.h>
+#include <mach/spear.h>
+
+/* Add spear6xx machines common devices here */
+/* uart device registeration */
+struct amba_device uart_device[] = {
+ {
+ .dev = {
+ .init_name = "uart0",
+ },
+ .res = {
+ .start = SPEAR6XX_ICM1_UART0_BASE,
+ .end = SPEAR6XX_ICM1_UART0_BASE +
+ SPEAR6XX_ICM1_UART0_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART_0, NO_IRQ},
+ }, {
+ .dev = {
+ .init_name = "uart1",
+ },
+ .res = {
+ .start = SPEAR6XX_ICM1_UART1_BASE,
+ .end = SPEAR6XX_ICM1_UART1_BASE +
+ SPEAR6XX_ICM1_UART1_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_UART_1, NO_IRQ},
+ }
+};
+
+/* gpio device registeration */
+static struct pl061_platform_data gpio_plat_data[] = {
+ {
+ .gpio_base = 0,
+ .irq_base = SPEAR_GPIO0_INT_BASE,
+ }, {
+ .gpio_base = 8,
+ .irq_base = SPEAR_GPIO1_INT_BASE,
+ }, {
+ .gpio_base = 16,
+ .irq_base = SPEAR_GPIO2_INT_BASE,
+ },
+};
+
+struct amba_device gpio_device[] = {
+ {
+ .dev = {
+ .init_name = "gpio0",
+ .platform_data = &gpio_plat_data[0],
+ },
+ .res = {
+ .start = SPEAR6XX_CPU_GPIO_BASE,
+ .end = SPEAR6XX_CPU_GPIO_BASE +
+ SPEAR6XX_CPU_GPIO_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_LOCAL_GPIO, NO_IRQ},
+ }, {
+ .dev = {
+ .init_name = "gpio1",
+ .platform_data = &gpio_plat_data[1],
+ },
+ .res = {
+ .start = SPEAR6XX_ICM3_GPIO_BASE,
+ .end = SPEAR6XX_ICM3_GPIO_BASE +
+ SPEAR6XX_ICM3_GPIO_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_BASIC_GPIO, NO_IRQ},
+ }, {
+ .dev = {
+ .init_name = "gpio2",
+ .platform_data = &gpio_plat_data[2],
+ },
+ .res = {
+ .start = SPEAR6XX_ICM2_GPIO_BASE,
+ .end = SPEAR6XX_ICM2_GPIO_BASE +
+ SPEAR6XX_ICM2_GPIO_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ .irq = {IRQ_APPL_GPIO, NO_IRQ},
+ }
+};
+
+/* This will add devices, and do machine specific tasks */
+void __init spear6xx_init(void)
+{
+ /* nothing to do for now */
+}
+
+/* This will initialize vic */
+void __init spear6xx_init_irq(void)
+{
+ vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0);
+ vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0);
+}
+
+/* Following will create static virtual/physical mappings */
+static struct map_desc spear6xx_io_desc[] __initdata = {
+ {
+ .virtual = VA_SPEAR6XX_ICM1_UART0_BASE,
+ .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
+ .length = SPEAR6XX_ICM1_UART0_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
+ .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
+ .length = SPEAR6XX_CPU_VIC_PRI_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE,
+ .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
+ .length = SPEAR6XX_CPU_VIC_SEC_SIZE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
+ .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
+ .length = SPEAR6XX_ICM3_MISC_REG_BASE,
+ .type = MT_DEVICE
+ }, {
+ .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE,
+ .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
+ .length = SPEAR6XX_ICM3_MISC_REG_SIZE,
+ .type = MT_DEVICE
+ },
+};
+
+/* This will create static memory mapping for selected devices */
+void __init spear6xx_map_io(void)
+{
+ iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
+
+ /* This will initialize clock framework */
+ clk_init();
+}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 09/12] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/
2010-03-25 8:40 ` [PATCH V2 Resend 08/12] ST SPEAr: Added source files for SPEAr6xx " Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 10/12] ST SPEAr: Added default configuration files for SPEAr machines Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/Kconfig | 13 +++++++++++++
arch/arm/Makefile | 5 +++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5408bf..1459231 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -801,6 +801,18 @@ config ARCH_OMAP
help
Support for TI's OMAP platform (OMAP1 and OMAP2).
+config PLAT_SPEAR
+ bool "ST SPEAr"
+ select ARM_AMBA
+ select ARCH_REQUIRE_GPIOLIB
+ select COMMON_CLKDEV
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_GPIO
+ select GENERIC_TIME
+ select HAVE_CLK
+ help
+ Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
+
endchoice
#
@@ -886,6 +898,7 @@ source "arch/arm/plat-samsung/Kconfig"
source "arch/arm/plat-s3c24xx/Kconfig"
source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-s5pc1xx/Kconfig"
+source "arch/arm/plat-spear/Kconfig"
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ed820e7..b3a3518 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -178,6 +178,10 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile
machine-$(CONFIG_ARCH_W90X900) := w90x900
machine-$(CONFIG_ARCH_NUC93X) := nuc93x
machine-$(CONFIG_FOOTBRIDGE) := footbridge
+machine-$(CONFIG_MACH_SPEAR300) := spear3xx
+machine-$(CONFIG_MACH_SPEAR310) := spear3xx
+machine-$(CONFIG_MACH_SPEAR320) := spear3xx
+machine-$(CONFIG_MACH_SPEAR600) := spear6xx
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
@@ -192,6 +196,7 @@ plat-$(CONFIG_PLAT_PXA) := pxa
plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx samsung
plat-$(CONFIG_PLAT_S5P) := s5p samsung
+plat-$(CONFIG_PLAT_SPEAR) := spear
ifeq ($(CONFIG_ARCH_EBSA110),y)
# This is what happens if you forget the IOCS16 line.
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 10/12] ST SPEAr: Added default configuration files for SPEAr machines
2010-03-25 8:40 ` [PATCH V2 Resend 09/12] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 11/12] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/configs/spear300_defconfig | 773 ++++++++++++++++++++++++++++++++++
arch/arm/configs/spear310_defconfig | 775 +++++++++++++++++++++++++++++++++++
arch/arm/configs/spear320_defconfig | 775 +++++++++++++++++++++++++++++++++++
arch/arm/configs/spear600_defconfig | 760 ++++++++++++++++++++++++++++++++++
4 files changed, 3083 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/configs/spear300_defconfig
create mode 100644 arch/arm/configs/spear310_defconfig
create mode 100644 arch/arm/configs/spear320_defconfig
create mode 100644 arch/arm/configs/spear600_defconfig
diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear300_defconfig
new file mode 100644
index 0000000..35e64d1
--- /dev/null
+++ b/arch/arm/configs/spear300_defconfig
@@ -0,0 +1,773 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32
+# Tue Mar 23 14:36:23 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR3XX=y
+# CONFIG_ARCH_SPEAR6XX is not set
+CONFIG_MACH_SPEAR300=y
+# CONFIG_MACH_SPEAR310 is not set
+# CONFIG_MACH_SPEAR320 is not set
+CONFIG_BOARD_SPEAR300_EVB=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+CONFIG_GPIO_PL061=y
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig
new file mode 100644
index 0000000..cbbfd29
--- /dev/null
+++ b/arch/arm/configs/spear310_defconfig
@@ -0,0 +1,775 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32
+# Tue Mar 23 14:37:01 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR3XX=y
+# CONFIG_ARCH_SPEAR6XX is not set
+# CONFIG_MACH_SPEAR300 is not set
+CONFIG_MACH_SPEAR310=y
+# CONFIG_MACH_SPEAR320 is not set
+# CONFIG_BOARD_SPEAR300_EVB is not set
+CONFIG_BOARD_SPEAR310_EVB=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+CONFIG_GPIO_PL061=y
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig
new file mode 100644
index 0000000..2ae3c11
--- /dev/null
+++ b/arch/arm/configs/spear320_defconfig
@@ -0,0 +1,775 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32
+# Tue Mar 23 14:37:12 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR3XX=y
+# CONFIG_ARCH_SPEAR6XX is not set
+# CONFIG_MACH_SPEAR300 is not set
+# CONFIG_MACH_SPEAR310 is not set
+CONFIG_MACH_SPEAR320=y
+# CONFIG_BOARD_SPEAR300_EVB is not set
+CONFIG_BOARD_SPEAR320_EVB=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+CONFIG_GPIO_PL061=y
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear600_defconfig
new file mode 100644
index 0000000..c85a029
--- /dev/null
+++ b/arch/arm/configs/spear600_defconfig
@@ -0,0 +1,760 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32
+# Tue Mar 23 14:37:26 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_PLAT_SPEAR=y
+# CONFIG_ARCH_SPEAR3XX is not set
+CONFIG_ARCH_SPEAR6XX=y
+# CONFIG_MACH_SPEAR300 is not set
+# CONFIG_MACH_SPEAR310 is not set
+# CONFIG_MACH_SPEAR320 is not set
+# CONFIG_BOARD_SPEAR300_EVB is not set
+CONFIG_MACH_SPEAR600=y
+CONFIG_BOARD_SPEAR600_EVB=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_R3964 is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+CONFIG_GPIO_PL061=y
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 11/12] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr
2010-03-25 8:40 ` [PATCH V2 Resend 10/12] ST SPEAr: Added default configuration files for SPEAr machines Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 12/12] ST SPEAr: Adding gpio pad multiplexing support Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
Documentation/arm/00-INDEX | 2 +
Documentation/arm/SPEAr/overview.txt | 60 ++++++++++++++++++++++++++++++++++
MAINTAINERS | 40 ++++++++++++++++++++++
3 files changed, 102 insertions(+), 0 deletions(-)
create mode 100644 Documentation/arm/SPEAr/overview.txt
diff --git a/Documentation/arm/00-INDEX b/Documentation/arm/00-INDEX
index 82e418d..7f5fc3b 100644
--- a/Documentation/arm/00-INDEX
+++ b/Documentation/arm/00-INDEX
@@ -20,6 +20,8 @@ Samsung-S3C24XX
- S3C24XX ARM Linux Overview
Sharp-LH
- Linux on Sharp LH79524 and LH7A40X System On a Chip (SOC)
+SPEAr
+ - ST SPEAr platform Linux Overview
VFP/
- Release notes for Linux Kernel Vector Floating Point support code
empeg/
diff --git a/Documentation/arm/SPEAr/overview.txt b/Documentation/arm/SPEAr/overview.txt
new file mode 100644
index 0000000..253a35c
--- /dev/null
+++ b/Documentation/arm/SPEAr/overview.txt
@@ -0,0 +1,60 @@
+ SPEAr ARM Linux Overview
+ ==========================
+
+Introduction
+------------
+
+ SPEAr (Structured Processor Enhanced Architecture).
+ weblink : http://www.st.com/spear
+
+ The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
+ supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
+ SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
+ series is in progress.
+
+ Hierarchy in SPEAr is as follows:
+
+ SPEAr (Platform)
+ - SPEAr3XX (3XX SOC series, based on ARM9)
+ - SPEAr300 (SOC)
+ - SPEAr300_EVB (Evaluation Board)
+ - SPEAr310 (SOC)
+ - SPEAr310_EVB (Evaluation Board)
+ - SPEAr320 (SOC)
+ - SPEAr320_EVB (Evaluation Board)
+ - SPEAr6XX (6XX SOC series, based on ARM9)
+ - SPEAr600 (SOC)
+ - SPEAr600_EVB (Evaluation Board)
+ - SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
+ - SPEAr1300 (SOC)
+
+ Configuration
+ -------------
+
+ A generic configuration is provided for each machine, and can be used as the
+ default by
+ make spear600_defconfig
+ make spear300_defconfig
+ make spear310_defconfig
+ make spear320_defconfig
+
+ Layout
+ ------
+
+ The common files for multiple machine families (SPEAr3XX, SPEAr6XX and
+ SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear
+ with headers in plat/.
+
+ Each machine series have a directory with name arch/arm/mach-spear followed by
+ series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
+
+ Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
+ spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
+ specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
+ mach-spear* also contains board specific files for each machine type.
+
+
+ Document Author
+ ---------------
+
+ Viresh Kumar, (c) 2010 ST Microelectronics
diff --git a/MAINTAINERS b/MAINTAINERS
index 449d444..dc6b246 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5238,6 +5238,46 @@ F: drivers/serial/sunsu.c
F: drivers/serial/sunzilog.c
F: drivers/serial/sunzilog.h
+SPEAR PLATFORM SUPPORT
+M: Viresh Kumar <viresh.kumar@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/plat-spear/
+
+SPEAR3XX MACHINE SUPPORT
+M: Viresh Kumar <viresh.kumar@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/mach-spear3xx/
+
+SPEAR6XX MACHINE SUPPORT
+M: Rajeev Kumar <rajeev-dlh.kumar@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/mach-spear6xx/
+
+SPEAR CLOCK FRAMEWORK SUPPORT
+M: Viresh Kumar <viresh.kumar@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/mach-spear*/clock.c
+F: arch/arm/mach-spear*/include/mach/clkdev.h
+F: arch/arm/plat-spear/clock.c
+F: arch/arm/plat-spear/include/plat/clock.h and clkdev.h
+
+SPEAR PAD MULTIPLEXING SUPPORT
+M: Viresh Kumar <viresh.kumar@st.com>
+W: http://www.st.com/spear
+S: Maintained
+F: arch/arm/plat-spear/include/plat/padmux.h
+F: arch/arm/plat-spear/padmux.c
+F: arch/arm/mach-spear*/spear*xx.c
+F: arch/arm/mach-spear*/include/mach/generic.h
+F: arch/arm/mach-spear3xx/spear3*0.c
+F: arch/arm/mach-spear3xx/spear3*0_evb.c
+F: arch/arm/mach-spear6xx/spear600.c
+F: arch/arm/mach-spear6xx/spear600_evb.c
+
SPECIALIX IO8+ MULTIPORT SERIAL CARD DRIVER
M: Roger Wolff <R.E.Wolff@BitWizard.nl>
S: Supported
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 12/12] ST SPEAr: Adding gpio pad multiplexing support
2010-03-25 8:40 ` [PATCH V2 Resend 11/12] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr Viresh KUMAR
@ 2010-03-25 8:40 ` Viresh KUMAR
2010-04-03 17:14 ` Shiraz HASHIM
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-03-25 8:40 UTC (permalink / raw)
To: linux-arm-kernel
GPIO Pads in spear platform are are multiplexed in various machines.
This patch adds support for this pad multiplexing.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
---
arch/arm/mach-spear3xx/include/mach/generic.h | 161 +++++++++-
arch/arm/mach-spear3xx/spear300.c | 358 ++++++++++++++++++++
arch/arm/mach-spear3xx/spear300_evb.c | 22 ++
arch/arm/mach-spear3xx/spear310.c | 129 +++++++
arch/arm/mach-spear3xx/spear310_evb.c | 30 ++
arch/arm/mach-spear3xx/spear320.c | 374 +++++++++++++++++++++
arch/arm/mach-spear3xx/spear320_evb.c | 27 ++
arch/arm/mach-spear3xx/spear3xx.c | 447 +++++++++++++++++++++++++
arch/arm/plat-spear/Makefile | 2 +-
arch/arm/plat-spear/include/plat/padmux.h | 92 +++++
arch/arm/plat-spear/padmux.c | 164 +++++++++
11 files changed, 1798 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/plat-spear/include/plat/padmux.h
create mode 100644 arch/arm/plat-spear/padmux.c
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index aeea845..af7e02c 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -19,7 +19,9 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
+#include <plat/padmux.h>
+/* spear3xx declarations */
/*
* Each GPT has 2 timer channels
* Following GPT channels will be used as clock source and clockevent
@@ -34,25 +36,170 @@ extern struct amba_device uart_device;
extern struct sys_timer spear_sys_timer;
/* Add spear3xx family function declarations here */
+void __init clk_init(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
void __init spear3xx_init(void);
-void __init spear300_init(void);
-void __init spear310_init(void);
-void __init spear320_init(void);
-void __init clk_init(void);
+void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
-/* Add spear300 machine device structure declarations here */
+/* pad mux declarations */
+#define PMX_FIRDA_MASK (1 << 14)
+#define PMX_I2C_MASK (1 << 13)
+#define PMX_SSP_CS_MASK (1 << 12)
+#define PMX_SSP_MASK (1 << 11)
+#define PMX_MII_MASK (1 << 10)
+#define PMX_GPIO_PIN0_MASK (1 << 9)
+#define PMX_GPIO_PIN1_MASK (1 << 8)
+#define PMX_GPIO_PIN2_MASK (1 << 7)
+#define PMX_GPIO_PIN3_MASK (1 << 6)
+#define PMX_GPIO_PIN4_MASK (1 << 5)
+#define PMX_GPIO_PIN5_MASK (1 << 4)
+#define PMX_UART0_MODEM_MASK (1 << 3)
+#define PMX_UART0_MASK (1 << 2)
+#define PMX_TIMER_3_4_MASK (1 << 1)
+#define PMX_TIMER_1_2_MASK (1 << 0)
+
+/* pad mux devices */
+extern struct pmx_dev pmx_firda;
+extern struct pmx_dev pmx_i2c;
+extern struct pmx_dev pmx_ssp_cs;
+extern struct pmx_dev pmx_ssp;
+extern struct pmx_dev pmx_mii;
+extern struct pmx_dev pmx_gpio_pin0;
+extern struct pmx_dev pmx_gpio_pin1;
+extern struct pmx_dev pmx_gpio_pin2;
+extern struct pmx_dev pmx_gpio_pin3;
+extern struct pmx_dev pmx_gpio_pin4;
+extern struct pmx_dev pmx_gpio_pin5;
+extern struct pmx_dev pmx_uart0_modem;
+extern struct pmx_dev pmx_uart0;
+extern struct pmx_dev pmx_timer_3_4;
+extern struct pmx_dev pmx_timer_1_2;
+
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* padmux plgpio devices */
+extern struct pmx_dev pmx_plgpio_0_1;
+extern struct pmx_dev pmx_plgpio_2_3;
+extern struct pmx_dev pmx_plgpio_4_5;
+extern struct pmx_dev pmx_plgpio_6_9;
+extern struct pmx_dev pmx_plgpio_10_27;
+extern struct pmx_dev pmx_plgpio_28;
+extern struct pmx_dev pmx_plgpio_29;
+extern struct pmx_dev pmx_plgpio_30;
+extern struct pmx_dev pmx_plgpio_31;
+extern struct pmx_dev pmx_plgpio_32;
+extern struct pmx_dev pmx_plgpio_33;
+extern struct pmx_dev pmx_plgpio_34_36;
+extern struct pmx_dev pmx_plgpio_37_42;
+extern struct pmx_dev pmx_plgpio_43_44_47_48;
+extern struct pmx_dev pmx_plgpio_45_46_49_50;
+#endif
+
+extern struct pmx_driver pmx_driver;
+
+/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
+/* Add spear300 machine device structure declarations here */
extern struct amba_device gpio1_device;
+
+/* pad mux modes */
+extern struct pmx_mode nand_mode;
+extern struct pmx_mode nor_mode;
+extern struct pmx_mode photo_frame_mode;
+extern struct pmx_mode lend_ip_phone_mode;
+extern struct pmx_mode hend_ip_phone_mode;
+extern struct pmx_mode lend_wifi_phone_mode;
+extern struct pmx_mode hend_wifi_phone_mode;
+extern struct pmx_mode ata_pabx_wi2s_mode;
+extern struct pmx_mode ata_pabx_i2s_mode;
+extern struct pmx_mode caml_lcdw_mode;
+extern struct pmx_mode camu_lcd_mode;
+extern struct pmx_mode camu_wlcd_mode;
+extern struct pmx_mode caml_lcd_mode;
+
+/* pad mux devices */
+extern struct pmx_dev pmx_fsmc_2_chips;
+extern struct pmx_dev pmx_fsmc_4_chips;
+extern struct pmx_dev pmx_keyboard;
+extern struct pmx_dev pmx_clcd;
+extern struct pmx_dev pmx_telecom_gpio;
+extern struct pmx_dev pmx_telecom_tdm;
+extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk;
+extern struct pmx_dev pmx_telecom_camera;
+extern struct pmx_dev pmx_telecom_dac;
+extern struct pmx_dev pmx_telecom_i2s;
+extern struct pmx_dev pmx_telecom_boot_pins;
+extern struct pmx_dev pmx_telecom_sdio_4bit;
+extern struct pmx_dev pmx_telecom_sdio_8bit;
+extern struct pmx_dev pmx_gpio1;
+
+void spear300_pmx_init(void);
+
+/* Add spear300 machine function declarations here */
+void __init spear300_init(void);
+
#endif /* CONFIG_MACH_SPEAR300 */
-/* Add spear310 machine device structure declarations here */
+/* spear310 declarations */
#ifdef CONFIG_MACH_SPEAR310
+/* Add spear310 machine device structure declarations here */
+
+/* pad mux devices */
+extern struct pmx_dev pmx_emi_cs_0_1_4_5;
+extern struct pmx_dev pmx_emi_cs_2_3;
+extern struct pmx_dev pmx_uart1;
+extern struct pmx_dev pmx_uart2;
+extern struct pmx_dev pmx_uart3_4_5;
+extern struct pmx_dev pmx_fsmc;
+extern struct pmx_dev pmx_rs485_0_1;
+extern struct pmx_dev pmx_tdm0;
+
+void spear310_pmx_init(void);
+
+/* Add spear310 machine function declarations here */
+void __init spear310_init(void);
+
#endif /* CONFIG_MACH_SPEAR310 */
-/* Add spear320 machine device structure declarations here */
+/* spear320 declarations */
#ifdef CONFIG_MACH_SPEAR320
+/* Add spear320 machine device structure declarations here */
+
+/* pad mux modes */
+extern struct pmx_mode auto_net_smii_mode;
+extern struct pmx_mode auto_net_mii_mode;
+extern struct pmx_mode auto_exp_mode;
+extern struct pmx_mode small_printers_mode;
+
+/* pad mux devices */
+extern struct pmx_dev pmx_clcd;
+extern struct pmx_dev pmx_emi;
+extern struct pmx_dev pmx_fsmc;
+extern struct pmx_dev pmx_spp;
+extern struct pmx_dev pmx_sdio;
+extern struct pmx_dev pmx_i2s;
+extern struct pmx_dev pmx_uart1;
+extern struct pmx_dev pmx_uart1_modem;
+extern struct pmx_dev pmx_uart2;
+extern struct pmx_dev pmx_touchscreen;
+extern struct pmx_dev pmx_can;
+extern struct pmx_dev pmx_sdio_led;
+extern struct pmx_dev pmx_pwm0;
+extern struct pmx_dev pmx_pwm1;
+extern struct pmx_dev pmx_pwm2;
+extern struct pmx_dev pmx_pwm3;
+extern struct pmx_dev pmx_ssp1;
+extern struct pmx_dev pmx_ssp2;
+extern struct pmx_dev pmx_mii1;
+extern struct pmx_dev pmx_smii0;
+extern struct pmx_dev pmx_smii1;
+extern struct pmx_dev pmx_i2c1;
+
+void spear320_pmx_init(void);
+
+/* Add spear320 machine function declarations here */
+void __init spear320_init(void);
+
#endif /* CONFIG_MACH_SPEAR320 */
#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 63aca8f..66e7fcd 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -18,6 +18,357 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* pad multiplexing support */
+/* muxing registers */
+#define PAD_MUX_CONFIG_REG 0x00
+#define MODE_CONFIG_REG 0x04
+
+/* modes */
+#define NAND_MODE (1 << 0)
+#define NOR_MODE (1 << 1)
+#define PHOTO_FRAME_MODE (1 << 2)
+#define LEND_IP_PHONE_MODE (1 << 3)
+#define HEND_IP_PHONE_MODE (1 << 4)
+#define LEND_WIFI_PHONE_MODE (1 << 5)
+#define HEND_WIFI_PHONE_MODE (1 << 6)
+#define ATA_PABX_WI2S_MODE (1 << 7)
+#define ATA_PABX_I2S_MODE (1 << 8)
+#define CAML_LCDW_MODE (1 << 9)
+#define CAMU_LCD_MODE (1 << 10)
+#define CAMU_WLCD_MODE (1 << 11)
+#define CAML_LCD_MODE (1 << 12)
+#define ALL_MODES 0x1FFF
+
+struct pmx_mode nand_mode = {
+ .id = NAND_MODE,
+ .name = "nand mode",
+ .mask = 0x00,
+};
+
+struct pmx_mode nor_mode = {
+ .id = NOR_MODE,
+ .name = "nor mode",
+ .mask = 0x01,
+};
+
+struct pmx_mode photo_frame_mode = {
+ .id = PHOTO_FRAME_MODE,
+ .name = "photo frame mode",
+ .mask = 0x02,
+};
+
+struct pmx_mode lend_ip_phone_mode = {
+ .id = LEND_IP_PHONE_MODE,
+ .name = "lend ip phone mode",
+ .mask = 0x03,
+};
+
+struct pmx_mode hend_ip_phone_mode = {
+ .id = HEND_IP_PHONE_MODE,
+ .name = "hend ip phone mode",
+ .mask = 0x04,
+};
+
+struct pmx_mode lend_wifi_phone_mode = {
+ .id = LEND_WIFI_PHONE_MODE,
+ .name = "lend wifi phone mode",
+ .mask = 0x05,
+};
+
+struct pmx_mode hend_wifi_phone_mode = {
+ .id = HEND_WIFI_PHONE_MODE,
+ .name = "hend wifi phone mode",
+ .mask = 0x06,
+};
+
+struct pmx_mode ata_pabx_wi2s_mode = {
+ .id = ATA_PABX_WI2S_MODE,
+ .name = "ata pabx wi2s mode",
+ .mask = 0x07,
+};
+
+struct pmx_mode ata_pabx_i2s_mode = {
+ .id = ATA_PABX_I2S_MODE,
+ .name = "ata pabx i2s mode",
+ .mask = 0x08,
+};
+
+struct pmx_mode caml_lcdw_mode = {
+ .id = CAML_LCDW_MODE,
+ .name = "caml lcdw mode",
+ .mask = 0x0C,
+};
+
+struct pmx_mode camu_lcd_mode = {
+ .id = CAMU_LCD_MODE,
+ .name = "camu lcd mode",
+ .mask = 0x0D,
+};
+
+struct pmx_mode camu_wlcd_mode = {
+ .id = CAMU_WLCD_MODE,
+ .name = "camu wlcd mode",
+ .mask = 0x0E,
+};
+
+struct pmx_mode caml_lcd_mode = {
+ .id = CAML_LCD_MODE,
+ .name = "caml lcd mode",
+ .mask = 0x0F,
+};
+
+/* devices */
+struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
+ {
+ .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+ ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+ .mask = PMX_FIRDA_MASK,
+ },
+};
+
+struct pmx_dev pmx_fsmc_2_chips = {
+ .name = "fsmc_2_chips",
+ .modes = pmx_fsmc_2_chips_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
+ {
+ .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
+ ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
+ .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
+ },
+};
+
+struct pmx_dev pmx_fsmc_4_chips = {
+ .name = "fsmc_4_chips",
+ .modes = pmx_fsmc_4_chips_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_keyboard_modes[] = {
+ {
+ .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
+ LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+ CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
+ CAML_LCD_MODE,
+ .mask = 0x0,
+ },
+};
+
+struct pmx_dev pmx_keyboard = {
+ .name = "keyboard",
+ .modes = pmx_keyboard_modes,
+ .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_clcd_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
+ }, {
+ .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+ CAMU_LCD_MODE | CAML_LCD_MODE,
+ .mask = PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_clcd = {
+ .name = "clcd",
+ .modes = pmx_clcd_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
+ .mask = PMX_MII_MASK,
+ }, {
+ .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
+ .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ }, {
+ .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
+ .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
+ }, {
+ .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
+ .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
+ }, {
+ .ids = ATA_PABX_WI2S_MODE,
+ .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
+ | PMX_UART0_MODEM_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_gpio = {
+ .name = "telecom_gpio",
+ .modes = pmx_telecom_gpio_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+ HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
+ | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
+ | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+ | CAMU_WLCD_MODE | CAML_LCD_MODE,
+ .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_tdm = {
+ .name = "telecom_tdm",
+ .modes = pmx_telecom_tdm_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
+ {
+ .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
+ LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
+ | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
+ CAML_LCDW_MODE | CAML_LCD_MODE,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
+ .name = "telecom_spi_cs_i2c_clk",
+ .modes = pmx_telecom_spi_cs_i2c_clk_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_camera_modes[] = {
+ {
+ .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
+ .mask = PMX_MII_MASK,
+ }, {
+ .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_camera = {
+ .name = "telecom_camera",
+ .modes = pmx_telecom_camera_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_dac_modes[] = {
+ {
+ .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+ | CAMU_WLCD_MODE | CAML_LCD_MODE,
+ .mask = PMX_TIMER_1_2_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_dac = {
+ .name = "telecom_dac",
+ .modes = pmx_telecom_dac_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
+ {
+ .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
+ | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
+ ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
+ | CAMU_WLCD_MODE | CAML_LCD_MODE,
+ .mask = PMX_UART0_MODEM_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_i2s = {
+ .name = "telecom_i2s",
+ .modes = pmx_telecom_i2s_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
+ {
+ .ids = NAND_MODE | NOR_MODE,
+ .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
+ PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_boot_pins = {
+ .name = "telecom_boot_pins",
+ .modes = pmx_telecom_boot_pins_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+ HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+ HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+ CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
+ ATA_PABX_I2S_MODE,
+ .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+ PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+ PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_sdio_4bit = {
+ .name = "telecom_sdio_4bit",
+ .modes = pmx_telecom_sdio_4bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
+ HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
+ HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
+ CAMU_WLCD_MODE | CAML_LCD_MODE,
+ .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
+ PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+ PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_telecom_sdio_8bit = {
+ .name = "telecom_sdio_8bit",
+ .modes = pmx_telecom_sdio_8bit_modes,
+ .mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_gpio1_modes[] = {
+ {
+ .ids = PHOTO_FRAME_MODE,
+ .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
+ PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_gpio1 = {
+ .name = "arm gpio1",
+ .modes = pmx_gpio1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
+ .enb_on_reset = 1,
+};
+
+/* pmx driver structure */
+struct pmx_driver pmx_driver = {
+ .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
+ .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
+};
+
/* Add spear300 specific devices here */
/* arm gpio1 device registeration */
static struct pl061_platform_data gpio1_plat_data = {
@@ -38,8 +389,15 @@ struct amba_device gpio1_device = {
.irq = {IRQ_GEN_RAS_1, NO_IRQ},
};
+/* spear300 routines */
void __init spear300_init(void)
{
/* call spear3xx family common init function */
spear3xx_init();
}
+
+void spear300_pmx_init(void)
+{
+ spear_pmx_init(&pmx_driver, SPEAR300_SOC_CONFIG_BASE,
+ SPEAR300_SOC_CONFIG_SIZE);
+}
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 1272a38..bb21db1 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -16,6 +16,22 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+ /* spear3xx specific devices */
+ &pmx_i2c,
+ &pmx_ssp_cs,
+ &pmx_ssp,
+ &pmx_mii,
+ &pmx_uart0,
+
+ /* spear300 specific devices */
+ &pmx_fsmc_2_chips,
+ &pmx_clcd,
+ &pmx_telecom_sdio_4bit,
+ &pmx_gpio1,
+};
+
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
@@ -38,6 +54,12 @@ static void __init spear300_evb_init(void)
/* call spear300 machine init function */
spear300_init();
+ /* padmux initialization */
+ pmx_driver.mode = &photo_frame_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+ spear300_pmx_init();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 6eb62f9..dd5a572 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -16,10 +16,139 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* pad multiplexing support */
+/* muxing registers */
+#define PAD_MUX_CONFIG_REG 0x08
+
+/* devices */
+struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_emi_cs_0_1_4_5 = {
+ .name = "emi_cs_0_1_4_5",
+ .modes = pmx_emi_cs_0_1_4_5_modes,
+ .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_TIMER_1_2_MASK,
+ },
+};
+
+struct pmx_dev pmx_emi_cs_2_3 = {
+ .name = "emi_cs_2_3",
+ .modes = pmx_emi_cs_2_3_modes,
+ .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_uart1_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_FIRDA_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart1 = {
+ .name = "uart1",
+ .modes = pmx_uart1_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_uart2_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_TIMER_1_2_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart2 = {
+ .name = "uart2",
+ .modes = pmx_uart2_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart2_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_UART0_MODEM_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart3_4_5 = {
+ .name = "uart3_4_5",
+ .modes = pmx_uart3_4_5_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_fsmc_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_SSP_CS_MASK,
+ },
+};
+
+struct pmx_dev pmx_fsmc = {
+ .name = "fsmc",
+ .modes = pmx_fsmc_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_rs485_0_1 = {
+ .name = "rs485_0_1",
+ .modes = pmx_rs485_0_1_modes,
+ .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_tdm0_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_tdm0 = {
+ .name = "tdm0",
+ .modes = pmx_tdm0_modes,
+ .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
+ .enb_on_reset = 1,
+};
+
+/* pmx driver structure */
+struct pmx_driver pmx_driver = {
+ .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
+};
+
/* Add spear310 specific devices here */
+/* spear310 routines */
void __init spear310_init(void)
{
/* call spear3xx family common init function */
spear3xx_init();
}
+
+void spear310_pmx_init(void)
+{
+ spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
+ SPEAR310_SOC_CONFIG_SIZE);
+}
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index e781b2b..7facf66 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -16,6 +16,30 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+ /* spear3xx specific devices */
+ &pmx_i2c,
+ &pmx_ssp,
+ &pmx_gpio_pin0,
+ &pmx_gpio_pin1,
+ &pmx_gpio_pin2,
+ &pmx_gpio_pin3,
+ &pmx_gpio_pin4,
+ &pmx_gpio_pin5,
+ &pmx_uart0,
+
+ /* spear310 specific devices */
+ &pmx_emi_cs_0_1_4_5,
+ &pmx_emi_cs_2_3,
+ &pmx_uart1,
+ &pmx_uart2,
+ &pmx_uart3_4_5,
+ &pmx_fsmc,
+ &pmx_rs485_0_1,
+ &pmx_tdm0,
+};
+
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
@@ -37,6 +61,12 @@ static void __init spear310_evb_init(void)
/* call spear310 machine init function */
spear310_init();
+ /* padmux initialization */
+ pmx_driver.mode = NULL;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+ spear310_pmx_init();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 72d4548..2cedf5e 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -16,10 +16,384 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* pad multiplexing support */
+/* muxing registers */
+#define PAD_MUX_CONFIG_REG 0x0C
+#define MODE_CONFIG_REG 0x10
+
+/* modes */
+#define AUTO_NET_SMII_MODE (1 << 0)
+#define AUTO_NET_MII_MODE (1 << 1)
+#define AUTO_EXP_MODE (1 << 2)
+#define SMALL_PRINTERS_MODE (1 << 3)
+#define ALL_MODES 0xF
+
+struct pmx_mode auto_net_smii_mode = {
+ .id = AUTO_NET_SMII_MODE,
+ .name = "Automation Networking SMII Mode",
+ .mask = 0x00,
+};
+
+struct pmx_mode auto_net_mii_mode = {
+ .id = AUTO_NET_MII_MODE,
+ .name = "Automation Networking MII Mode",
+ .mask = 0x01,
+};
+
+struct pmx_mode auto_exp_mode = {
+ .id = AUTO_EXP_MODE,
+ .name = "Automation Expanded Mode",
+ .mask = 0x02,
+};
+
+struct pmx_mode small_printers_mode = {
+ .id = SMALL_PRINTERS_MODE,
+ .name = "Small Printers Mode",
+ .mask = 0x03,
+};
+
+/* devices */
+struct pmx_dev_mode pmx_clcd_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE,
+ .mask = 0x0,
+ },
+};
+
+struct pmx_dev pmx_clcd = {
+ .name = "clcd",
+ .modes = pmx_clcd_modes,
+ .mode_count = ARRAY_SIZE(pmx_clcd_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_emi_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_emi = {
+ .name = "emi",
+ .modes = pmx_emi_modes,
+ .mode_count = ARRAY_SIZE(pmx_emi_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_fsmc_modes[] = {
+ {
+ .ids = ALL_MODES,
+ .mask = 0x0,
+ },
+};
+
+struct pmx_dev pmx_fsmc = {
+ .name = "fsmc",
+ .modes = pmx_fsmc_modes,
+ .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_spp_modes[] = {
+ {
+ .ids = SMALL_PRINTERS_MODE,
+ .mask = 0x0,
+ },
+};
+
+struct pmx_dev pmx_spp = {
+ .name = "spp",
+ .modes = pmx_spp_modes,
+ .mode_count = ARRAY_SIZE(pmx_spp_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_sdio_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
+ SMALL_PRINTERS_MODE,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_sdio = {
+ .name = "sdio",
+ .modes = pmx_sdio_modes,
+ .mode_count = ARRAY_SIZE(pmx_sdio_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_i2s_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mask = PMX_UART0_MODEM_MASK,
+ },
+};
+
+struct pmx_dev pmx_i2s = {
+ .name = "i2s",
+ .modes = pmx_i2s_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2s_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_uart1_modes[] = {
+ {
+ .ids = ALL_MODES,
+ .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart1 = {
+ .name = "uart1",
+ .modes = pmx_uart1_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_uart1_modem_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE,
+ .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
+ PMX_SSP_CS_MASK,
+ }, {
+ .ids = SMALL_PRINTERS_MODE,
+ .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
+ PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart1_modem = {
+ .name = "uart1_modem",
+ .modes = pmx_uart1_modem_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_uart2_modes[] = {
+ {
+ .ids = ALL_MODES,
+ .mask = PMX_FIRDA_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart2 = {
+ .name = "uart2",
+ .modes = pmx_uart2_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart2_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_touchscreen_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE,
+ .mask = PMX_SSP_CS_MASK,
+ },
+};
+
+struct pmx_dev pmx_touchscreen = {
+ .name = "touchscreen",
+ .modes = pmx_touchscreen_modes,
+ .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_can_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
+ .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
+ PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
+ },
+};
+
+struct pmx_dev pmx_can = {
+ .name = "can",
+ .modes = pmx_can_modes,
+ .mode_count = ARRAY_SIZE(pmx_can_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_sdio_led_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mask = PMX_SSP_CS_MASK,
+ },
+};
+
+struct pmx_dev pmx_sdio_led = {
+ .name = "sdio_led",
+ .modes = pmx_sdio_led_modes,
+ .mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_pwm0_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mask = PMX_UART0_MODEM_MASK,
+ }, {
+ .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_pwm0 = {
+ .name = "pwm0",
+ .modes = pmx_pwm0_modes,
+ .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_pwm1_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mask = PMX_UART0_MODEM_MASK,
+ }, {
+ .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_pwm1 = {
+ .name = "pwm1",
+ .modes = pmx_pwm1_modes,
+ .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_pwm2_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
+ .mask = PMX_SSP_CS_MASK,
+ }, {
+ .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_pwm2 = {
+ .name = "pwm2",
+ .modes = pmx_pwm2_modes,
+ .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_pwm3_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_pwm3 = {
+ .name = "pwm3",
+ .modes = pmx_pwm3_modes,
+ .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_ssp1_modes[] = {
+ {
+ .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_ssp1 = {
+ .name = "ssp1",
+ .modes = pmx_ssp1_modes,
+ .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_ssp2_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_ssp2 = {
+ .name = "ssp2",
+ .modes = pmx_ssp2_modes,
+ .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_mii1_modes[] = {
+ {
+ .ids = AUTO_NET_MII_MODE,
+ .mask = 0x0,
+ },
+};
+
+struct pmx_dev pmx_mii1 = {
+ .name = "mii1",
+ .modes = pmx_mii1_modes,
+ .mode_count = ARRAY_SIZE(pmx_mii1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_smii0_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_smii0 = {
+ .name = "smii0",
+ .modes = pmx_smii0_modes,
+ .mode_count = ARRAY_SIZE(pmx_smii0_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_smii1_modes[] = {
+ {
+ .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_smii1 = {
+ .name = "smii1",
+ .modes = pmx_smii1_modes,
+ .mode_count = ARRAY_SIZE(pmx_smii1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_i2c1_modes[] = {
+ {
+ .ids = AUTO_EXP_MODE,
+ .mask = 0x0,
+ },
+};
+
+struct pmx_dev pmx_i2c1 = {
+ .name = "i2c1",
+ .modes = pmx_i2c1_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
+ .enb_on_reset = 1,
+};
+
+/* pmx driver structure */
+struct pmx_driver pmx_driver = {
+ .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
+ .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
+};
+
/* Add spear320 specific devices here */
+/* spear320 routines */
void __init spear320_init(void)
{
/* call spear3xx family common init function */
spear3xx_init();
}
+
+void spear320_pmx_init(void)
+{
+ spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
+ SPEAR320_SOC_CONFIG_SIZE);
+}
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 85bc4d2..62ac685 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -16,6 +16,27 @@
#include <mach/generic.h>
#include <mach/spear.h>
+/* padmux devices to enable */
+static struct pmx_dev *pmx_devs[] = {
+ /* spear3xx specific devices */
+ &pmx_i2c,
+ &pmx_ssp,
+ &pmx_mii,
+ &pmx_uart0,
+
+ /* spear320 specific devices */
+ &pmx_fsmc,
+ &pmx_sdio,
+ &pmx_i2s,
+ &pmx_uart1,
+ &pmx_uart2,
+ &pmx_can,
+ &pmx_pwm0,
+ &pmx_pwm1,
+ &pmx_pwm2,
+ &pmx_mii1,
+};
+
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
&gpio_device,
@@ -37,6 +58,12 @@ static void __init spear320_evb_init(void)
/* call spear320 machine init function */
spear320_init();
+ /* padmux initialization */
+ pmx_driver.mode = &auto_net_mii_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
+ spear320_pmx_init();
+
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 82ebcd3..e87313a 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -99,3 +99,450 @@ void __init spear3xx_map_io(void)
/* This will initialize clock framework */
clk_init();
}
+
+/* pad multiplexing support */
+/* devices */
+struct pmx_dev_mode pmx_firda_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_FIRDA_MASK,
+ },
+};
+
+struct pmx_dev pmx_firda = {
+ .name = "firda",
+ .modes = pmx_firda_modes,
+ .mode_count = ARRAY_SIZE(pmx_firda_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_i2c_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_I2C_MASK,
+ },
+};
+
+struct pmx_dev pmx_i2c = {
+ .name = "i2c",
+ .modes = pmx_i2c_modes,
+ .mode_count = ARRAY_SIZE(pmx_i2c_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_ssp_cs_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_SSP_CS_MASK,
+ },
+};
+
+struct pmx_dev pmx_ssp_cs = {
+ .name = "ssp_chip_selects",
+ .modes = pmx_ssp_cs_modes,
+ .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_ssp_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_SSP_MASK,
+ },
+};
+
+struct pmx_dev pmx_ssp = {
+ .name = "ssp",
+ .modes = pmx_ssp_modes,
+ .mode_count = ARRAY_SIZE(pmx_ssp_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_mii_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_mii = {
+ .name = "mii",
+ .modes = pmx_mii_modes,
+ .mode_count = ARRAY_SIZE(pmx_mii_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_GPIO_PIN0_MASK,
+ },
+};
+
+struct pmx_dev pmx_gpio_pin0 = {
+ .name = "gpio_pin0",
+ .modes = pmx_gpio_pin0_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_GPIO_PIN1_MASK,
+ },
+};
+
+struct pmx_dev pmx_gpio_pin1 = {
+ .name = "gpio_pin1",
+ .modes = pmx_gpio_pin1_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_GPIO_PIN2_MASK,
+ },
+};
+
+struct pmx_dev pmx_gpio_pin2 = {
+ .name = "gpio_pin2",
+ .modes = pmx_gpio_pin2_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_GPIO_PIN3_MASK,
+ },
+};
+
+struct pmx_dev pmx_gpio_pin3 = {
+ .name = "gpio_pin3",
+ .modes = pmx_gpio_pin3_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_GPIO_PIN4_MASK,
+ },
+};
+
+struct pmx_dev pmx_gpio_pin4 = {
+ .name = "gpio_pin4",
+ .modes = pmx_gpio_pin4_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_GPIO_PIN5_MASK,
+ },
+};
+
+struct pmx_dev pmx_gpio_pin5 = {
+ .name = "gpio_pin5",
+ .modes = pmx_gpio_pin5_modes,
+ .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_uart0_modem_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_UART0_MODEM_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart0_modem = {
+ .name = "uart0_modem",
+ .modes = pmx_uart0_modem_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_uart0_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_UART0_MASK,
+ },
+};
+
+struct pmx_dev pmx_uart0 = {
+ .name = "uart0",
+ .modes = pmx_uart0_modes,
+ .mode_count = ARRAY_SIZE(pmx_uart0_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_timer_3_4_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_timer_3_4 = {
+ .name = "timer_3_4",
+ .modes = pmx_timer_3_4_modes,
+ .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
+ .enb_on_reset = 0,
+};
+
+struct pmx_dev_mode pmx_timer_1_2_modes[] = {
+ {
+ .ids = 0xffffffff,
+ .mask = PMX_TIMER_1_2_MASK,
+ },
+};
+
+struct pmx_dev pmx_timer_1_2 = {
+ .name = "timer_1_2",
+ .modes = pmx_timer_1_2_modes,
+ .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
+ .enb_on_reset = 0,
+};
+
+#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
+/* plgpios devices */
+struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_FIRDA_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_0_1 = {
+ .name = "plgpio 0 and 1",
+ .modes = pmx_plgpio_0_1_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_UART0_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_2_3 = {
+ .name = "plgpio 2 and 3",
+ .modes = pmx_plgpio_2_3_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_I2C_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_4_5 = {
+ .name = "plgpio 4 and 5",
+ .modes = pmx_plgpio_4_5_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_SSP_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_6_9 = {
+ .name = "plgpio 6 to 9",
+ .modes = pmx_plgpio_6_9_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_MII_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_10_27 = {
+ .name = "plgpio 10 to 27",
+ .modes = pmx_plgpio_10_27_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_28_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_GPIO_PIN0_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_28 = {
+ .name = "plgpio 28",
+ .modes = pmx_plgpio_28_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_29_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_GPIO_PIN1_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_29 = {
+ .name = "plgpio 29",
+ .modes = pmx_plgpio_29_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_30_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_GPIO_PIN2_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_30 = {
+ .name = "plgpio 30",
+ .modes = pmx_plgpio_30_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_31_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_GPIO_PIN3_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_31 = {
+ .name = "plgpio 31",
+ .modes = pmx_plgpio_31_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_32_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_GPIO_PIN4_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_32 = {
+ .name = "plgpio 32",
+ .modes = pmx_plgpio_32_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_33_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_GPIO_PIN5_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_33 = {
+ .name = "plgpio 33",
+ .modes = pmx_plgpio_33_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_SSP_CS_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_34_36 = {
+ .name = "plgpio 34 to 36",
+ .modes = pmx_plgpio_34_36_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_UART0_MODEM_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_37_42 = {
+ .name = "plgpio 37 to 42",
+ .modes = pmx_plgpio_37_42_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_TIMER_1_2_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_43_44_47_48 = {
+ .name = "plgpio 43, 44, 47 and 48",
+ .modes = pmx_plgpio_43_44_47_48_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
+ .enb_on_reset = 1,
+};
+
+struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
+ {
+ .ids = 0x00,
+ .mask = PMX_TIMER_3_4_MASK,
+ },
+};
+
+struct pmx_dev pmx_plgpio_45_46_49_50 = {
+ .name = "plgpio 45, 46, 49 and 50",
+ .modes = pmx_plgpio_45_46_49_50_modes,
+ .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
+ .enb_on_reset = 1,
+};
+
+#endif
+
+/* spear padmux initialization function */
+void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size)
+{
+ int ret = 0;
+
+ /* pad mux initialization */
+ pmx_driver->base = ioremap(base, size);
+ if (!pmx_driver->base) {
+ ret = -ENOMEM;
+ goto pmx_fail;
+ }
+
+ ret = pmx_register(pmx_driver);
+ iounmap(pmx_driver->base);
+
+pmx_fail:
+ if (ret)
+ printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
+ ret);
+}
diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
index 96f9ac3..6f4ad5e 100644
--- a/arch/arm/plat-spear/Makefile
+++ b/arch/arm/plat-spear/Makefile
@@ -3,4 +3,4 @@
#
# Common support
-obj-y := clock.o time.o
+obj-y := clock.o padmux.o time.o
diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
new file mode 100644
index 0000000..877f3ad
--- /dev/null
+++ b/arch/arm/plat-spear/include/plat/padmux.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/plat-spear/include/plat/padmux.h
+ *
+ * SPEAr platform specific gpio pads muxing file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_PADMUX_H
+#define __PLAT_PADMUX_H
+
+#include <linux/types.h>
+
+/*
+ * struct pmx_reg: configuration structure for mode reg and mux reg
+ *
+ * offset: offset of mode reg
+ * mask: mask of mode reg
+ */
+struct pmx_reg {
+ u32 offset;
+ u32 mask;
+};
+
+/*
+ * struct pmx_dev_mode: configuration structure every group of modes of a device
+ *
+ * ids: all modes for this configuration
+ * mask: mask for supported mode
+ */
+struct pmx_dev_mode {
+ u32 ids;
+ u32 mask;
+};
+
+/*
+ * struct pmx_mode: mode definition structure
+ *
+ * name: mode name
+ * mask: mode mask
+ */
+struct pmx_mode {
+ char *name;
+ u32 id;
+ u32 mask;
+};
+
+/*
+ * struct pmx_dev: device definition structure
+ *
+ * name: device name
+ * modes: device configuration array for different modes supported
+ * mode_count: size of modes array
+ * is_active: is peripheral active/enabled
+ * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
+ */
+struct pmx_dev {
+ char *name;
+ struct pmx_dev_mode *modes;
+ u8 mode_count;
+ bool is_active;
+ bool enb_on_reset;
+};
+
+/*
+ * struct pmx_driver: driver definition structure
+ *
+ * mode: mode to be set
+ * devs: array of pointer to pmx devices
+ * devs_count: ARRAY_SIZE of devs
+ * base: base address of soc config registers
+ * mode_reg: structure of mode config register
+ * mux_reg: structure of device mux config register
+ */
+struct pmx_driver {
+ struct pmx_mode *mode;
+ struct pmx_dev **devs;
+ u8 devs_count;
+ u32 *base;
+ struct pmx_reg mode_reg;
+ struct pmx_reg mux_reg;
+};
+
+/* pmx functions */
+int pmx_register(struct pmx_driver *driver);
+
+#endif /* __PLAT_PADMUX_H */
diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
new file mode 100644
index 0000000..d2aab3a
--- /dev/null
+++ b/arch/arm/plat-spear/padmux.c
@@ -0,0 +1,164 @@
+/*
+ * arch/arm/plat-spear/include/plat/padmux.c
+ *
+ * SPEAr platform specific gpio pads muxing source file
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Viresh Kumar<viresh.kumar@st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <plat/padmux.h>
+
+/*
+ * struct pmx: pmx definition structure
+ *
+ * base: base address of configuration registers
+ * mode_reg: mode configurations
+ * mux_reg: muxing configurations
+ * active_mode: pointer to current active mode
+ */
+struct pmx {
+ u32 base;
+ struct pmx_reg mode_reg;
+ struct pmx_reg mux_reg;
+ struct pmx_mode *active_mode;
+};
+
+static struct pmx *pmx;
+
+/**
+ * pmx_mode_set - Enables an multiplexing mode
+ * @mode - pointer to pmx mode
+ *
+ * It will set mode of operation in hardware.
+ * Returns -ve on Err otherwise 0
+ */
+static int pmx_mode_set(struct pmx_mode *mode)
+{
+ u32 val;
+
+ if (!mode->name)
+ return -EFAULT;
+
+ pmx->active_mode = mode;
+
+ val = readl(pmx->base + pmx->mode_reg.offset);
+ val &= ~pmx->mode_reg.mask;
+ val |= mode->mask & pmx->mode_reg.mask;
+ writel(val, pmx->base + pmx->mode_reg.offset);
+
+ return 0;
+}
+
+/**
+ * pmx_devs_enable - Enables list of devices
+ * @devs - pointer to pmx device array
+ * @count - number of devices to enable
+ *
+ * It will enable pads for all required peripherals once and only once.
+ * If peripheral is not supported by current mode then request is rejected.
+ * Conflicts between peripherals are not handled and peripherals will be
+ * enabled in the order they are present in pmx_dev array.
+ * In case of conflicts last peripheral enalbed will be present.
+ * Returns -ve on Err otherwise 0
+ */
+static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
+{
+ u32 val, i, mask;
+
+ if (!count)
+ return -EINVAL;
+
+ val = readl(pmx->base + pmx->mux_reg.offset);
+ for (i = 0; i < count; i++) {
+ u8 j = 0;
+
+ if (!devs[i]->name || !devs[i]->modes) {
+ printk(KERN_ERR "padmux: dev name or modes is null\n");
+ continue;
+ }
+ /* check if peripheral exists in active mode */
+ if (pmx->active_mode) {
+ bool found = false;
+ for (j = 0; j < devs[i]->mode_count; j++) {
+ if (devs[i]->modes[j].ids &
+ pmx->active_mode->id) {
+ found = true;
+ break;
+ }
+ }
+ if (found == false) {
+ printk(KERN_ERR "%s device not available in %s"\
+ "mode\n", devs[i]->name,
+ pmx->active_mode->name);
+ continue;
+ }
+ }
+
+ /* enable peripheral */
+ mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
+ if (devs[i]->enb_on_reset)
+ val &= ~mask;
+ else
+ val |= mask;
+
+ devs[i]->is_active = true;
+ }
+ writel(val, pmx->base + pmx->mux_reg.offset);
+ kfree(pmx);
+
+ /* this will ensure that multiplexing can't be changed now */
+ pmx = (struct pmx *)-1;
+
+ return 0;
+}
+
+/**
+ * pmx_register - registers a platform requesting pad mux feature
+ * @driver - pointer to driver structure containing driver specific parameters
+ *
+ * Also this must be called only once. This will allocate memory for pmx
+ * structure, will call pmx_mode_set, will call pmx_devs_enable.
+ * Returns -ve on Err otherwise 0
+ */
+int pmx_register(struct pmx_driver *driver)
+{
+ int ret = 0;
+
+ if (pmx)
+ return -EPERM;
+ if (!driver->base || !driver->devs)
+ return -EFAULT;
+
+ pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
+ if (!pmx)
+ return -ENOMEM;
+
+ pmx->base = (u32)driver->base;
+ pmx->mode_reg.offset = driver->mode_reg.offset;
+ pmx->mode_reg.mask = driver->mode_reg.mask;
+ pmx->mux_reg.offset = driver->mux_reg.offset;
+ pmx->mux_reg.mask = driver->mux_reg.mask;
+
+ /* choose mode to enable */
+ if (driver->mode) {
+ ret = pmx_mode_set(driver->mode);
+ if (ret)
+ goto pmx_fail;
+ }
+ ret = pmx_devs_enable(driver->devs, driver->devs_count);
+ if (ret)
+ goto pmx_fail;
+
+ return 0;
+
+pmx_fail:
+ return ret;
+}
--
1.6.0.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 12/12] ST SPEAr: Adding gpio pad multiplexing support
2010-03-25 8:40 ` [PATCH V2 Resend 12/12] ST SPEAr: Adding gpio pad multiplexing support Viresh KUMAR
@ 2010-04-03 17:14 ` Shiraz HASHIM
2010-04-05 4:24 ` Viresh KUMAR
0 siblings, 1 reply; 17+ messages in thread
From: Shiraz HASHIM @ 2010-04-03 17:14 UTC (permalink / raw)
To: linux-arm-kernel
Viresh,
On 3/25/2010 2:10 PM, Viresh KUMAR wrote:
> GPIO Pads in spear platform are are multiplexed in various machines.
> This patch adds support for this pad multiplexing.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
> ---
> arch/arm/mach-spear3xx/include/mach/generic.h | 161 +++++++++-
> arch/arm/mach-spear3xx/spear300.c | 358 ++++++++++++++++++++
> arch/arm/mach-spear3xx/spear300_evb.c | 22 ++
> arch/arm/mach-spear3xx/spear310.c | 129 +++++++
> arch/arm/mach-spear3xx/spear310_evb.c | 30 ++
> arch/arm/mach-spear3xx/spear320.c | 374 +++++++++++++++++++++
> arch/arm/mach-spear3xx/spear320_evb.c | 27 ++
> arch/arm/mach-spear3xx/spear3xx.c | 447 +++++++++++++++++++++++++
> arch/arm/plat-spear/Makefile | 2 +-
> arch/arm/plat-spear/include/plat/padmux.h | 92 +++++
> arch/arm/plat-spear/padmux.c | 164 +++++++++
> 11 files changed, 1798 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/plat-spear/include/plat/padmux.h
> create mode 100644 arch/arm/plat-spear/padmux.c
>
> diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
> index aeea845..af7e02c 100644
> --- a/arch/arm/mach-spear3xx/include/mach/generic.h
> +++ b/arch/arm/mach-spear3xx/include/mach/generic.h
> @@ -19,7 +19,9 @@
> #include <linux/init.h>
> #include <linux/platform_device.h>
> #include <linux/amba/bus.h>
> +#include <plat/padmux.h>
>
> +/* spear3xx declarations */
> /*
> * Each GPT has 2 timer channels
> * Following GPT channels will be used as clock source and clockevent
> @@ -34,25 +36,170 @@ extern struct amba_device uart_device;
> extern struct sys_timer spear_sys_timer;
>
> /* Add spear3xx family function declarations here */
> +void __init clk_init(void);
> void __init spear3xx_map_io(void);
> void __init spear3xx_init_irq(void);
> void __init spear3xx_init(void);
> -void __init spear300_init(void);
> -void __init spear310_init(void);
> -void __init spear320_init(void);
> -void __init clk_init(void);
> +void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
>
> -/* Add spear300 machine device structure declarations here */
> +/* pad mux declarations */
These are spear300 soecific declarations, isn't it?
> +#define PMX_FIRDA_MASK (1 << 14)
> +#define PMX_I2C_MASK (1 << 13)
> +#define PMX_SSP_CS_MASK (1 << 12)
> +#define PMX_SSP_MASK (1 << 11)
> +#define PMX_MII_MASK (1 << 10)
> +#define PMX_GPIO_PIN0_MASK (1 << 9)
> +#define PMX_GPIO_PIN1_MASK (1 << 8)
> +#define PMX_GPIO_PIN2_MASK (1 << 7)
> +#define PMX_GPIO_PIN3_MASK (1 << 6)
> +#define PMX_GPIO_PIN4_MASK (1 << 5)
> +#define PMX_GPIO_PIN5_MASK (1 << 4)
> +#define PMX_UART0_MODEM_MASK (1 << 3)
> +#define PMX_UART0_MASK (1 << 2)
> +#define PMX_TIMER_3_4_MASK (1 << 1)
> +#define PMX_TIMER_1_2_MASK (1 << 0)
> +
> +/* pad mux devices */
> +extern struct pmx_dev pmx_firda;
> +extern struct pmx_dev pmx_i2c;
> +extern struct pmx_dev pmx_ssp_cs;
> +extern struct pmx_dev pmx_ssp;
> +extern struct pmx_dev pmx_mii;
> +extern struct pmx_dev pmx_gpio_pin0;
> +extern struct pmx_dev pmx_gpio_pin1;
> +extern struct pmx_dev pmx_gpio_pin2;
> +extern struct pmx_dev pmx_gpio_pin3;
> +extern struct pmx_dev pmx_gpio_pin4;
> +extern struct pmx_dev pmx_gpio_pin5;
> +extern struct pmx_dev pmx_uart0_modem;
> +extern struct pmx_dev pmx_uart0;
> +extern struct pmx_dev pmx_timer_3_4;
> +extern struct pmx_dev pmx_timer_1_2;
> +
> +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
> +/* padmux plgpio devices */
> +extern struct pmx_dev pmx_plgpio_0_1;
> +extern struct pmx_dev pmx_plgpio_2_3;
> +extern struct pmx_dev pmx_plgpio_4_5;
> +extern struct pmx_dev pmx_plgpio_6_9;
> +extern struct pmx_dev pmx_plgpio_10_27;
> +extern struct pmx_dev pmx_plgpio_28;
> +extern struct pmx_dev pmx_plgpio_29;
> +extern struct pmx_dev pmx_plgpio_30;
> +extern struct pmx_dev pmx_plgpio_31;
> +extern struct pmx_dev pmx_plgpio_32;
> +extern struct pmx_dev pmx_plgpio_33;
> +extern struct pmx_dev pmx_plgpio_34_36;
> +extern struct pmx_dev pmx_plgpio_37_42;
> +extern struct pmx_dev pmx_plgpio_43_44_47_48;
> +extern struct pmx_dev pmx_plgpio_45_46_49_50;
> +#endif
> +
> +extern struct pmx_driver pmx_driver;
> +
> +/* spear300 declarations */
> #ifdef CONFIG_MACH_SPEAR300
see above comment
> +/* Add spear300 machine device structure declarations here */
> extern struct amba_device gpio1_device;
> +
> +/* pad mux modes */
> +extern struct pmx_mode nand_mode;
> +extern struct pmx_mode nor_mode;
> +extern struct pmx_mode photo_frame_mode;
> +extern struct pmx_mode lend_ip_phone_mode;
> +extern struct pmx_mode hend_ip_phone_mode;
> +extern struct pmx_mode lend_wifi_phone_mode;
> +extern struct pmx_mode hend_wifi_phone_mode;
> +extern struct pmx_mode ata_pabx_wi2s_mode;
> +extern struct pmx_mode ata_pabx_i2s_mode;
> +extern struct pmx_mode caml_lcdw_mode;
> +extern struct pmx_mode camu_lcd_mode;
> +extern struct pmx_mode camu_wlcd_mode;
> +extern struct pmx_mode caml_lcd_mode;
> +
> +/* pad mux devices */
> +extern struct pmx_dev pmx_fsmc_2_chips;
> +extern struct pmx_dev pmx_fsmc_4_chips;
> +extern struct pmx_dev pmx_keyboard;
> +extern struct pmx_dev pmx_clcd;
> +extern struct pmx_dev pmx_telecom_gpio;
> +extern struct pmx_dev pmx_telecom_tdm;
> +extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk;
> +extern struct pmx_dev pmx_telecom_camera;
> +extern struct pmx_dev pmx_telecom_dac;
> +extern struct pmx_dev pmx_telecom_i2s;
> +extern struct pmx_dev pmx_telecom_boot_pins;
> +extern struct pmx_dev pmx_telecom_sdio_4bit;
> +extern struct pmx_dev pmx_telecom_sdio_8bit;
> +extern struct pmx_dev pmx_gpio1;
> +
> +void spear300_pmx_init(void);
> +
> +/* Add spear300 machine function declarations here */
> +void __init spear300_init(void);
> +
> #endif /* CONFIG_MACH_SPEAR300 */
>
> -/* Add spear310 machine device structure declarations here */
> +/* spear310 declarations */
> #ifdef CONFIG_MACH_SPEAR310
> +/* Add spear310 machine device structure declarations here */
> +
> +/* pad mux devices */
> +extern struct pmx_dev pmx_emi_cs_0_1_4_5;
> +extern struct pmx_dev pmx_emi_cs_2_3;
> +extern struct pmx_dev pmx_uart1;
> +extern struct pmx_dev pmx_uart2;
> +extern struct pmx_dev pmx_uart3_4_5;
> +extern struct pmx_dev pmx_fsmc;
> +extern struct pmx_dev pmx_rs485_0_1;
> +extern struct pmx_dev pmx_tdm0;
> +
> +void spear310_pmx_init(void);
> +
> +/* Add spear310 machine function declarations here */
> +void __init spear310_init(void);
> +
> #endif /* CONFIG_MACH_SPEAR310 */
>
> -/* Add spear320 machine device structure declarations here */
> +/* spear320 declarations */
> #ifdef CONFIG_MACH_SPEAR320
> +/* Add spear320 machine device structure declarations here */
> +
> +/* pad mux modes */
> +extern struct pmx_mode auto_net_smii_mode;
> +extern struct pmx_mode auto_net_mii_mode;
> +extern struct pmx_mode auto_exp_mode;
> +extern struct pmx_mode small_printers_mode;
> +
> +/* pad mux devices */
> +extern struct pmx_dev pmx_clcd;
> +extern struct pmx_dev pmx_emi;
> +extern struct pmx_dev pmx_fsmc;
> +extern struct pmx_dev pmx_spp;
> +extern struct pmx_dev pmx_sdio;
> +extern struct pmx_dev pmx_i2s;
> +extern struct pmx_dev pmx_uart1;
> +extern struct pmx_dev pmx_uart1_modem;
> +extern struct pmx_dev pmx_uart2;
> +extern struct pmx_dev pmx_touchscreen;
> +extern struct pmx_dev pmx_can;
> +extern struct pmx_dev pmx_sdio_led;
> +extern struct pmx_dev pmx_pwm0;
> +extern struct pmx_dev pmx_pwm1;
> +extern struct pmx_dev pmx_pwm2;
> +extern struct pmx_dev pmx_pwm3;
> +extern struct pmx_dev pmx_ssp1;
> +extern struct pmx_dev pmx_ssp2;
> +extern struct pmx_dev pmx_mii1;
> +extern struct pmx_dev pmx_smii0;
> +extern struct pmx_dev pmx_smii1;
> +extern struct pmx_dev pmx_i2c1;
> +
> +void spear320_pmx_init(void);
> +
> +/* Add spear320 machine function declarations here */
> +void __init spear320_init(void);
> +
> #endif /* CONFIG_MACH_SPEAR320 */
>
> #endif /* __MACH_GENERIC_H */
> diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
> index 63aca8f..66e7fcd 100644
> --- a/arch/arm/mach-spear3xx/spear300.c
> +++ b/arch/arm/mach-spear3xx/spear300.c
> @@ -18,6 +18,357 @@
> #include <mach/generic.h>
> #include <mach/spear.h>
>
> +/* pad multiplexing support */
> +/* muxing registers */
> +#define PAD_MUX_CONFIG_REG 0x00
> +#define MODE_CONFIG_REG 0x04
> +
> +/* modes */
> +#define NAND_MODE (1 << 0)
> +#define NOR_MODE (1 << 1)
> +#define PHOTO_FRAME_MODE (1 << 2)
> +#define LEND_IP_PHONE_MODE (1 << 3)
> +#define HEND_IP_PHONE_MODE (1 << 4)
> +#define LEND_WIFI_PHONE_MODE (1 << 5)
> +#define HEND_WIFI_PHONE_MODE (1 << 6)
> +#define ATA_PABX_WI2S_MODE (1 << 7)
> +#define ATA_PABX_I2S_MODE (1 << 8)
> +#define CAML_LCDW_MODE (1 << 9)
> +#define CAMU_LCD_MODE (1 << 10)
> +#define CAMU_WLCD_MODE (1 << 11)
> +#define CAML_LCD_MODE (1 << 12)
> +#define ALL_MODES 0x1FFF
> +
> +struct pmx_mode nand_mode = {
> + .id = NAND_MODE,
> + .name = "nand mode",
> + .mask = 0x00,
> +};
> +
> +struct pmx_mode nor_mode = {
> + .id = NOR_MODE,
> + .name = "nor mode",
> + .mask = 0x01,
> +};
> +
> +struct pmx_mode photo_frame_mode = {
> + .id = PHOTO_FRAME_MODE,
> + .name = "photo frame mode",
> + .mask = 0x02,
> +};
> +
> +struct pmx_mode lend_ip_phone_mode = {
> + .id = LEND_IP_PHONE_MODE,
> + .name = "lend ip phone mode",
> + .mask = 0x03,
> +};
> +
> +struct pmx_mode hend_ip_phone_mode = {
> + .id = HEND_IP_PHONE_MODE,
> + .name = "hend ip phone mode",
> + .mask = 0x04,
> +};
> +
> +struct pmx_mode lend_wifi_phone_mode = {
> + .id = LEND_WIFI_PHONE_MODE,
> + .name = "lend wifi phone mode",
> + .mask = 0x05,
> +};
> +
> +struct pmx_mode hend_wifi_phone_mode = {
> + .id = HEND_WIFI_PHONE_MODE,
> + .name = "hend wifi phone mode",
> + .mask = 0x06,
> +};
> +
> +struct pmx_mode ata_pabx_wi2s_mode = {
> + .id = ATA_PABX_WI2S_MODE,
> + .name = "ata pabx wi2s mode",
> + .mask = 0x07,
> +};
> +
> +struct pmx_mode ata_pabx_i2s_mode = {
> + .id = ATA_PABX_I2S_MODE,
> + .name = "ata pabx i2s mode",
> + .mask = 0x08,
> +};
> +
> +struct pmx_mode caml_lcdw_mode = {
> + .id = CAML_LCDW_MODE,
> + .name = "caml lcdw mode",
> + .mask = 0x0C,
> +};
> +
> +struct pmx_mode camu_lcd_mode = {
> + .id = CAMU_LCD_MODE,
> + .name = "camu lcd mode",
> + .mask = 0x0D,
> +};
> +
> +struct pmx_mode camu_wlcd_mode = {
> + .id = CAMU_WLCD_MODE,
> + .name = "camu wlcd mode",
> + .mask = 0x0E,
> +};
> +
> +struct pmx_mode caml_lcd_mode = {
> + .id = CAML_LCD_MODE,
> + .name = "caml lcd mode",
> + .mask = 0x0F,
> +};
> +
> +/* devices */
> +struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
> + {
> + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
> + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
> + .mask = PMX_FIRDA_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_fsmc_2_chips = {
> + .name = "fsmc_2_chips",
> + .modes = pmx_fsmc_2_chips_modes,
> + .mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
> + {
> + .ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
> + ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
> + .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_fsmc_4_chips = {
> + .name = "fsmc_4_chips",
> + .modes = pmx_fsmc_4_chips_modes,
> + .mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_keyboard_modes[] = {
> + {
> + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
> + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
> + CAML_LCDW_MODE | CAMU_LCD_MODE | CAMU_WLCD_MODE |
> + CAML_LCD_MODE,
> + .mask = 0x0,
> + },
> +};
> +
> +struct pmx_dev pmx_keyboard = {
> + .name = "keyboard",
> + .modes = pmx_keyboard_modes,
> + .mode_count = ARRAY_SIZE(pmx_keyboard_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_clcd_modes[] = {
> + {
> + .ids = PHOTO_FRAME_MODE,
> + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
> + }, {
> + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE |
> + CAMU_LCD_MODE | CAML_LCD_MODE,
> + .mask = PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_clcd = {
> + .name = "clcd",
> + .modes = pmx_clcd_modes,
> + .mode_count = ARRAY_SIZE(pmx_clcd_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
> + {
> + .ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
> + .mask = PMX_MII_MASK,
> + }, {
> + .ids = LEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE,
> + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
> + }, {
> + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_WLCD_MODE,
> + .mask = PMX_MII_MASK | PMX_TIMER_3_4_MASK,
> + }, {
> + .ids = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE,
> + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK,
> + }, {
> + .ids = ATA_PABX_WI2S_MODE,
> + .mask = PMX_MII_MASK | PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK
> + | PMX_UART0_MODEM_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_gpio = {
> + .name = "telecom_gpio",
> + .modes = pmx_telecom_gpio_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
> + {
> + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
> + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
> + | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE
> + | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
> + | CAMU_WLCD_MODE | CAML_LCD_MODE,
> + .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_tdm = {
> + .name = "telecom_tdm",
> + .modes = pmx_telecom_tdm_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
> + {
> + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
> + LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
> + | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE |
> + CAML_LCDW_MODE | CAML_LCD_MODE,
> + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
> + .name = "telecom_spi_cs_i2c_clk",
> + .modes = pmx_telecom_spi_cs_i2c_clk_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_camera_modes[] = {
> + {
> + .ids = CAML_LCDW_MODE | CAML_LCD_MODE,
> + .mask = PMX_MII_MASK,
> + }, {
> + .ids = CAMU_LCD_MODE | CAMU_WLCD_MODE,
> + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK | PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_camera = {
> + .name = "telecom_camera",
> + .modes = pmx_telecom_camera_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_dac_modes[] = {
> + {
> + .ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
> + | CAMU_WLCD_MODE | CAML_LCD_MODE,
> + .mask = PMX_TIMER_1_2_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_dac = {
> + .name = "telecom_dac",
> + .modes = pmx_telecom_dac_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
> + {
> + .ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
> + | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
> + ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
> + | CAMU_WLCD_MODE | CAML_LCD_MODE,
> + .mask = PMX_UART0_MODEM_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_i2s = {
> + .name = "telecom_i2s",
> + .modes = pmx_telecom_i2s_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
> + {
> + .ids = NAND_MODE | NOR_MODE,
> + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
> + PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_boot_pins = {
> + .name = "telecom_boot_pins",
> + .modes = pmx_telecom_boot_pins_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
> + {
> + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
> + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
> + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
> + CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE |
> + ATA_PABX_I2S_MODE,
> + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
> + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
> + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_sdio_4bit = {
> + .name = "telecom_sdio_4bit",
> + .modes = pmx_telecom_sdio_4bit_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
> + {
> + .ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
> + HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
> + HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE |
> + CAMU_WLCD_MODE | CAML_LCD_MODE,
> + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
> + PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
> + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_telecom_sdio_8bit = {
> + .name = "telecom_sdio_8bit",
> + .modes = pmx_telecom_sdio_8bit_modes,
> + .mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_gpio1_modes[] = {
> + {
> + .ids = PHOTO_FRAME_MODE,
> + .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
> + PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_gpio1 = {
> + .name = "arm gpio1",
> + .modes = pmx_gpio1_modes,
> + .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
> + .enb_on_reset = 1,
> +};
We have generalized pmx_dev in mode and mask attributes. Is it generic enough?
What if we have several mux register in same mode?
> +
> +/* pmx driver structure */
> +struct pmx_driver pmx_driver = {
> + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
> + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
> +};
We assume that all SoCs would either have a mode register or a mux register or
both. Is this assumption generic enough. What if we have
- more than 1 mux register
- more than 1 mode register
- may be a submode register in some new silicon.
> +
> /* Add spear300 specific devices here */
> /* arm gpio1 device registeration */
> static struct pl061_platform_data gpio1_plat_data = {
> @@ -38,8 +389,15 @@ struct amba_device gpio1_device = {
> .irq = {IRQ_GEN_RAS_1, NO_IRQ},
> };
>
> +/* spear300 routines */
> void __init spear300_init(void)
> {
> /* call spear3xx family common init function */
> spear3xx_init();
> }
> +
> +void spear300_pmx_init(void)
> +{
> + spear_pmx_init(&pmx_driver, SPEAR300_SOC_CONFIG_BASE,
> + SPEAR300_SOC_CONFIG_SIZE);
> +}
> diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
> index 1272a38..bb21db1 100644
> --- a/arch/arm/mach-spear3xx/spear300_evb.c
> +++ b/arch/arm/mach-spear3xx/spear300_evb.c
> @@ -16,6 +16,22 @@
> #include <mach/generic.h>
> #include <mach/spear.h>
>
> +/* padmux devices to enable */
> +static struct pmx_dev *pmx_devs[] = {
> + /* spear3xx specific devices */
> + &pmx_i2c,
> + &pmx_ssp_cs,
> + &pmx_ssp,
> + &pmx_mii,
> + &pmx_uart0,
> +
> + /* spear300 specific devices */
> + &pmx_fsmc_2_chips,
> + &pmx_clcd,
> + &pmx_telecom_sdio_4bit,
> + &pmx_gpio1,
> +};
> +
> static struct amba_device *amba_devs[] __initdata = {
> /* spear3xx specific devices */
> &gpio_device,
> @@ -38,6 +54,12 @@ static void __init spear300_evb_init(void)
> /* call spear300 machine init function */
> spear300_init();
>
> + /* padmux initialization */
> + pmx_driver.mode = &photo_frame_mode;
> + pmx_driver.devs = pmx_devs;
> + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
> + spear300_pmx_init();
Intializing pmx_driver and not using it directly obstructs readability.
Better to pass pmx_driver and other info in spear300_pmx_init itself.
What is your opinion?
> +
> /* Add Platform Devices */
> platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
>
> diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
> index 6eb62f9..dd5a572 100644
> --- a/arch/arm/mach-spear3xx/spear310.c
> +++ b/arch/arm/mach-spear3xx/spear310.c
> @@ -16,10 +16,139 @@
> #include <mach/generic.h>
> #include <mach/spear.h>
>
> +/* pad multiplexing support */
> +/* muxing registers */
> +#define PAD_MUX_CONFIG_REG 0x08
> +
> +/* devices */
> +struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_emi_cs_0_1_4_5 = {
> + .name = "emi_cs_0_1_4_5",
> + .modes = pmx_emi_cs_0_1_4_5_modes,
> + .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_TIMER_1_2_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_emi_cs_2_3 = {
> + .name = "emi_cs_2_3",
> + .modes = pmx_emi_cs_2_3_modes,
> + .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_uart1_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_FIRDA_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart1 = {
> + .name = "uart1",
> + .modes = pmx_uart1_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_uart2_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_TIMER_1_2_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart2 = {
> + .name = "uart2",
> + .modes = pmx_uart2_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart2_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_UART0_MODEM_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart3_4_5 = {
> + .name = "uart3_4_5",
> + .modes = pmx_uart3_4_5_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_fsmc_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_SSP_CS_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_fsmc = {
> + .name = "fsmc",
> + .modes = pmx_fsmc_modes,
> + .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_rs485_0_1 = {
> + .name = "rs485_0_1",
> + .modes = pmx_rs485_0_1_modes,
> + .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_tdm0_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_tdm0 = {
> + .name = "tdm0",
> + .modes = pmx_tdm0_modes,
> + .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
> + .enb_on_reset = 1,
> +};
> +
> +/* pmx driver structure */
> +struct pmx_driver pmx_driver = {
> + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
> +};
> +
> /* Add spear310 specific devices here */
>
> +/* spear310 routines */
> void __init spear310_init(void)
> {
> /* call spear3xx family common init function */
> spear3xx_init();
> }
> +
> +void spear310_pmx_init(void)
> +{
> + spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
> + SPEAR310_SOC_CONFIG_SIZE);
> +}
> diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
> index e781b2b..7facf66 100644
> --- a/arch/arm/mach-spear3xx/spear310_evb.c
> +++ b/arch/arm/mach-spear3xx/spear310_evb.c
> @@ -16,6 +16,30 @@
> #include <mach/generic.h>
> #include <mach/spear.h>
>
> +/* padmux devices to enable */
> +static struct pmx_dev *pmx_devs[] = {
> + /* spear3xx specific devices */
> + &pmx_i2c,
> + &pmx_ssp,
> + &pmx_gpio_pin0,
> + &pmx_gpio_pin1,
> + &pmx_gpio_pin2,
> + &pmx_gpio_pin3,
> + &pmx_gpio_pin4,
> + &pmx_gpio_pin5,
> + &pmx_uart0,
> +
> + /* spear310 specific devices */
> + &pmx_emi_cs_0_1_4_5,
> + &pmx_emi_cs_2_3,
> + &pmx_uart1,
> + &pmx_uart2,
> + &pmx_uart3_4_5,
> + &pmx_fsmc,
> + &pmx_rs485_0_1,
> + &pmx_tdm0,
> +};
> +
> static struct amba_device *amba_devs[] __initdata = {
> /* spear3xx specific devices */
> &gpio_device,
> @@ -37,6 +61,12 @@ static void __init spear310_evb_init(void)
> /* call spear310 machine init function */
> spear310_init();
>
> + /* padmux initialization */
> + pmx_driver.mode = NULL;
> + pmx_driver.devs = pmx_devs;
> + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
> + spear310_pmx_init();
I see your point in not passing pmx_driver here. It is due to initialization of
pmx_driver.mux fields. This field is specific to mach so may not be defined in
board file. Any other idea to overcome this little readability issue?
> +
> /* Add Platform Devices */
> platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
>
> diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
> index 72d4548..2cedf5e 100644
> --- a/arch/arm/mach-spear3xx/spear320.c
> +++ b/arch/arm/mach-spear3xx/spear320.c
> @@ -16,10 +16,384 @@
> #include <mach/generic.h>
> #include <mach/spear.h>
>
> +/* pad multiplexing support */
> +/* muxing registers */
> +#define PAD_MUX_CONFIG_REG 0x0C
> +#define MODE_CONFIG_REG 0x10
> +
> +/* modes */
> +#define AUTO_NET_SMII_MODE (1 << 0)
> +#define AUTO_NET_MII_MODE (1 << 1)
> +#define AUTO_EXP_MODE (1 << 2)
> +#define SMALL_PRINTERS_MODE (1 << 3)
> +#define ALL_MODES 0xF
> +
> +struct pmx_mode auto_net_smii_mode = {
> + .id = AUTO_NET_SMII_MODE,
> + .name = "Automation Networking SMII Mode",
> + .mask = 0x00,
> +};
> +
> +struct pmx_mode auto_net_mii_mode = {
> + .id = AUTO_NET_MII_MODE,
> + .name = "Automation Networking MII Mode",
> + .mask = 0x01,
> +};
> +
> +struct pmx_mode auto_exp_mode = {
> + .id = AUTO_EXP_MODE,
> + .name = "Automation Expanded Mode",
> + .mask = 0x02,
> +};
> +
> +struct pmx_mode small_printers_mode = {
> + .id = SMALL_PRINTERS_MODE,
> + .name = "Small Printers Mode",
> + .mask = 0x03,
> +};
> +
> +/* devices */
> +struct pmx_dev_mode pmx_clcd_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE,
> + .mask = 0x0,
> + },
> +};
> +
> +struct pmx_dev pmx_clcd = {
> + .name = "clcd",
> + .modes = pmx_clcd_modes,
> + .mode_count = ARRAY_SIZE(pmx_clcd_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_emi_modes[] = {
> + {
> + .ids = AUTO_EXP_MODE,
> + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_emi = {
> + .name = "emi",
> + .modes = pmx_emi_modes,
> + .mode_count = ARRAY_SIZE(pmx_emi_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_fsmc_modes[] = {
> + {
> + .ids = ALL_MODES,
> + .mask = 0x0,
> + },
> +};
> +
> +struct pmx_dev pmx_fsmc = {
> + .name = "fsmc",
> + .modes = pmx_fsmc_modes,
> + .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_spp_modes[] = {
> + {
> + .ids = SMALL_PRINTERS_MODE,
> + .mask = 0x0,
> + },
> +};
> +
> +struct pmx_dev pmx_spp = {
> + .name = "spp",
> + .modes = pmx_spp_modes,
> + .mode_count = ARRAY_SIZE(pmx_spp_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_sdio_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
> + SMALL_PRINTERS_MODE,
> + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_sdio = {
> + .name = "sdio",
> + .modes = pmx_sdio_modes,
> + .mode_count = ARRAY_SIZE(pmx_sdio_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_i2s_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
> + .mask = PMX_UART0_MODEM_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_i2s = {
> + .name = "i2s",
> + .modes = pmx_i2s_modes,
> + .mode_count = ARRAY_SIZE(pmx_i2s_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_uart1_modes[] = {
> + {
> + .ids = ALL_MODES,
> + .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart1 = {
> + .name = "uart1",
> + .modes = pmx_uart1_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_uart1_modem_modes[] = {
> + {
> + .ids = AUTO_EXP_MODE,
> + .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
> + PMX_SSP_CS_MASK,
> + }, {
> + .ids = SMALL_PRINTERS_MODE,
> + .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
> + PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart1_modem = {
> + .name = "uart1_modem",
> + .modes = pmx_uart1_modem_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_uart2_modes[] = {
> + {
> + .ids = ALL_MODES,
> + .mask = PMX_FIRDA_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart2 = {
> + .name = "uart2",
> + .modes = pmx_uart2_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart2_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_touchscreen_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE,
> + .mask = PMX_SSP_CS_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_touchscreen = {
> + .name = "touchscreen",
> + .modes = pmx_touchscreen_modes,
> + .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_can_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
> + .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
> + PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_can = {
> + .name = "can",
> + .modes = pmx_can_modes,
> + .mode_count = ARRAY_SIZE(pmx_can_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_sdio_led_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
> + .mask = PMX_SSP_CS_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_sdio_led = {
> + .name = "sdio_led",
> + .modes = pmx_sdio_led_modes,
> + .mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_pwm0_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
> + .mask = PMX_UART0_MODEM_MASK,
> + }, {
> + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_pwm0 = {
> + .name = "pwm0",
> + .modes = pmx_pwm0_modes,
> + .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_pwm1_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
> + .mask = PMX_UART0_MODEM_MASK,
> + }, {
> + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_pwm1 = {
> + .name = "pwm1",
> + .modes = pmx_pwm1_modes,
> + .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_pwm2_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
> + .mask = PMX_SSP_CS_MASK,
> + }, {
> + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_pwm2 = {
> + .name = "pwm2",
> + .modes = pmx_pwm2_modes,
> + .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_pwm3_modes[] = {
> + {
> + .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_pwm3 = {
> + .name = "pwm3",
> + .modes = pmx_pwm3_modes,
> + .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_ssp1_modes[] = {
> + {
> + .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_ssp1 = {
> + .name = "ssp1",
> + .modes = pmx_ssp1_modes,
> + .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_ssp2_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_ssp2 = {
> + .name = "ssp2",
> + .modes = pmx_ssp2_modes,
> + .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_mii1_modes[] = {
> + {
> + .ids = AUTO_NET_MII_MODE,
> + .mask = 0x0,
> + },
> +};
> +
> +struct pmx_dev pmx_mii1 = {
> + .name = "mii1",
> + .modes = pmx_mii1_modes,
> + .mode_count = ARRAY_SIZE(pmx_mii1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_smii0_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_smii0 = {
> + .name = "smii0",
> + .modes = pmx_smii0_modes,
> + .mode_count = ARRAY_SIZE(pmx_smii0_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_smii1_modes[] = {
> + {
> + .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_smii1 = {
> + .name = "smii1",
> + .modes = pmx_smii1_modes,
> + .mode_count = ARRAY_SIZE(pmx_smii1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_i2c1_modes[] = {
> + {
> + .ids = AUTO_EXP_MODE,
> + .mask = 0x0,
> + },
> +};
> +
> +struct pmx_dev pmx_i2c1 = {
> + .name = "i2c1",
> + .modes = pmx_i2c1_modes,
> + .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +/* pmx driver structure */
> +struct pmx_driver pmx_driver = {
> + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
> + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
> +};
> +
> /* Add spear320 specific devices here */
>
> +/* spear320 routines */
> void __init spear320_init(void)
> {
> /* call spear3xx family common init function */
> spear3xx_init();
> }
> +
> +void spear320_pmx_init(void)
> +{
> + spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
> + SPEAR320_SOC_CONFIG_SIZE);
> +}
> diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
> index 85bc4d2..62ac685 100644
> --- a/arch/arm/mach-spear3xx/spear320_evb.c
> +++ b/arch/arm/mach-spear3xx/spear320_evb.c
> @@ -16,6 +16,27 @@
> #include <mach/generic.h>
> #include <mach/spear.h>
>
> +/* padmux devices to enable */
> +static struct pmx_dev *pmx_devs[] = {
> + /* spear3xx specific devices */
> + &pmx_i2c,
> + &pmx_ssp,
> + &pmx_mii,
> + &pmx_uart0,
> +
> + /* spear320 specific devices */
> + &pmx_fsmc,
> + &pmx_sdio,
> + &pmx_i2s,
> + &pmx_uart1,
> + &pmx_uart2,
> + &pmx_can,
> + &pmx_pwm0,
> + &pmx_pwm1,
> + &pmx_pwm2,
> + &pmx_mii1,
> +};
> +
> static struct amba_device *amba_devs[] __initdata = {
> /* spear3xx specific devices */
> &gpio_device,
> @@ -37,6 +58,12 @@ static void __init spear320_evb_init(void)
> /* call spear320 machine init function */
> spear320_init();
>
> + /* padmux initialization */
> + pmx_driver.mode = &auto_net_mii_mode;
> + pmx_driver.devs = pmx_devs;
> + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
> + spear320_pmx_init();
> +
> /* Add Platform Devices */
> platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
>
> diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
> index 82ebcd3..e87313a 100644
> --- a/arch/arm/mach-spear3xx/spear3xx.c
> +++ b/arch/arm/mach-spear3xx/spear3xx.c
> @@ -99,3 +99,450 @@ void __init spear3xx_map_io(void)
> /* This will initialize clock framework */
> clk_init();
> }
> +
> +/* pad multiplexing support */
> +/* devices */
> +struct pmx_dev_mode pmx_firda_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_FIRDA_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_firda = {
> + .name = "firda",
> + .modes = pmx_firda_modes,
> + .mode_count = ARRAY_SIZE(pmx_firda_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_i2c_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_I2C_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_i2c = {
> + .name = "i2c",
> + .modes = pmx_i2c_modes,
> + .mode_count = ARRAY_SIZE(pmx_i2c_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_ssp_cs_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_SSP_CS_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_ssp_cs = {
> + .name = "ssp_chip_selects",
> + .modes = pmx_ssp_cs_modes,
> + .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_ssp_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_SSP_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_ssp = {
> + .name = "ssp",
> + .modes = pmx_ssp_modes,
> + .mode_count = ARRAY_SIZE(pmx_ssp_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_mii_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_mii = {
> + .name = "mii",
> + .modes = pmx_mii_modes,
> + .mode_count = ARRAY_SIZE(pmx_mii_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_GPIO_PIN0_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_gpio_pin0 = {
> + .name = "gpio_pin0",
> + .modes = pmx_gpio_pin0_modes,
> + .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_GPIO_PIN1_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_gpio_pin1 = {
> + .name = "gpio_pin1",
> + .modes = pmx_gpio_pin1_modes,
> + .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_GPIO_PIN2_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_gpio_pin2 = {
> + .name = "gpio_pin2",
> + .modes = pmx_gpio_pin2_modes,
> + .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_GPIO_PIN3_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_gpio_pin3 = {
> + .name = "gpio_pin3",
> + .modes = pmx_gpio_pin3_modes,
> + .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_GPIO_PIN4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_gpio_pin4 = {
> + .name = "gpio_pin4",
> + .modes = pmx_gpio_pin4_modes,
> + .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_GPIO_PIN5_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_gpio_pin5 = {
> + .name = "gpio_pin5",
> + .modes = pmx_gpio_pin5_modes,
> + .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_uart0_modem_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_UART0_MODEM_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart0_modem = {
> + .name = "uart0_modem",
> + .modes = pmx_uart0_modem_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_uart0_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_UART0_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_uart0 = {
> + .name = "uart0",
> + .modes = pmx_uart0_modes,
> + .mode_count = ARRAY_SIZE(pmx_uart0_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_timer_3_4_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_timer_3_4 = {
> + .name = "timer_3_4",
> + .modes = pmx_timer_3_4_modes,
> + .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
> + .enb_on_reset = 0,
> +};
> +
> +struct pmx_dev_mode pmx_timer_1_2_modes[] = {
> + {
> + .ids = 0xffffffff,
> + .mask = PMX_TIMER_1_2_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_timer_1_2 = {
> + .name = "timer_1_2",
> + .modes = pmx_timer_1_2_modes,
> + .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
> + .enb_on_reset = 0,
> +};
> +
> +#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
> +/* plgpios devices */
> +struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_FIRDA_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_0_1 = {
> + .name = "plgpio 0 and 1",
> + .modes = pmx_plgpio_0_1_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_UART0_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_2_3 = {
> + .name = "plgpio 2 and 3",
> + .modes = pmx_plgpio_2_3_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_I2C_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_4_5 = {
> + .name = "plgpio 4 and 5",
> + .modes = pmx_plgpio_4_5_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_SSP_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_6_9 = {
> + .name = "plgpio 6 to 9",
> + .modes = pmx_plgpio_6_9_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_MII_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_10_27 = {
> + .name = "plgpio 10 to 27",
> + .modes = pmx_plgpio_10_27_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_28_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_GPIO_PIN0_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_28 = {
> + .name = "plgpio 28",
> + .modes = pmx_plgpio_28_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_29_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_GPIO_PIN1_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_29 = {
> + .name = "plgpio 29",
> + .modes = pmx_plgpio_29_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_30_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_GPIO_PIN2_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_30 = {
> + .name = "plgpio 30",
> + .modes = pmx_plgpio_30_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_31_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_GPIO_PIN3_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_31 = {
> + .name = "plgpio 31",
> + .modes = pmx_plgpio_31_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_32_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_GPIO_PIN4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_32 = {
> + .name = "plgpio 32",
> + .modes = pmx_plgpio_32_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_33_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_GPIO_PIN5_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_33 = {
> + .name = "plgpio 33",
> + .modes = pmx_plgpio_33_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_SSP_CS_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_34_36 = {
> + .name = "plgpio 34 to 36",
> + .modes = pmx_plgpio_34_36_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_UART0_MODEM_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_37_42 = {
> + .name = "plgpio 37 to 42",
> + .modes = pmx_plgpio_37_42_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_TIMER_1_2_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_43_44_47_48 = {
> + .name = "plgpio 43, 44, 47 and 48",
> + .modes = pmx_plgpio_43_44_47_48_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
> + .enb_on_reset = 1,
> +};
> +
> +struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
> + {
> + .ids = 0x00,
> + .mask = PMX_TIMER_3_4_MASK,
> + },
> +};
> +
> +struct pmx_dev pmx_plgpio_45_46_49_50 = {
> + .name = "plgpio 45, 46, 49 and 50",
> + .modes = pmx_plgpio_45_46_49_50_modes,
> + .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
> + .enb_on_reset = 1,
> +};
> +
> +#endif
> +
> +/* spear padmux initialization function */
> +void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size)
> +{
> + int ret = 0;
> +
> + /* pad mux initialization */
> + pmx_driver->base = ioremap(base, size);
> + if (!pmx_driver->base) {
> + ret = -ENOMEM;
> + goto pmx_fail;
> + }
> +
> + ret = pmx_register(pmx_driver);
> + iounmap(pmx_driver->base);
> +
> +pmx_fail:
> + if (ret)
> + printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
> + ret);
> +}
> diff --git a/arch/arm/plat-spear/Makefile b/arch/arm/plat-spear/Makefile
> index 96f9ac3..6f4ad5e 100644
> --- a/arch/arm/plat-spear/Makefile
> +++ b/arch/arm/plat-spear/Makefile
> @@ -3,4 +3,4 @@
> #
>
> # Common support
> -obj-y := clock.o time.o
> +obj-y := clock.o padmux.o time.o
> diff --git a/arch/arm/plat-spear/include/plat/padmux.h b/arch/arm/plat-spear/include/plat/padmux.h
> new file mode 100644
> index 0000000..877f3ad
> --- /dev/null
> +++ b/arch/arm/plat-spear/include/plat/padmux.h
> @@ -0,0 +1,92 @@
> +/*
> + * arch/arm/plat-spear/include/plat/padmux.h
> + *
> + * SPEAr platform specific gpio pads muxing file
> + *
> + * Copyright (C) 2009 ST Microelectronics
> + * Viresh Kumar<viresh.kumar@st.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __PLAT_PADMUX_H
> +#define __PLAT_PADMUX_H
> +
> +#include <linux/types.h>
> +
> +/*
> + * struct pmx_reg: configuration structure for mode reg and mux reg
> + *
> + * offset: offset of mode reg
> + * mask: mask of mode reg
> + */
> +struct pmx_reg {
> + u32 offset;
> + u32 mask;
> +};
> +
> +/*
> + * struct pmx_dev_mode: configuration structure every group of modes of a device
> + *
> + * ids: all modes for this configuration
> + * mask: mask for supported mode
> + */
> +struct pmx_dev_mode {
> + u32 ids;
> + u32 mask;
> +};
> +
> +/*
> + * struct pmx_mode: mode definition structure
> + *
> + * name: mode name
> + * mask: mode mask
> + */
> +struct pmx_mode {
> + char *name;
> + u32 id;
> + u32 mask;
> +};
> +
> +/*
> + * struct pmx_dev: device definition structure
> + *
> + * name: device name
> + * modes: device configuration array for different modes supported
> + * mode_count: size of modes array
> + * is_active: is peripheral active/enabled
> + * enb_on_reset: if 1, mask bits to be cleared in reg otherwise to be set in reg
> + */
> +struct pmx_dev {
> + char *name;
> + struct pmx_dev_mode *modes;
> + u8 mode_count;
> + bool is_active;
> + bool enb_on_reset;
> +};
> +
> +/*
> + * struct pmx_driver: driver definition structure
> + *
> + * mode: mode to be set
> + * devs: array of pointer to pmx devices
> + * devs_count: ARRAY_SIZE of devs
> + * base: base address of soc config registers
> + * mode_reg: structure of mode config register
> + * mux_reg: structure of device mux config register
> + */
> +struct pmx_driver {
> + struct pmx_mode *mode;
> + struct pmx_dev **devs;
> + u8 devs_count;
> + u32 *base;
> + struct pmx_reg mode_reg;
> + struct pmx_reg mux_reg;
> +};
> +
> +/* pmx functions */
> +int pmx_register(struct pmx_driver *driver);
> +
> +#endif /* __PLAT_PADMUX_H */
> diff --git a/arch/arm/plat-spear/padmux.c b/arch/arm/plat-spear/padmux.c
> new file mode 100644
> index 0000000..d2aab3a
> --- /dev/null
> +++ b/arch/arm/plat-spear/padmux.c
> @@ -0,0 +1,164 @@
> +/*
> + * arch/arm/plat-spear/include/plat/padmux.c
> + *
> + * SPEAr platform specific gpio pads muxing source file
> + *
> + * Copyright (C) 2009 ST Microelectronics
> + * Viresh Kumar<viresh.kumar@st.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/slab.h>
> +#include <plat/padmux.h>
> +
> +/*
> + * struct pmx: pmx definition structure
> + *
> + * base: base address of configuration registers
> + * mode_reg: mode configurations
> + * mux_reg: muxing configurations
> + * active_mode: pointer to current active mode
> + */
> +struct pmx {
> + u32 base;
> + struct pmx_reg mode_reg;
> + struct pmx_reg mux_reg;
> + struct pmx_mode *active_mode;
> +};
> +
> +static struct pmx *pmx;
> +
> +/**
> + * pmx_mode_set - Enables an multiplexing mode
> + * @mode - pointer to pmx mode
> + *
> + * It will set mode of operation in hardware.
> + * Returns -ve on Err otherwise 0
> + */
> +static int pmx_mode_set(struct pmx_mode *mode)
> +{
> + u32 val;
> +
> + if (!mode->name)
> + return -EFAULT;
> +
> + pmx->active_mode = mode;
> +
> + val = readl(pmx->base + pmx->mode_reg.offset);
> + val &= ~pmx->mode_reg.mask;
> + val |= mode->mask & pmx->mode_reg.mask;
> + writel(val, pmx->base + pmx->mode_reg.offset);
> +
> + return 0;
> +}
> +
> +/**
> + * pmx_devs_enable - Enables list of devices
> + * @devs - pointer to pmx device array
> + * @count - number of devices to enable
> + *
> + * It will enable pads for all required peripherals once and only once.
> + * If peripheral is not supported by current mode then request is rejected.
> + * Conflicts between peripherals are not handled and peripherals will be
> + * enabled in the order they are present in pmx_dev array.
> + * In case of conflicts last peripheral enalbed will be present.
> + * Returns -ve on Err otherwise 0
> + */
> +static int pmx_devs_enable(struct pmx_dev **devs, u8 count)
> +{
> + u32 val, i, mask;
> +
> + if (!count)
> + return -EINVAL;
> +
> + val = readl(pmx->base + pmx->mux_reg.offset);
> + for (i = 0; i < count; i++) {
> + u8 j = 0;
> +
> + if (!devs[i]->name || !devs[i]->modes) {
> + printk(KERN_ERR "padmux: dev name or modes is null\n");
> + continue;
> + }
> + /* check if peripheral exists in active mode */
> + if (pmx->active_mode) {
> + bool found = false;
> + for (j = 0; j < devs[i]->mode_count; j++) {
> + if (devs[i]->modes[j].ids &
> + pmx->active_mode->id) {
> + found = true;
> + break;
> + }
> + }
> + if (found == false) {
> + printk(KERN_ERR "%s device not available in %s"\
> + "mode\n", devs[i]->name,
> + pmx->active_mode->name);
> + continue;
> + }
> + }
> +
> + /* enable peripheral */
> + mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
Didn't understand this line.
> + if (devs[i]->enb_on_reset)
> + val &= ~mask;
> + else
> + val |= mask;
> +
> + devs[i]->is_active = true;
> + }
> + writel(val, pmx->base + pmx->mux_reg.offset);
> + kfree(pmx);
> +
> + /* this will ensure that multiplexing can't be changed now */
> + pmx = (struct pmx *)-1;
> +
> + return 0;
> +}
> +
> +/**
> + * pmx_register - registers a platform requesting pad mux feature
> + * @driver - pointer to driver structure containing driver specific parameters
> + *
> + * Also this must be called only once. This will allocate memory for pmx
> + * structure, will call pmx_mode_set, will call pmx_devs_enable.
> + * Returns -ve on Err otherwise 0
> + */
> +int pmx_register(struct pmx_driver *driver)
> +{
> + int ret = 0;
> +
> + if (pmx)
> + return -EPERM;
> + if (!driver->base || !driver->devs)
> + return -EFAULT;
> +
> + pmx = kzalloc(sizeof(*pmx), GFP_KERNEL);
> + if (!pmx)
> + return -ENOMEM;
> +
> + pmx->base = (u32)driver->base;
> + pmx->mode_reg.offset = driver->mode_reg.offset;
> + pmx->mode_reg.mask = driver->mode_reg.mask;
> + pmx->mux_reg.offset = driver->mux_reg.offset;
> + pmx->mux_reg.mask = driver->mux_reg.mask;
> +
> + /* choose mode to enable */
> + if (driver->mode) {
> + ret = pmx_mode_set(driver->mode);
> + if (ret)
> + goto pmx_fail;
> + }
> + ret = pmx_devs_enable(driver->devs, driver->devs_count);
> + if (ret)
> + goto pmx_fail;
> +
> + return 0;
> +
> +pmx_fail:
> + return ret;
> +}
regards
Shiraz
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 12/12] ST SPEAr: Adding gpio pad multiplexing support
2010-04-03 17:14 ` Shiraz HASHIM
@ 2010-04-05 4:24 ` Viresh KUMAR
2010-04-05 7:15 ` Shiraz HASHIM
0 siblings, 1 reply; 17+ messages in thread
From: Viresh KUMAR @ 2010-04-05 4:24 UTC (permalink / raw)
To: linux-arm-kernel
On 4/3/2010 10:44 PM, Shiraz HASHIM wrote:
>> /* Add spear3xx family function declarations here */
>> +void __init clk_init(void);
>> void __init spear3xx_map_io(void);
>> void __init spear3xx_init_irq(void);
>> void __init spear3xx_init(void);
>> -void __init spear300_init(void);
>> -void __init spear310_init(void);
>> -void __init spear320_init(void);
>> -void __init clk_init(void);
>> +void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
>>
>> -/* Add spear300 machine device structure declarations here */
>> +/* pad mux declarations */
> These are spear300 soecific declarations, isn't it?
No. I have added few spear3xx specific declarations here and moved spear300
declarations later in the list.
>
>> +#define PMX_FIRDA_MASK (1 << 14)
>> +#define PMX_I2C_MASK (1 << 13)
>> +#define PMX_SSP_CS_MASK (1 << 12)
>> +#define PMX_SSP_MASK (1 << 11)
>> +#define PMX_MII_MASK (1 << 10)
>> +#define PMX_GPIO_PIN0_MASK (1 << 9)
>> +#define PMX_GPIO_PIN1_MASK (1 << 8)
>> +#define PMX_GPIO_PIN2_MASK (1 << 7)
>> +#define PMX_GPIO_PIN3_MASK (1 << 6)
>> +#define PMX_GPIO_PIN4_MASK (1 << 5)
>> +#define PMX_GPIO_PIN5_MASK (1 << 4)
>> +#define PMX_UART0_MODEM_MASK (1 << 3)
>> +#define PMX_UART0_MASK (1 << 2)
>> +#define PMX_TIMER_3_4_MASK (1 << 1)
>> +#define PMX_TIMER_1_2_MASK (1 << 0)
>> +
>> +extern struct pmx_driver pmx_driver;
>> +
>> +/* spear300 declarations */
>> #ifdef CONFIG_MACH_SPEAR300
>
> see above comment
explained above
>
>> +/* Add spear300 machine device structure declarations here */
>> extern struct amba_device gpio1_device;
>> +
>> +/* pad mux modes */
>> +extern struct pmx_mode nand_mode;
>> +extern struct pmx_mode nor_mode;
>> +extern struct pmx_mode photo_frame_mode;
>> +extern struct pmx_mode lend_ip_phone_mode;
>> +extern struct pmx_mode hend_ip_phone_mode;
>> +extern struct pmx_mode lend_wifi_phone_mode;
>> +extern struct pmx_mode hend_wifi_phone_mode;
>> +extern struct pmx_mode ata_pabx_wi2s_mode;
>> +extern struct pmx_mode ata_pabx_i2s_mode;
>> +extern struct pmx_mode caml_lcdw_mode;
>> +extern struct pmx_mode camu_lcd_mode;
>> +extern struct pmx_mode camu_wlcd_mode;
>> +extern struct pmx_mode caml_lcd_mode;
>> +
>> +
>> +struct pmx_dev pmx_gpio1 = {
>> + .name = "arm gpio1",
>> + .modes = pmx_gpio1_modes,
>> + .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
>> + .enb_on_reset = 1,
>> +};
>
> We have generalized pmx_dev in mode and mask attributes. Is it generic enough?
> What if we have several mux register in same mode?
>
This layer is spear specific and as far as our socs are concerned it is okay.
In later socs if we have something which doesn't suit this framework then we
can do minor modifications here with little effort.
>> +
>> +/* pmx driver structure */
>> +struct pmx_driver pmx_driver = {
>> + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
>> + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
>> +};
>
> We assume that all SoCs would either have a mode register or a mux register or
> both. Is this assumption generic enough. What if we have
> - more than 1 mux register
> - more than 1 mode register
> - may be a submode register in some new silicon.
Same as above.
>
>> +
>> + /* padmux initialization */
>> + pmx_driver.mode = &photo_frame_mode;
>> + pmx_driver.devs = pmx_devs;
>> + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
>> + spear300_pmx_init();
>
> Intializing pmx_driver and not using it directly obstructs readability.
> Better to pass pmx_driver and other info in spear300_pmx_init itself.
> What is your opinion?
>
Explained below.
>> +
>> + /* padmux initialization */
>> + pmx_driver.mode = NULL;
>> + pmx_driver.devs = pmx_devs;
>> + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
>> + spear310_pmx_init();
>
> I see your point in not passing pmx_driver here. It is due to initialization of
> pmx_driver.mux fields. This field is specific to mach so may not be defined in
> board file. Any other idea to overcome this little readability issue?
There are few things divided between mach and board. Now this situation will
always have some readability issue. I feel it is just fine.
>
>> + val = readl(pmx->base + pmx->mux_reg.offset);
>> + for (i = 0; i < count; i++) {
>> + u8 j = 0;
>> +
>> + if (!devs[i]->name || !devs[i]->modes) {
>> + printk(KERN_ERR "padmux: dev name or modes is null\n");
>> + continue;
>> + }
>> + /* check if peripheral exists in active mode */
>> + if (pmx->active_mode) {
>> + bool found = false;
>> + for (j = 0; j < devs[i]->mode_count; j++) {
>> + if (devs[i]->modes[j].ids &
>> + pmx->active_mode->id) {
>> + found = true;
>> + break;
>> + }
>> + }
>> + if (found == false) {
>> + printk(KERN_ERR "%s device not available in %s"\
>> + "mode\n", devs[i]->name,
>> + pmx->active_mode->name);
>> + continue;
>> + }
>> + }
>> +
>> + /* enable peripheral */
>> + mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
>
> Didn't understand this line.
>
Here we are preparing mask to be written for enabling a peripheral in a specific
mode. devs[i]->modes[j].mask will give mask of dev[i] for mode[j], this must be
& with valid mask of mux register.
regards,
viresh kumar
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 12/12] ST SPEAr: Adding gpio pad multiplexing support
2010-04-05 4:24 ` Viresh KUMAR
@ 2010-04-05 7:15 ` Shiraz HASHIM
0 siblings, 0 replies; 17+ messages in thread
From: Shiraz HASHIM @ 2010-04-05 7:15 UTC (permalink / raw)
To: linux-arm-kernel
Hello Viresh,
On 4/5/2010 9:54 AM, Viresh KUMAR wrote:
> On 4/3/2010 10:44 PM, Shiraz HASHIM wrote:
>>> /* Add spear3xx family function declarations here */
>>> +void __init clk_init(void);
>>> void __init spear3xx_map_io(void);
>>> void __init spear3xx_init_irq(void);
>>> void __init spear3xx_init(void);
>>> -void __init spear300_init(void);
>>> -void __init spear310_init(void);
>>> -void __init spear320_init(void);
>>> -void __init clk_init(void);
>>> +void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
>>>
>>> -/* Add spear300 machine device structure declarations here */
>>> +/* pad mux declarations */
>> These are spear300 soecific declarations, isn't it?
>
> No. I have added few spear3xx specific declarations here and moved spear300
> declarations later in the list.
OK
>>
>>> +#define PMX_FIRDA_MASK (1 << 14)
>>> +#define PMX_I2C_MASK (1 << 13)
>>> +#define PMX_SSP_CS_MASK (1 << 12)
>>> +#define PMX_SSP_MASK (1 << 11)
>>> +#define PMX_MII_MASK (1 << 10)
>>> +#define PMX_GPIO_PIN0_MASK (1 << 9)
>>> +#define PMX_GPIO_PIN1_MASK (1 << 8)
>>> +#define PMX_GPIO_PIN2_MASK (1 << 7)
>>> +#define PMX_GPIO_PIN3_MASK (1 << 6)
>>> +#define PMX_GPIO_PIN4_MASK (1 << 5)
>>> +#define PMX_GPIO_PIN5_MASK (1 << 4)
>>> +#define PMX_UART0_MODEM_MASK (1 << 3)
>>> +#define PMX_UART0_MASK (1 << 2)
>>> +#define PMX_TIMER_3_4_MASK (1 << 1)
>>> +#define PMX_TIMER_1_2_MASK (1 << 0)
>>> +
>>> +extern struct pmx_driver pmx_driver;
>>> +
>>> +/* spear300 declarations */
>>> #ifdef CONFIG_MACH_SPEAR300
>>
>> see above comment
>
> explained above
>>
>>> +/* Add spear300 machine device structure declarations here */
>>> extern struct amba_device gpio1_device;
>>> +
>>> +/* pad mux modes */
>>> +extern struct pmx_mode nand_mode;
>>> +extern struct pmx_mode nor_mode;
>>> +extern struct pmx_mode photo_frame_mode;
>>> +extern struct pmx_mode lend_ip_phone_mode;
>>> +extern struct pmx_mode hend_ip_phone_mode;
>>> +extern struct pmx_mode lend_wifi_phone_mode;
>>> +extern struct pmx_mode hend_wifi_phone_mode;
>>> +extern struct pmx_mode ata_pabx_wi2s_mode;
>>> +extern struct pmx_mode ata_pabx_i2s_mode;
>>> +extern struct pmx_mode caml_lcdw_mode;
>>> +extern struct pmx_mode camu_lcd_mode;
>>> +extern struct pmx_mode camu_wlcd_mode;
>>> +extern struct pmx_mode caml_lcd_mode;
>>> +
>>> +
>>> +struct pmx_dev pmx_gpio1 = {
>>> + .name = "arm gpio1",
>>> + .modes = pmx_gpio1_modes,
>>> + .mode_count = ARRAY_SIZE(pmx_gpio1_modes),
>>> + .enb_on_reset = 1,
>>> +};
>>
>> We have generalized pmx_dev in mode and mask attributes. Is it generic enough?
>> What if we have several mux register in same mode?
>>
>
> This layer is spear specific and as far as our socs are concerned it is okay.
> In later socs if we have something which doesn't suit this framework then we
> can do minor modifications here with little effort.
OK. I think it is fine.
>>> +
>>> +/* pmx driver structure */
>>> +struct pmx_driver pmx_driver = {
>>> + .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
>>> + .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
>>> +};
>>
>> We assume that all SoCs would either have a mode register or a mux register or
>> both. Is this assumption generic enough. What if we have
>> - more than 1 mux register
>> - more than 1 mode register
>> - may be a submode register in some new silicon.
>
> Same as above.
>
>>
>>> +
>>> + /* padmux initialization */
>>> + pmx_driver.mode = &photo_frame_mode;
>>> + pmx_driver.devs = pmx_devs;
>>> + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
>>> + spear300_pmx_init();
>>
>> Intializing pmx_driver and not using it directly obstructs readability.
>> Better to pass pmx_driver and other info in spear300_pmx_init itself.
>> What is your opinion?
>>
>
> Explained below.
>
>>> +
>>> + /* padmux initialization */
>>> + pmx_driver.mode = NULL;
>>> + pmx_driver.devs = pmx_devs;
>>> + pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
>>> + spear310_pmx_init();
>>
>> I see your point in not passing pmx_driver here. It is due to initialization of
>> pmx_driver.mux fields. This field is specific to mach so may not be defined in
>> board file. Any other idea to overcome this little readability issue?
>
> There are few things divided between mach and board. Now this situation will
> always have some readability issue. I feel it is just fine.
>
>>
>>> + val = readl(pmx->base + pmx->mux_reg.offset);
>>> + for (i = 0; i < count; i++) {
>>> + u8 j = 0;
>>> +
>>> + if (!devs[i]->name || !devs[i]->modes) {
>>> + printk(KERN_ERR "padmux: dev name or modes is null\n");
>>> + continue;
>>> + }
>>> + /* check if peripheral exists in active mode */
>>> + if (pmx->active_mode) {
>>> + bool found = false;
>>> + for (j = 0; j < devs[i]->mode_count; j++) {
>>> + if (devs[i]->modes[j].ids &
>>> + pmx->active_mode->id) {
>>> + found = true;
>>> + break;
>>> + }
>>> + }
>>> + if (found == false) {
>>> + printk(KERN_ERR "%s device not available in %s"\
>>> + "mode\n", devs[i]->name,
>>> + pmx->active_mode->name);
>>> + continue;
>>> + }
>>> + }
>>> +
>>> + /* enable peripheral */
>>> + mask = devs[i]->modes[j].mask & pmx->mux_reg.mask;
>>
>> Didn't understand this line.
>>
>
> Here we are preparing mask to be written for enabling a peripheral in a specific
> mode. devs[i]->modes[j].mask will give mask of dev[i] for mode[j], this must be
> & with valid mask of mux register.
OK. Understood.
regards
Shiraz
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines
2010-03-25 8:40 ` [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 06/12] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR
@ 2010-04-14 10:36 ` Russell King - ARM Linux
1 sibling, 0 replies; 17+ messages in thread
From: Russell King - ARM Linux @ 2010-04-14 10:36 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 25, 2010 at 02:10:48PM +0530, Viresh KUMAR wrote:
> Clock framework for SPEAr is based upon clkdev framework for ARM
>
> Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
> ---
> arch/arm/mach-spear3xx/clock.c | 389 +++++++++++++++++++++
> arch/arm/mach-spear3xx/include/mach/clkdev.h | 19 +
> arch/arm/mach-spear6xx/clock.c | 483 ++++++++++++++++++++++++++
> arch/arm/mach-spear6xx/include/mach/clkdev.h | 19 +
> arch/arm/plat-spear/clock.c | 435 +++++++++++++++++++++++
> arch/arm/plat-spear/include/plat/clkdev.h | 20 +
> arch/arm/plat-spear/include/plat/clock.h | 126 +++++++
> 7 files changed, 1491 insertions(+), 0 deletions(-)
> create mode 100755 arch/arm/mach-spear3xx/clock.c
> create mode 100644 arch/arm/mach-spear3xx/include/mach/clkdev.h
> create mode 100755 arch/arm/mach-spear6xx/clock.c
> create mode 100644 arch/arm/mach-spear6xx/include/mach/clkdev.h
> create mode 100755 arch/arm/plat-spear/clock.c
> create mode 100644 arch/arm/plat-spear/include/plat/clkdev.h
> create mode 100755 arch/arm/plat-spear/include/plat/clock.h
Please ensure that source files do not have the 'executable' bits set.
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2010-04-14 10:36 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-03-25 8:40 [PATCH V2 Resend 00/12] Adding Support for SPEAr Platform under ARM architecture Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 01/12] ST SPEAr: Added ARM PrimeXsys System Controller SP810 header file Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 02/12] ST SPEAr: Added basic header files for SPEAr3xx machine family Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 03/12] ST SPEAr: Added basic header files for SPEAr6xx " Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 04/12] ST SPEAr: Added basic header files for SPEAr platform Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 06/12] ST SPEAr: Added source files for SPEAr platform Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 07/12] ST SPEAr: Added source files for SPEAr3xx machine family Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 08/12] ST SPEAr: Added source files for SPEAr6xx " Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 09/12] ST SPEAr: Added support for SPEAr platform and machines in arch/arm/ Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 10/12] ST SPEAr: Added default configuration files for SPEAr machines Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 11/12] ST SPEAr: Updated Maintainers and added Documentation/arm/SPEAr Viresh KUMAR
2010-03-25 8:40 ` [PATCH V2 Resend 12/12] ST SPEAr: Adding gpio pad multiplexing support Viresh KUMAR
2010-04-03 17:14 ` Shiraz HASHIM
2010-04-05 4:24 ` Viresh KUMAR
2010-04-05 7:15 ` Shiraz HASHIM
2010-04-14 10:36 ` [PATCH V2 Resend 05/12] ST SPEAr: Added clock framework for SPEAr platform and machines Russell King - ARM Linux
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