From mboxrd@z Thu Jan  1 00:00:00 1970
From: gores@marvell.com (Siddarth Gore)
Date: Wed, 12 May 2010 15:26:21 +0530
Subject: L2 cache support for pxa16x
Message-ID: <1273658181.6926.27.camel@pe-dt434>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

Hi Eric/Haojian,

Can the Tauros2 support be used for pxa168 as well? The one difference I
can see is that L2 Enable is in control register instead of extra
feature register. But rest of the things look very similar to me.

-siddarth