[PATCH 0/2] Barrier changes with !ARM_DMA_MEM_BUFFERABLE

[PATCH 0/2] Barrier changes with !ARM_DMA_MEM_BUFFERABLE

[Catalin Marinas]

The patches are relatively simple but without them the RealView boards
cannot be used with L210/L220 enabled (hardware deadlock, not a software
issue).

Catalin Marinas (2):
      ARM: Do not use outer_sync() in mb() if !ARM_DMA_MEM_BUFFERABLE
      ARM: Do not enable ARM_DMA_MEM_BUFFERABLE for some RealView boards


 arch/arm/include/asm/system.h |    6 +++++-
 arch/arm/mm/Kconfig           |    2 ++
 2 files changed, 7 insertions(+), 1 deletions(-)

-- 
Catalin

[PATCH 1/2] ARM: Do not use outer_sync() in mb() if !ARM_DMA_MEM_BUFFERABLE

[Catalin Marinas]

This patch changes the mb() barrier implementation for the
!ARM_DMA_MEM_BUFFERABLE case so that it no longer performs an outer
cache sync. When this is option is disabled, the coherent DMA buffers
are mapped as Strongly Ordered and there is no need for an L2 cache
sync.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/include/asm/system.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f480..3b2abcf 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -141,10 +141,14 @@ extern unsigned int user_debug;
 
 #ifdef CONFIG_ARCH_HAS_BARRIERS
 #include <mach/barriers.h>
-#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE)
 #define mb()		do { dsb(); outer_sync(); } while (0)
 #define rmb()		dmb()
 #define wmb()		mb()
+#elif defined(CONFIG_SMP)
+#define mb()		dsb()
+#define rmb()		dmb()
+#define wmb()		mb()
 #else
 #define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)

[PATCH 2/2] ARM: Do not enable ARM_DMA_MEM_BUFFERABLE for some RealView boards

[Catalin Marinas]

RealView boards with certain revisions of the L210/L220 cache controller
may have issues with recent changes to the mb() barrier implementation
(DSB followed by an L2 cache sync). The patch disables
ARM_DMA_MEM_BUFFERABLE for some of the RealView boards with L210/L220.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/mm/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index fc1b2fa..101105e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,6 +813,8 @@ config ARM_L1_CACHE_SHIFT
 
 config ARM_DMA_MEM_BUFFERABLE
 	bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+		     MACH_REALVIEW_PB11MP)
 	default y if CPU_V6 || CPU_V7
 	help
 	  Historically, the kernel has used strongly ordered mappings to

[PATCH 0/2] Barrier changes with !ARM_DMA_MEM_BUFFERABLE

[Catalin Marinas]

Russell,

On Mon, 2010-06-21 at 13:23 +0100, Catalin Marinas wrote:
> The patches are relatively simple but without them the RealView boards
> cannot be used with L210/L220 enabled (hardware deadlock, not a software
> issue).
> 
> Catalin Marinas (2):
>       ARM: Do not use outer_sync() in mb() if !ARM_DMA_MEM_BUFFERABLE
>       ARM: Do not enable ARM_DMA_MEM_BUFFERABLE for some RealView boards

Are you ok with these patches, especially the first one?

Alternatively, I can implement the barriers in the RealView code (though
the second patch is still needed as I'll drop the outer_sync() for ARMv6
RealView).

Thanks.

-- 
Catalin