[PATCH 0/5] arm/versatile: generalize PCI code

[PATCH 0/5] arm/versatile: generalize PCI code

[Arnd Bergmann]

In oder to make the PCI code in the versatile platform more
useful, I'm proposing this set of patches, which enables
using Virtio and other PCI devices including those that
require I/O space mappings to work on the versatile-pb,
realview-eb and realview-pb1176 boards.

Because of lack of actual hardware, I have only tested
this in qemu, so I would appreciate someone trying the
patches on actual hardware.

Arnd Bergmann (5):
  arm/versatile: move pci code to plat-versatile
  arm/versatile: boot-time configure xilinx-pci
  arm/versatile: enable PCI I/O space
  arm/realview: enable PCI for realview-eb and realview-pb1176
  arm: Enable support for virtio

 arch/arm/Kconfig                                  |    9 +-
 arch/arm/mach-realview/Kconfig                    |    2 +
 arch/arm/mach-realview/include/mach/hardware.h    |   14 +-
 arch/arm/mach-realview/include/mach/io.h          |    6 +-
 arch/arm/mach-realview/include/mach/platform.h    |   23 +-
 arch/arm/mach-realview/realview_eb.c              |   70 ++++-
 arch/arm/mach-realview/realview_pb1176.c          |   68 ++++
 arch/arm/mach-versatile/Kconfig                   |    1 +
 arch/arm/mach-versatile/Makefile                  |    1 -
 arch/arm/mach-versatile/core.c                    |   19 +-
 arch/arm/mach-versatile/include/mach/hardware.h   |   24 +-
 arch/arm/mach-versatile/include/mach/io.h         |    6 +-
 arch/arm/mach-versatile/include/mach/platform.h   |    4 +-
 arch/arm/mach-versatile/pci.c                     |  361 ---------------------
 arch/arm/mach-versatile/versatile_pb.c            |   47 +++
 arch/arm/plat-versatile/Makefile                  |    1 +
 arch/arm/plat-versatile/include/plat/xilinx-pci.h |   24 ++
 arch/arm/plat-versatile/xilinx-pci.c              |  344 ++++++++++++++++++++
 18 files changed, 611 insertions(+), 413 deletions(-)
 delete mode 100644 arch/arm/mach-versatile/pci.c
 create mode 100644 arch/arm/plat-versatile/include/plat/xilinx-pci.h
 create mode 100644 arch/arm/plat-versatile/xilinx-pci.c

[PATCH 1/5] arm/versatile: move pci code to plat-versatile

[Arnd Bergmann]

The Xilinx PCI macro is used on both versatile-pb and
realview-eb, so we should move the implementation to place
where it can be shared.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/Kconfig                                   |    5 +++++
 arch/arm/mach-versatile/Makefile                   |    1 -
 arch/arm/plat-versatile/Makefile                   |    1 +
 .../pci.c => plat-versatile/xilinx-pci.c}          |    0
 4 files changed, 6 insertions(+), 1 deletions(-)
 rename arch/arm/{mach-versatile/pci.c => plat-versatile/xilinx-pci.c} (100%)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7b117b1..ddbcaf2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1086,6 +1086,11 @@ config PCI_HOST_ITE8152
 	default y
 	select DMABOUNCE
 
+config PCI_HOST_XILINX
+	bool
+	depends on PCI && (ARCH_VERSATILE_PB || MACH_REALVIEW_EB || MACH_REALVIEW_PB1176)
+	default y
+
 source "drivers/pci/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 97cf4d8..191b65b 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -5,4 +5,3 @@
 obj-y					:= core.o
 obj-$(CONFIG_ARCH_VERSATILE_PB)		+= versatile_pb.o
 obj-$(CONFIG_MACH_VERSATILE_AB)		+= versatile_ab.o
-obj-$(CONFIG_PCI)			+= pci.o
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index 5cf88e8..de870b7 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -6,3 +6,4 @@ ifeq ($(CONFIG_LEDS_CLASS),y)
 obj-$(CONFIG_ARCH_REALVIEW) += leds.o
 obj-$(CONFIG_ARCH_VERSATILE) += leds.o
 endif
+obj-$(CONFIG_PCI_HOST_XILINX) += xilinx-pci.o
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/plat-versatile/xilinx-pci.c
similarity index 100%
rename from arch/arm/mach-versatile/pci.c
rename to arch/arm/plat-versatile/xilinx-pci.c
-- 
1.7.1

[PATCH 2/5] arm/versatile: boot-time configure xilinx-pci

[Arnd Bergmann]

The Xilinx-pci code is currently hardcoded to the registers
used on the versatile-pb platform. Make all dependencies on
specific register locations set at boot time so we can use
the same code on realview.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/mach-versatile/versatile_pb.c            |   47 ++++++
 arch/arm/plat-versatile/include/plat/xilinx-pci.h |   24 +++
 arch/arm/plat-versatile/xilinx-pci.c              |  183 +++++++++------------
 3 files changed, 146 insertions(+), 108 deletions(-)
 create mode 100644 arch/arm/plat-versatile/include/plat/xilinx-pci.h

diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 239cd30..c73abde 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -28,6 +28,8 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <plat/xilinx-pci.h>
+
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
@@ -94,6 +96,49 @@ static struct amba_device *amba_devs[] __initdata = {
 	&mmc1_device,
 };
 
+#ifdef CONFIG_PCI_HOST_XILINX
+/*
+ * these spaces are mapped using the following base registers:
+ *
+ * Usage Local Bus Memory         Base/Map registers used
+ *
+ * Mem   44000000 - 4FFFFFFF      LB_BASE0/LB_MAP0,  unused
+ * Mem   50000000 - 5FFFFFFF      LB_BASE1/LB_MAP1,  non prefetch
+ * Mem   60000000 - 6FFFFFFF      LB_BASE2/LB_MAP2,  prefetch
+ * IO    43000000 - 43FFFFFF      IO space
+ * Cfg   42000000 - 42FFFFFF	  PCI config
+ *
+ */
+#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
+static struct xilinx_pci_data versatile_pci_io = {
+	.base		= VERSATILE_PCI_VIRT_BASE,
+	.cfg_base	= VERSATILE_PCI_CFG_VIRT_BASE,
+	.io_base	= NULL,
+	.sys_pcictl	= __IO_ADDRESS(VERSATILE_SYS_PCICTL),
+	.core_base	= __IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
+	.base_irq	= 27,
+
+	.mem_spaces	= {
+		{
+			.name	= "PCI",
+			.start	= VERSATILE_PCI_MEM_BASE0,
+			.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
+			.flags	= IORESOURCE_IO,
+		}, {
+			.name	= "PCI non-prefetchable",
+			.start	= VERSATILE_PCI_MEM_BASE1,
+			.end	= VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
+			.flags	= IORESOURCE_MEM,
+		}, {
+			.name	= "PCI prefetchable",
+			.start	= VERSATILE_PCI_MEM_BASE2,
+			.end	= VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
+			.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
+		},
+	},
+};
+#endif
+
 static void __init versatile_pb_init(void)
 {
 	int i;
@@ -104,6 +149,8 @@ static void __init versatile_pb_init(void)
 		struct amba_device *d = amba_devs[i];
 		amba_device_register(d, &iomem_resource);
 	}
+
+	xilinx_pci_init(&versatile_pci_io);
 }
 
 MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
diff --git a/arch/arm/plat-versatile/include/plat/xilinx-pci.h b/arch/arm/plat-versatile/include/plat/xilinx-pci.h
new file mode 100644
index 0000000..251eed6
--- /dev/null
+++ b/arch/arm/plat-versatile/include/plat/xilinx-pci.h
@@ -0,0 +1,24 @@
+#ifndef _PLAT_VERSATILE_XILINX_PCI_H
+#define _PLAT_VERSATILE_XILINX_PCI_H
+
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+
+struct xilinx_pci_data {
+	void __iomem *sys_pcictl;
+	void __iomem *base;
+	void __iomem *core_base;
+	void __iomem *cfg_base;
+	void __iomem *io_base;
+	int base_irq;
+
+	struct resource mem_spaces[3];
+};
+
+#ifdef CONFIG_PCI_HOST_XILINX
+extern int __init xilinx_pci_init(struct xilinx_pci_data *x);
+#else
+#define xilinx_pci_init(x) do { } while (0)
+#endif
+
+#endif
diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
index 13c7e5f..1106b84 100644
--- a/arch/arm/plat-versatile/xilinx-pci.c
+++ b/arch/arm/plat-versatile/xilinx-pci.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mach-versatile/pci.c
+ *  linux/arch/arm/plat-versatile/pci.c
  *
  * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
  * You can redistribute and/or modify this software under the terms of version 2
@@ -27,37 +27,31 @@
 #include <asm/system.h>
 #include <asm/mach/pci.h>
 
-/*
- * these spaces are mapped using the following base registers:
- *
- * Usage Local Bus Memory         Base/Map registers used
- *
- * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0,  non prefetch
- * Mem   60000000 - 6FFFFFFF      LB_BASE1/LB_MAP1,  prefetch
- * IO    44000000 - 4FFFFFFF      LB_BASE2/LB_MAP2,  IO
- * Cfg   42000000 - 42FFFFFF	  PCI config
- *
- */
-#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
-#define SYS_PCICTL		__IO_ADDRESS(VERSATILE_SYS_PCICTL)
-#define PCI_IMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
-#define PCI_IMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
-#define PCI_IMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
-#define PCI_SMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
-#define PCI_SMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
-#define PCI_SMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
-#define PCI_SELFID		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
-
-#define DEVICE_ID_OFFSET		0x00
-#define CSR_OFFSET			0x04
-#define CLASS_ID_OFFSET			0x08
-
-#define VP_PCI_DEVICE_ID		0x030010ee
-#define VP_PCI_CLASS_ID			0x0b400000
+#include <plat/xilinx-pci.h>
+
+static struct xilinx_pci_data *xilinx_pci;
+
+#define XILINX_PCI_VIRT_BASE	(xilinx_pci->base)
+#define XILINX_PCI_CFG_VIRT_BASE (xilinx_pci->cfg_base)
+#define SYS_PCICTL		(xilinx_pci->sys_pcictl)
+#define PCI_IMAP0		(xilinx_pci->core_base+0x0)
+#define PCI_IMAP1		(xilinx_pci->core_base+0x4)
+#define PCI_IMAP2		(xilinx_pci->core_base+0x8)
+#define PCI_SMAP0		(xilinx_pci->core_base+0x10)
+#define PCI_SMAP1		(xilinx_pci->core_base+0x14)
+#define PCI_SMAP2		(xilinx_pci->core_base+0x18)
+#define PCI_SELFID		(xilinx_pci->core_base+0xc)
+
+#define DEVICE_ID_OFFSET	0x00
+#define CSR_OFFSET		0x04
+#define CLASS_ID_OFFSET		0x08
+
+#define VP_PCI_DEVICE_ID	0x030010ee
+#define VP_PCI_CLASS_ID		0x0b400000
 
 static unsigned long pci_slot_ignore = 0;
 
-static int __init versatile_pci_slot_ignore(char *str)
+static int __init xilinx_pci_slot_ignore(char *str)
 {
 	int retval;
 	int slot;
@@ -72,7 +66,7 @@ static int __init versatile_pci_slot_ignore(char *str)
 	return 1;
 }
 
-__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
+__setup("pci_slot_ignore=", xilinx_pci_slot_ignore);
 
 
 static void __iomem *__pci_addr(struct pci_bus *bus,
@@ -90,11 +84,11 @@ static void __iomem *__pci_addr(struct pci_bus *bus,
 	if (devfn > 255)
 		BUG();
 
-	return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
+	return XILINX_PCI_CFG_VIRT_BASE + ((busnr << 16) |
 		(PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
 }
 
-static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
+static int xilinx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 				 int size, u32 *val)
 {
 	void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
@@ -138,7 +132,7 @@ static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int wh
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
+static int xilinx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
 				  int size, u32 val)
 {
 	void __iomem *addr = __pci_addr(bus, devfn, where);
@@ -165,75 +159,48 @@ static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int w
 	return PCIBIOS_SUCCESSFUL;
 }
 
-static struct pci_ops pci_versatile_ops = {
-	.read	= versatile_read_config,
-	.write	= versatile_write_config,
-};
-
-static struct resource io_mem = {
-	.name	= "PCI I/O space",
-	.start	= VERSATILE_PCI_MEM_BASE0,
-	.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
-	.flags	= IORESOURCE_IO,
-};
-
-static struct resource non_mem = {
-	.name	= "PCI non-prefetchable",
-	.start	= VERSATILE_PCI_MEM_BASE1,
-	.end	= VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
-	.flags	= IORESOURCE_MEM,
+static struct pci_ops pci_xilinx_ops = {
+	.read	= xilinx_read_config,
+	.write	= xilinx_write_config,
 };
 
-static struct resource pre_mem = {
-	.name	= "PCI prefetchable",
-	.start	= VERSATILE_PCI_MEM_BASE2,
-	.end	= VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
-	.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
-};
-
-static int __init pci_versatile_setup_resources(struct resource **resource)
+static int __init pci_xilinx_setup_resources(struct resource **resource)
 {
 	int ret = 0;
-
-	ret = request_resource(&iomem_resource, &io_mem);
-	if (ret) {
-		printk(KERN_ERR "PCI: unable to allocate I/O "
-		       "memory region (%d)\n", ret);
-		goto out;
-	}
-	ret = request_resource(&iomem_resource, &non_mem);
-	if (ret) {
-		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
-		       "memory region (%d)\n", ret);
-		goto release_io_mem;
-	}
-	ret = request_resource(&iomem_resource, &pre_mem);
-	if (ret) {
-		printk(KERN_ERR "PCI: unable to allocate prefetchable "
-		       "memory region (%d)\n", ret);
-		goto release_non_mem;
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		ret = request_resource(&iomem_resource,
+					&xilinx_pci->mem_spaces[i]);
+		if (ret) {
+			printk(KERN_ERR "PCI: unable to allocate memory "
+				"region %d\n", i);
+			goto out_release;
+		}
 	}
-
 	/*
 	 * bus->resource[0] is the IO resource for this bus
 	 * bus->resource[1] is the mem resource for this bus
 	 * bus->resource[2] is the prefetch mem resource for this bus
 	 */
-	resource[0] = &io_mem;
-	resource[1] = &non_mem;
-	resource[2] = &pre_mem;
-
+	resource[0] = &xilinx_pci->mem_spaces[0];
+	resource[1] = &xilinx_pci->mem_spaces[1];
+	resource[2] = &xilinx_pci->mem_spaces[2];
 	goto out;
 
- release_non_mem:
-	release_resource(&non_mem);
- release_io_mem:
-	release_resource(&io_mem);
+ out_release:
+	switch(i) {
+	case 2:
+		release_resource(&xilinx_pci->mem_spaces[1]);
+	case 1:
+		release_resource(&xilinx_pci->mem_spaces[0]);
+		break;
+	}
  out:
 	return ret;
 }
 
-int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
+int __init pci_xilinx_setup(int nr, struct pci_sys_data *sys)
 {
 	int ret = 0;
         int i;
@@ -250,13 +217,13 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 
 	if (nr == 0) {
 		sys->mem_offset = 0;
-		ret = pci_versatile_setup_resources(sys->resource);
+		ret = pci_xilinx_setup_resources(sys->resource);
 		if (ret < 0) {
-			printk("pci_versatile_setup: resources... oops?\n");
+			printk("pci_xilinx_setup: resources... oops?\n");
 			goto out;
 		}
 	} else {
-		printk("pci_versatile_setup: resources... nr == 0??\n");
+		printk("pci_xilinx_setup: resources... nr == 0??\n");
 		goto out;
 	}
 
@@ -265,8 +232,8 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 	 *  before the main PCI probing is performed
 	 */
 	for (i=0; i<32; i++)
-		if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
-		    (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
+		if ((__raw_readl(XILINX_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
+		    (__raw_readl(XILINX_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
 			myslot = i;
 			break;
 		}
@@ -280,7 +247,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 	printk("PCI core found (slot %d)\n",myslot);
 
 	__raw_writel(myslot, PCI_SELFID);
-	local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
+	local_pci_cfg_base = XILINX_PCI_CFG_VIRT_BASE + (myslot << 11);
 
 	val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
 	val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
@@ -304,16 +271,16 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 }
 
 
-struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
+struct pci_bus * __init pci_xilinx_scan_bus(int nr, struct pci_sys_data *sys)
 {
-	return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
+	return pci_scan_bus(sys->busnr, &pci_xilinx_ops, sys);
 }
 
-void __init pci_versatile_preinit(void)
+void __init pci_xilinx_preinit(void)
 {
-	__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
-	__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
-	__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
+	__raw_writel(xilinx_pci->mem_spaces[0].start >> 28, PCI_IMAP0);
+	__raw_writel(xilinx_pci->mem_spaces[1].start >> 28, PCI_IMAP1);
+	__raw_writel(xilinx_pci->mem_spaces[2].start >> 28, PCI_IMAP2);
 
 	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
 	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
@@ -325,7 +292,7 @@ void __init pci_versatile_preinit(void)
 /*
  * map the specified device/slot/pin to an IRQ.   Different backplanes may need to modify this.
  */
-static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+static int __init xilinx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
 	int irq;
 	int devslot = PCI_SLOT(dev->devfn);
@@ -336,26 +303,26 @@ static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 	 *  26     1     29
 	 *  27     1     30
 	 */
-	irq = 27 + ((slot + pin - 1) & 3);
+	irq = xilinx_pci->base_irq + ((slot + pin - 1) & 3);
 
 	printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
 
 	return irq;
 }
 
-static struct hw_pci versatile_pci __initdata = {
+static struct hw_pci xilinx_hw_pci __initdata = {
 	.swizzle		= NULL,
-	.map_irq		= versatile_map_irq,
+	.map_irq		= xilinx_map_irq,
 	.nr_controllers		= 1,
-	.setup			= pci_versatile_setup,
-	.scan			= pci_versatile_scan_bus,
-	.preinit		= pci_versatile_preinit,
+	.setup			= pci_xilinx_setup,
+	.scan			= pci_xilinx_scan_bus,
+	.preinit		= pci_xilinx_preinit,
 };
 
-static int __init versatile_pci_init(void)
+int __init xilinx_pci_init(struct xilinx_pci_data *x)
 {
-	pci_common_init(&versatile_pci);
+	xilinx_pci = x;
+	pci_common_init(&xilinx_hw_pci);
 	return 0;
 }
 
-subsys_initcall(versatile_pci_init);
-- 
1.7.1

[PATCH 3/5] arm/versatile: enable PCI I/O space

[Arnd Bergmann]

I/O space handling on the versatile platform is currently
broken in multiple ways. Most importantly, the ports do
not get mapped into the virtual address space at all.

Also, there is some amount of confusion between PCI I/O
space and other statically mapped MMIO registers in the
platform code:

* The __io_address() macro that is used to access the
  platform register maps to the same __io macro that gets
  used for I/O space.

* The IO_SPACE_LIMIT is set to a value that is much larger
  than the total available space.

* The I/O resource of the PCI bus is set to the physical
  address of the mapping, which is way outside of the
  actual I/O space limit as well as the address range that
  gets decoded by traditional PCI cards.

* No attempt is made to stay outside of the ISA port range
  that some device drivers try access.

* No resource gets requested as a child of ioport_resource,
  but an IORESOURCE_IO type mapping gets requested
  as a child of iomem_resource.

This patch attempts to correct all of the above. This makes
it possible to use virtio-pci based virtual devices as well
as actual PCI cards including those with legacy ISA port
ranges like VGA.

Some of the issues seem to be duplicated on other platforms.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/mach-versatile/core.c                  |   19 ++---------------
 arch/arm/mach-versatile/include/mach/hardware.h |   24 ++++++----------------
 arch/arm/mach-versatile/include/mach/io.h       |    6 +++-
 arch/arm/mach-versatile/include/mach/platform.h |    4 ++-
 arch/arm/mach-versatile/versatile_pb.c          |    4 +-
 arch/arm/plat-versatile/xilinx-pci.c            |   19 ++++++++++++++++-
 6 files changed, 36 insertions(+), 40 deletions(-)

diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 6ccd261..e47efcf 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -201,26 +201,13 @@ static struct map_desc versatile_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 		.length		= VERSATILE_PCI_CFG_BASE_SIZE,
 		.type		= MT_DEVICE
-	},
-#if 0
- 	{
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE0,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
-		.length		= SZ_16M,
-		.type		= MT_DEVICE
 	}, {
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE1,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
-		.length		= SZ_16M,
-		.type		= MT_DEVICE
-	}, {
-		.virtual	=  VERSATILE_PCI_VIRT_MEM_BASE2,
-		.pfn		= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
-		.length		= SZ_16M,
+		.virtual	=  (unsigned long)PCIO_BASE,
+		.pfn		= __phys_to_pfn(VERSATILE_PCI_IO_BASE),
+		.length		= IO_SPACE_LIMIT,
 		.type		= MT_DEVICE
 	},
 #endif
-#endif
 };
 
 void __init versatile_map_io(void)
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index 4f8f99a..59b7716 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -24,30 +24,20 @@
 
 #include <asm/sizes.h>
 
+/* macro to get at MMIO space when running virtually */
+#define IO_ADDRESS(x)		(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+#define __io_address(n)		((void __iomem *)(IO_ADDRESS(n)))
+
 /*
  * PCI space virtual addresses
  */
 #define VERSATILE_PCI_VIRT_BASE		(void __iomem *)0xe8000000ul
 #define VERSATILE_PCI_CFG_VIRT_BASE	(void __iomem *)0xe9000000ul
+#define VERSATILE_PCI_IO_VIRT_BASE	(void __iomem *)PCIO_BASE
 
-#if 0
-#define VERSATILE_PCI_VIRT_MEM_BASE0	0xf4000000
-#define VERSATILE_PCI_VIRT_MEM_BASE1	0xf5000000
-#define VERSATILE_PCI_VIRT_MEM_BASE2	0xf6000000
-
-#define PCIO_BASE			VERSATILE_PCI_VIRT_MEM_BASE0
-#define PCIMEM_BASE			VERSATILE_PCI_VIRT_MEM_BASE1
-#endif
-
-/* CIK guesswork */
-#define PCIBIOS_MIN_IO			0x44000000
-#define PCIBIOS_MIN_MEM			0x50000000
+#define PCIBIOS_MIN_IO			0x00001000
+#define PCIBIOS_MIN_MEM			0x00000000
 
 #define pcibios_assign_all_busses()     1
 
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x)		(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
-
-#define __io_address(n)		__io(IO_ADDRESS(n))
-
 #endif
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
index f067c14..4f1f61b 100644
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ b/arch/arm/mach-versatile/include/mach/io.h
@@ -20,9 +20,11 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#define PCIO_BASE	(void __iomem *)0xeb000000ul
+#define PCIO_SIZE	0x00100000ul
+#define IO_SPACE_LIMIT  (PCIO_SIZE - 1)
 
-#define __io(a)		__typesafe_io(a)
+#define __io(a)		(a + PCIO_BASE)
 #define __mem_pci(a)	(a)
 
 #endif
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
index ec08740..efb5328 100644
--- a/arch/arm/mach-versatile/include/mach/platform.h
+++ b/arch/arm/mach-versatile/include/mach/platform.h
@@ -231,12 +231,14 @@
 /* PCI space */
 #define VERSATILE_PCI_BASE             0x41000000	/* PCI Interface */
 #define VERSATILE_PCI_CFG_BASE	       0x42000000
+#define VERSATILE_PCI_IO_BASE	       0x43000000
 #define VERSATILE_PCI_MEM_BASE0        0x44000000
 #define VERSATILE_PCI_MEM_BASE1        0x50000000
 #define VERSATILE_PCI_MEM_BASE2        0x60000000
 /* Sizes of above maps */
 #define VERSATILE_PCI_BASE_SIZE	       0x01000000
-#define VERSATILE_PCI_CFG_BASE_SIZE    0x02000000
+#define VERSATILE_PCI_CFG_BASE_SIZE    0x01000000
+#define VERSATILE_PCI_IO_BASE_SIZE     0x01000000
 #define VERSATILE_PCI_MEM_BASE0_SIZE   0x0c000000	/* 32Mb */
 #define VERSATILE_PCI_MEM_BASE1_SIZE   0x10000000	/* 256Mb */
 #define VERSATILE_PCI_MEM_BASE2_SIZE   0x10000000	/* 256Mb */
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index c73abde..1d2ee26 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -113,7 +113,7 @@ static struct amba_device *amba_devs[] __initdata = {
 static struct xilinx_pci_data versatile_pci_io = {
 	.base		= VERSATILE_PCI_VIRT_BASE,
 	.cfg_base	= VERSATILE_PCI_CFG_VIRT_BASE,
-	.io_base	= NULL,
+	.io_base	= PCIO_BASE,
 	.sys_pcictl	= __IO_ADDRESS(VERSATILE_SYS_PCICTL),
 	.core_base	= __IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 	.base_irq	= 27,
@@ -123,7 +123,7 @@ static struct xilinx_pci_data versatile_pci_io = {
 			.name	= "PCI",
 			.start	= VERSATILE_PCI_MEM_BASE0,
 			.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
-			.flags	= IORESOURCE_IO,
+			.flags	= IORESOURCE_MEM,
 		}, {
 			.name	= "PCI non-prefetchable",
 			.start	= VERSATILE_PCI_MEM_BASE1,
diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
index 1106b84..077d24a 100644
--- a/arch/arm/plat-versatile/xilinx-pci.c
+++ b/arch/arm/plat-versatile/xilinx-pci.c
@@ -164,11 +164,25 @@ static struct pci_ops pci_xilinx_ops = {
 	.write	= xilinx_write_config,
 };
 
+static struct resource io_port = {
+	.name	= "PCI",
+	.start	= 0,
+	.end	= IO_SPACE_LIMIT,
+	.flags	= IORESOURCE_IO,
+};
+
 static int __init pci_xilinx_setup_resources(struct resource **resource)
 {
 	int ret = 0;
 	int i;
 
+	ret = request_resource(&ioport_resource, &io_port);
+	if (ret) {
+		printk(KERN_ERR "PCI: unable to allocate I/O "
+		       "port region (%d)\n", ret);
+		goto out;
+	}
+
 	for (i = 0; i < 3; i++) {
 		ret = request_resource(&iomem_resource,
 					&xilinx_pci->mem_spaces[i]);
@@ -183,7 +197,7 @@ static int __init pci_xilinx_setup_resources(struct resource **resource)
 	 * bus->resource[1] is the mem resource for this bus
 	 * bus->resource[2] is the prefetch mem resource for this bus
 	 */
-	resource[0] = &xilinx_pci->mem_spaces[0];
+	resource[0] = &io_port;
 	resource[1] = &xilinx_pci->mem_spaces[1];
 	resource[2] = &xilinx_pci->mem_spaces[2];
 	goto out;
@@ -194,6 +208,8 @@ static int __init pci_xilinx_setup_resources(struct resource **resource)
 		release_resource(&xilinx_pci->mem_spaces[1]);
 	case 1:
 		release_resource(&xilinx_pci->mem_spaces[0]);
+	case 0:
+		release_resource(&io_port);
 		break;
 	}
  out:
@@ -325,4 +341,3 @@ int __init xilinx_pci_init(struct xilinx_pci_data *x)
 	pci_common_init(&xilinx_hw_pci);
 	return 0;
 }
-
-- 
1.7.1

[PATCH 4/5] arm/realview: enable PCI for realview-eb and realview-pb1176

[Arnd Bergmann]

These two boards use the Xilinx PCI macro, so enable the
code and set up all the I/O windows for it.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/Kconfig                               |    2 +-
 arch/arm/mach-realview/include/mach/hardware.h |   14 +++++-
 arch/arm/mach-realview/include/mach/io.h       |    6 ++-
 arch/arm/mach-realview/include/mach/platform.h |   23 +++++----
 arch/arm/mach-realview/realview_eb.c           |   70 +++++++++++++++++++++++-
 arch/arm/mach-realview/realview_pb1176.c       |   68 +++++++++++++++++++++++
 arch/arm/plat-versatile/xilinx-pci.c           |    1 +
 7 files changed, 169 insertions(+), 15 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ddbcaf2..dd452ee 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1060,7 +1060,7 @@ config ISA_DMA_API
 	bool
 
 config PCI
-	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_REALVIEW
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
 	  bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
index 8a638d1..ff60011 100644
--- a/arch/arm/mach-realview/include/mach/hardware.h
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -37,6 +37,18 @@
 #else
 #define IO_ADDRESS(x)		(x)
 #endif
-#define __io_address(n)		__io(IO_ADDRESS(n))
+#define __io_address(n)		((void __iomem *)(IO_ADDRESS(n)))
+
+/*
+ * PCI space virtual addresses
+ */
+#define REALVIEW_PCI_VIRT_BASE		(void __iomem *)0xf8000000ul
+#define REALVIEW_PCI_CFG_VIRT_BASE	(void __iomem *)0xf9000000ul
+#define REALVIEW_PCI_IO_VIRT_BASE	(void __iomem *)PCIO_BASE
+
+#define PCIBIOS_MIN_IO			0x00001000
+#define PCIBIOS_MIN_MEM			0x00000000
+
+#define pcibios_assign_all_busses()     1
 
 #endif
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
index f05bcdf..4fcb187 100644
--- a/arch/arm/mach-realview/include/mach/io.h
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -20,9 +20,11 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
+#define PCIO_BASE	(void __iomem *)0xfa000000ul
+#define PCIO_SIZE	0x00100000ul
+#define IO_SPACE_LIMIT  (PCIO_SIZE - 1)
 
-#define __io(a)		__typesafe_io(a)
+#define __io(a)		(a + PCIO_BASE)
 #define __mem_pci(a)	(a)
 
 #endif
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
index 1b77a27..f5a777b 100644
--- a/arch/arm/mach-realview/include/mach/platform.h
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -172,20 +172,23 @@
 #define REALVIEW_GPIO1_BASE           0x10014000	/* GPIO port 1 */
 #define REALVIEW_GPIO2_BASE           0x10015000	/* GPIO port 2 */
 #define REALVIEW_DMC_BASE             0x10018000	/* DMC configuration */
+#define REALVIEW_PCI_CORE_BASE	      0x10019000	/* PCI map and control */
 #define REALVIEW_DMAC_BASE            0x10030000	/* DMA controller */
 
 /* PCI space */
-#define REALVIEW_PCI_BASE             0x41000000	/* PCI Interface */
-#define REALVIEW_PCI_CFG_BASE	      0x42000000
-#define REALVIEW_PCI_MEM_BASE0        0x44000000
-#define REALVIEW_PCI_MEM_BASE1        0x50000000
-#define REALVIEW_PCI_MEM_BASE2        0x60000000
+#define REALVIEW_PCI_BASE             0x61000000	/* PCI Interface */
+#define REALVIEW_PCI_CFG_BASE	      0x62000000
+#define REALVIEW_PCI_IO_BASE	      0x63000000
+#define REALVIEW_PCI_MEM_BASE0        0x64000000
+#define REALVIEW_PCI_MEM_BASE1        0x68000000
+#define REALVIEW_PCI_MEM_BASE2        0x6C000000
 /* Sizes of above maps */
-#define REALVIEW_PCI_BASE_SIZE	       0x01000000
-#define REALVIEW_PCI_CFG_BASE_SIZE    0x02000000
-#define REALVIEW_PCI_MEM_BASE0_SIZE   0x0c000000	/* 32Mb */
-#define REALVIEW_PCI_MEM_BASE1_SIZE   0x10000000	/* 256Mb */
-#define REALVIEW_PCI_MEM_BASE2_SIZE   0x10000000	/* 256Mb */
+#define REALVIEW_PCI_BASE_SIZE	      0x01000000
+#define REALVIEW_PCI_CFG_BASE_SIZE    0x01000000
+#define REALVIEW_PCI_IO_BASE_SIZE     0x01000000
+#define REALVIEW_PCI_MEM_BASE0_SIZE   0x04000000	/* 64Mb */
+#define REALVIEW_PCI_MEM_BASE1_SIZE   0x04000000	/* 64Mb */
+#define REALVIEW_PCI_MEM_BASE2_SIZE   0x04000000	/* 64Mb */
 
 #define REALVIEW_SDRAM67_BASE         0x70000000	/* SDRAM banks 6 and 7 */
 #define REALVIEW_LT_BASE              0x80000000	/* Logic Tile expansion */
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 991c1f8..7e59eae 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -44,6 +44,7 @@
 
 #include <mach/board-eb.h>
 #include <mach/irqs.h>
+#include <plat/xilinx-pci.h>
 
 #include "core.h"
 
@@ -85,7 +86,30 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(REALVIEW_EB_UART0_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
-	}
+	},
+#endif
+#ifdef CONFIG_PCI
+	{
+		.virtual	= IO_ADDRESS(REALVIEW_PCI_CORE_BASE),
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_CORE_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)REALVIEW_PCI_VIRT_BASE,
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_BASE),
+		.length		= REALVIEW_PCI_BASE_SIZE,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)REALVIEW_PCI_CFG_VIRT_BASE,
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_CFG_BASE),
+		.length		= REALVIEW_PCI_CFG_BASE_SIZE,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)REALVIEW_PCI_IO_VIRT_BASE,
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_IO_BASE),
+		.length		= REALVIEW_PCI_IO_BASE_SIZE,
+		.type		= MT_DEVICE
+	},
 #endif
 };
 
@@ -452,6 +476,49 @@ static void realview_eb_reset(char mode)
 		__raw_writel(0x0008, reset_ctrl);
 }
 
+#ifdef CONFIG_PCI_HOST_XILINX
+/*
+ * Realview/AB and /PB1136 use a the following base registers
+ *
+ * Usage Local Bus Memory         Base/Map registers used
+ *
+ * Mem   64000000 - 67FFFFFF      LB_BASE0/LB_MAP0,  non prefetch
+ * Mem   68000000 - 6BFFFFFF      LB_BASE1/LB_MAP1,  prefetch
+ * Mem   6C000000 - 6FFFFFFF      LB_BASE2/LB_MAP2
+ * IO    63000000 - 63FFFFFF      PCI IO
+ * Cfg   62000000 - 62FFFFFF	  PCI config
+ *
+ */
+#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
+static struct xilinx_pci_data realview_eb_pci = {
+	.base		= REALVIEW_PCI_VIRT_BASE,
+	.cfg_base	= REALVIEW_PCI_CFG_VIRT_BASE,
+	.io_base	= PCIO_BASE,
+	.sys_pcictl	= __IO_ADDRESS(REALVIEW_SYS_PCICTL),
+	.core_base	= __IO_ADDRESS(REALVIEW_PCI_CORE_BASE),
+	.base_irq	= IRQ_EB_GIC_START + 48,
+
+	.mem_spaces	= {
+		{
+			.name	= "PCI",
+			.start	= REALVIEW_PCI_MEM_BASE0,
+			.end	= REALVIEW_PCI_MEM_BASE0+REALVIEW_PCI_MEM_BASE0_SIZE-1,
+			.flags	= IORESOURCE_MEM,
+		}, {
+			.name	= "PCI non-prefetchable",
+			.start	= REALVIEW_PCI_MEM_BASE1,
+			.end	= REALVIEW_PCI_MEM_BASE1+REALVIEW_PCI_MEM_BASE1_SIZE-1,
+			.flags	= IORESOURCE_MEM,
+		}, {
+			.name	= "PCI prefetchable",
+			.start	= REALVIEW_PCI_MEM_BASE2,
+			.end	= REALVIEW_PCI_MEM_BASE2+REALVIEW_PCI_MEM_BASE2_SIZE-1,
+			.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
+		},
+	},
+};
+#endif
+
 static void __init realview_eb_init(void)
 {
 	int i;
@@ -471,6 +538,7 @@ static void __init realview_eb_init(void)
 	platform_device_register(&realview_i2c_device);
 	platform_device_register(&char_lcd_device);
 	eth_device_register();
+	xilinx_pci_init(&realview_eb_pci);
 	realview_usb_register(realview_eb_isp1761_resources);
 
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d2be12e..583fd00 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -44,6 +44,7 @@
 
 #include <mach/board-pb1176.h>
 #include <mach/irqs.h>
+#include <plat/xilinx-pci.h>
 
 #include "core.h"
 
@@ -102,6 +103,29 @@ static struct map_desc realview_pb1176_io_desc[] __initdata = {
 		.type		= MT_DEVICE,
 	},
 #endif
+#ifdef CONFIG_PCI
+	{
+		.virtual	= IO_ADDRESS(REALVIEW_PCI_CORE_BASE),
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_CORE_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)REALVIEW_PCI_VIRT_BASE,
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_BASE),
+		.length		= REALVIEW_PCI_BASE_SIZE,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)REALVIEW_PCI_CFG_VIRT_BASE,
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_CFG_BASE),
+		.length		= REALVIEW_PCI_CFG_BASE_SIZE,
+		.type		= MT_DEVICE
+	}, {
+		.virtual	=  (unsigned long)REALVIEW_PCI_IO_VIRT_BASE,
+		.pfn		= __phys_to_pfn(REALVIEW_PCI_IO_BASE),
+		.length		= REALVIEW_PCI_IO_BASE_SIZE,
+		.type		= MT_DEVICE
+	},
+#endif
 };
 
 static void __init realview_pb1176_map_io(void)
@@ -348,6 +372,49 @@ static void realview_pb1176_fixup(struct machine_desc *mdesc,
 	meminfo->nr_banks = 1;
 }
 
+#ifdef CONFIG_PCI_HOST_XILINX
+/*
+ * Realview/AB and /PB1136 use a the following base registers
+ *
+ * Usage Local Bus Memory         Base/Map registers used
+ *
+ * Mem   64000000 - 67FFFFFF      LB_BASE0/LB_MAP0,  non prefetch
+ * Mem   68000000 - 6BFFFFFF      LB_BASE1/LB_MAP1,  prefetch
+ * Mem   6C000000 - 6FFFFFFF      LB_BASE2/LB_MAP2
+ * IO    63000000 - 63FFFFFF      PCI IO
+ * Cfg   62000000 - 62FFFFFF	  PCI config
+ *
+ */
+#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
+static struct xilinx_pci_data realview_pb1176_pci = {
+	.base		= REALVIEW_PCI_VIRT_BASE,
+	.cfg_base	= REALVIEW_PCI_CFG_VIRT_BASE,
+	.io_base	= PCIO_BASE,
+	.sys_pcictl	= __IO_ADDRESS(REALVIEW_SYS_PCICTL),
+	.core_base	= __IO_ADDRESS(REALVIEW_PCI_CORE_BASE),
+	.base_irq	= IRQ_EB_GIC_START + 48,
+
+	.mem_spaces	= {
+		{
+			.name	= "PCI",
+			.start	= REALVIEW_PCI_MEM_BASE0,
+			.end	= REALVIEW_PCI_MEM_BASE0+REALVIEW_PCI_MEM_BASE0_SIZE-1,
+			.flags	= IORESOURCE_MEM,
+		}, {
+			.name	= "PCI non-prefetchable",
+			.start	= REALVIEW_PCI_MEM_BASE1,
+			.end	= REALVIEW_PCI_MEM_BASE1+REALVIEW_PCI_MEM_BASE1_SIZE-1,
+			.flags	= IORESOURCE_MEM,
+		}, {
+			.name	= "PCI prefetchable",
+			.start	= REALVIEW_PCI_MEM_BASE2,
+			.end	= REALVIEW_PCI_MEM_BASE2+REALVIEW_PCI_MEM_BASE2_SIZE-1,
+			.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
+		},
+	},
+};
+#endif
+
 static void __init realview_pb1176_init(void)
 {
 	int i;
@@ -364,6 +431,7 @@ static void __init realview_pb1176_init(void)
 	realview_usb_register(realview_pb1176_isp1761_resources);
 	platform_device_register(&pmu_device);
 	platform_device_register(&char_lcd_device);
+	xilinx_pci_init(&realview_pb1176_pci);
 
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 		struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/plat-versatile/xilinx-pci.c b/arch/arm/plat-versatile/xilinx-pci.c
index 077d24a..e0b051c 100644
--- a/arch/arm/plat-versatile/xilinx-pci.c
+++ b/arch/arm/plat-versatile/xilinx-pci.c
@@ -23,6 +23,7 @@
 #include <linux/io.h>
 
 #include <mach/hardware.h>
+#include <mach/platform.h>
 #include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/mach/pci.h>
-- 
1.7.1

[PATCH 5/5] arm: Enable support for virtio

[Arnd Bergmann]

Qemu can use virtio-pci based devices when emulating a
machine with PCI. This adds the necessary Kconfig entry
that allows users to select those drivers.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dd452ee..4920e30 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1093,6 +1093,8 @@ config PCI_HOST_XILINX
 
 source "drivers/pci/Kconfig"
 
+source "drivers/virtio/Kconfig"
+
 source "drivers/pcmcia/Kconfig"
 
 endmenu
-- 
1.7.1

[PATCH 4/5] arm/realview: enable PCI for realview-eb and realview-pb1176

[Linus Walleij]

2010/8/4 Arnd Bergmann <arnd@arndb.de>:

> These two boards use the Xilinx PCI macro, so enable the
> code and set up all the I/O windows for it.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Cool, having worked on the PB1176 recently I think I can say:
Acked-by: Linus Walleij <linus.walleij@stericsson.com>

Yours,
Linus Walleij