ARM: LPC32XX: Various minor fixes and updates

ARM: LPC32XX: Various minor fixes and updates

[wellsk40 at gmail.com]

This patch set updates and fixes some minor LPC32xx issues.

[PATCH 1/6] ARM: LPC32XX: Fix several clock device ID strings
[PATCH 2/6] ARM: LPC32XX: Fix naming convention issues with some defines
[PATCH 3/6] ARM: LPC32xx: Fix gpiolib bit mask macro
[PATCH 4/6] ARM: LPC32xx: Remove MMC peripheral clock enable/disable code
[PATCH 5/6] ARM: LPC32XX: Remove clock enable code for AMBA driver
[PATCH 6/6] ARM: LPC32XX: Add board.h for platform_data structures

[PATCH 1/6] ARM: LPC32XX: Fix several clock device ID strings

[wellsk40 at gmail.com]

From: Kevin Wells <wellsk40@gmail.com>

TBDs for I2S0 and I2S1 clocks are now NULL. Touch controller
device clock renamed to match &pdev->dev.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/clock.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 32d6379..1659b3f 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -1076,9 +1076,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
 	_REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
 	_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
-	_REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
-	_REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
-	_REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
+	_REGISTER_CLOCK(NULL, "i2s0_ck", clk_i2s0)
+	_REGISTER_CLOCK(NULL, "i2s1_ck", clk_i2s1)
+	_REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
 	_REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
 	_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
 	_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
-- 
1.7.1.1

[PATCH 2/6] ARM: LPC32XX: Fix naming convention issues with some defines

[wellsk40 at gmail.com]

From: Kevin Wells <wellsk40@gmail.com>

Some platform defines were prefixed with LCP instead of LPC.
This has been corrected.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/include/mach/platform.h |   48 ++++++++++++------------
 arch/arm/mach-lpc32xx/timer.c                 |   46 ++++++++++++------------
 2 files changed, 47 insertions(+), 47 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index 14ea8d1..85f9aff 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -591,42 +591,42 @@
 /*
  * Timer/counter register offsets
  */
-#define LCP32XX_TIMER_IR(x)			io_p2v((x) + 0x00)
-#define LCP32XX_TIMER_TCR(x)			io_p2v((x) + 0x04)
-#define LCP32XX_TIMER_TC(x)			io_p2v((x) + 0x08)
-#define LCP32XX_TIMER_PR(x)			io_p2v((x) + 0x0C)
-#define LCP32XX_TIMER_PC(x)			io_p2v((x) + 0x10)
-#define LCP32XX_TIMER_MCR(x)			io_p2v((x) + 0x14)
-#define LCP32XX_TIMER_MR0(x)			io_p2v((x) + 0x18)
-#define LCP32XX_TIMER_MR1(x)			io_p2v((x) + 0x1C)
-#define LCP32XX_TIMER_MR2(x)			io_p2v((x) + 0x20)
-#define LCP32XX_TIMER_MR3(x)			io_p2v((x) + 0x24)
-#define LCP32XX_TIMER_CCR(x)			io_p2v((x) + 0x28)
-#define LCP32XX_TIMER_CR0(x)			io_p2v((x) + 0x2C)
-#define LCP32XX_TIMER_CR1(x)			io_p2v((x) + 0x30)
-#define LCP32XX_TIMER_CR2(x)			io_p2v((x) + 0x34)
-#define LCP32XX_TIMER_CR3(x)			io_p2v((x) + 0x38)
-#define LCP32XX_TIMER_EMR(x)			io_p2v((x) + 0x3C)
-#define LCP32XX_TIMER_CTCR(x)			io_p2v((x) + 0x70)
+#define LPC32XX_TIMER_IR(x)			io_p2v((x) + 0x00)
+#define LPC32XX_TIMER_TCR(x)			io_p2v((x) + 0x04)
+#define LPC32XX_TIMER_TC(x)			io_p2v((x) + 0x08)
+#define LPC32XX_TIMER_PR(x)			io_p2v((x) + 0x0C)
+#define LPC32XX_TIMER_PC(x)			io_p2v((x) + 0x10)
+#define LPC32XX_TIMER_MCR(x)			io_p2v((x) + 0x14)
+#define LPC32XX_TIMER_MR0(x)			io_p2v((x) + 0x18)
+#define LPC32XX_TIMER_MR1(x)			io_p2v((x) + 0x1C)
+#define LPC32XX_TIMER_MR2(x)			io_p2v((x) + 0x20)
+#define LPC32XX_TIMER_MR3(x)			io_p2v((x) + 0x24)
+#define LPC32XX_TIMER_CCR(x)			io_p2v((x) + 0x28)
+#define LPC32XX_TIMER_CR0(x)			io_p2v((x) + 0x2C)
+#define LPC32XX_TIMER_CR1(x)			io_p2v((x) + 0x30)
+#define LPC32XX_TIMER_CR2(x)			io_p2v((x) + 0x34)
+#define LPC32XX_TIMER_CR3(x)			io_p2v((x) + 0x38)
+#define LPC32XX_TIMER_EMR(x)			io_p2v((x) + 0x3C)
+#define LPC32XX_TIMER_CTCR(x)			io_p2v((x) + 0x70)
 
 /*
  * ir register definitions
  */
-#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)		(1 << ((n) & 0x3))
-#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)		(1 << (4 + ((n) & 0x3)))
+#define LPC32XX_TIMER_CNTR_MTCH_BIT(n)		(1 << ((n) & 0x3))
+#define LPC32XX_TIMER_CNTR_CAPT_BIT(n)		(1 << (4 + ((n) & 0x3)))
 
 /*
  * tcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_TCR_EN		0x1
-#define LCP32XX_TIMER_CNTR_TCR_RESET		0x2
+#define LPC32XX_TIMER_CNTR_TCR_EN		0x1
+#define LPC32XX_TIMER_CNTR_TCR_RESET		0x2
 
 /*
  * mcr register definitions
  */
-#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)		(0x1 << ((n) * 3))
-#define LCP32XX_TIMER_CNTR_MCR_RESET(n)		(0x1 << (((n) * 3) + 1))
-#define LCP32XX_TIMER_CNTR_MCR_STOP(n)		(0x1 << (((n) * 3) + 2))
+#define LPC32XX_TIMER_CNTR_MCR_MTCH(n)		(0x1 << ((n) * 3))
+#define LPC32XX_TIMER_CNTR_MCR_RESET(n)		(0x1 << (((n) * 3) + 1))
+#define LPC32XX_TIMER_CNTR_MCR_STOP(n)		(0x1 << (((n) * 3) + 2))
 
 /*
  * Standard UART register offsets
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 630dd4a..791100b 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -33,7 +33,7 @@
 
 static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
 {
-	return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
+	return (cycle_t)__raw_readl(LPC32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
 }
 
 static struct clocksource lpc32xx_clksrc = {
@@ -48,11 +48,11 @@ static struct clocksource lpc32xx_clksrc = {
 static int lpc32xx_clkevt_next_event(unsigned long delta,
     struct clock_event_device *dev)
 {
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-	__raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 
 	return 0;
 }
@@ -72,7 +72,7 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
 		 * disable the timer to wait for the first call to
 		 * set_next_event().
 		 */
-		__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+		__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
 		break;
 
 	case CLOCK_EVT_MODE_UNUSED:
@@ -95,8 +95,8 @@ static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
 	struct clock_event_device *evt = &lpc32xx_clkevt;
 
 	/* Clear match */
-	__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-		LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+		LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
 
 	evt->event_handler(evt);
 
@@ -142,14 +142,14 @@ static void __init lpc32xx_timer_init(void)
 	clkrate = clkrate / clk_get_pclk_div();
 
 	/* Initial timer setup */
-	__raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
-		LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
-	__raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
-		LCP32XX_TIMER_CNTR_MCR_STOP(0) |
-		LCP32XX_TIMER_CNTR_MCR_RESET(0),
-		LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0),
+		LPC32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+	__raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) |
+		LPC32XX_TIMER_CNTR_MCR_STOP(0) |
+		LPC32XX_TIMER_CNTR_MCR_RESET(0),
+		LPC32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
 
 	/* Setup tick interrupt */
 	setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
@@ -165,12 +165,12 @@ static void __init lpc32xx_timer_init(void)
 	clockevents_register_device(&lpc32xx_clkevt);
 
 	/* Use timer1 as clock source. */
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
-	__raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
-	__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
-	__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
-		LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+	__raw_writel(0, LPC32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+	__raw_writel(0, LPC32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+	__raw_writel(LPC32XX_TIMER_CNTR_TCR_EN,
+		LPC32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
 	lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
 		lpc32xx_clksrc.shift);
 	clocksource_register(&lpc32xx_clksrc);
-- 
1.7.1.1

[PATCH 3/6] ARM: LPC32xx: Fix gpiolib bit mask macro

[wellsk40 at gmail.com]

From: Kevin Wells <wellsk40@gmail.com>

The GPIO bank 3 input mask macro was missing a critical mask that
would cause it to return invalid pin states

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/gpiolib.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
index 69061ea..16577c5 100644
--- a/arch/arm/mach-lpc32xx/gpiolib.c
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -59,7 +59,8 @@
 #define GPO3_PIN_TO_BIT(x)			(1 << (x))
 #define GPIO012_PIN_IN_SEL(x, y)		(((x) >> (y)) & 1)
 #define GPIO3_PIN_IN_SHIFT(x)			((x) == 5 ? 24 : 10 + (x))
-#define GPIO3_PIN_IN_SEL(x, y)			((x) >> GPIO3_PIN_IN_SHIFT(y))
+#define GPIO3_PIN_IN_SEL(x, y)			(((x) >> \
+						GPIO3_PIN_IN_SHIFT(y)) & 1)
 #define GPIO3_PIN5_IN_SEL(x)			(((x) >> 24) & 1)
 #define GPI3_PIN_IN_SEL(x, y)			(((x) >> (y)) & 1)
 
-- 
1.7.1.1

[PATCH 4/6] ARM: LPC32xx: Remove MMC peripheral clock enable/disable code

[wellsk40 at gmail.com]

From: Kevin Wells <wellsk40@gmail.com>

The MMC clock rate set and get functions had extra code to force
the high level peripheral clock to enable prior to register
accesses. This isn't needed.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/clock.c |   14 ++------------
 1 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index 1659b3f..dd34a64 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -738,14 +738,9 @@ static int mmc_onoff_enable(struct clk *clk, int enable)
 
 static unsigned long mmc_get_rate(struct clk *clk)
 {
-	u32 div, rate, oldclk;
+	u32 div, rate;
 
-	/* The MMC clock must be on when accessing an MMC register */
-	oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
-	__raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
-		LPC32XX_CLKPWR_MS_CTRL);
 	div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
-	__raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
 
 	/* Get the parent clock rate */
 	rate = clk->parent->get_rate(clk->parent);
@@ -778,7 +773,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
 
 static int mmc_set_rate(struct clk *clk, unsigned long rate)
 {
-	u32 oldclk, tmp;
+	u32 tmp;
 	unsigned long prate, div, crate = mmc_round_rate(clk, rate);
 
 	prate = clk->parent->get_rate(clk->parent);
@@ -786,16 +781,11 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate)
 	div = prate / crate;
 
 	/* The MMC clock must be on when accessing an MMC register */
-	oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
-	__raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
-		LPC32XX_CLKPWR_MS_CTRL);
 	tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
 		~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
 	tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
 	__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 
-	__raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
-
 	return 0;
 }
 
-- 
1.7.1.1

[PATCH 5/6] ARM: LPC32XX: Remove clock enable code for AMBA driver

[wellsk40 at gmail.com]

From: Kevin Wells <wellsk40@gmail.com>

These clock enables were just for the AMBA driver's peripheral
ID check and are no longer needed with the AMBA bus clock
changes.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/phy3250.c |   17 -----------------
 1 files changed, 0 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index bc9a42d..3ef69cb 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -340,23 +340,6 @@ static void __init phy3250_board_init(void)
 
 	lpc32xx_serial_init();
 
-	/*
-	 * AMBA peripheral clocks need to be enabled prior to AMBA device
-	 * detection or a data fault will occur, so enable the clocks
-	 * here. However, we don't want to enable them if the peripheral
-	 * isn't included in the image
-	 */
-#ifdef CONFIG_FB_ARMCLCD
-	tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
-	__raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
-		LPC32XX_CLKPWR_LCDCLK_CTRL);
-#endif
-#ifdef CONFIG_SPI_PL022
-	tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
-	__raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
-		LPC32XX_CLKPWR_SSP_CLK_CTRL);
-#endif
-
 	platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 		struct amba_device *d = amba_devs[i];
-- 
1.7.1.1

[PATCH 6/6] ARM: LPC32XX: Add board.h for platform_data structures

[wellsk40 at gmail.com]

From: Kevin Wells <wellsk40@gmail.com>

Add the initial board.h file to support platform data for
some drivers.

Signed-off-by: Kevin Wells <wellsk40@gmail.com>
---
 arch/arm/mach-lpc32xx/include/mach/board.h |   47 ++++++++++++++++++++++++++++
 1 files changed, 47 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-lpc32xx/include/mach/board.h

diff --git a/arch/arm/mach-lpc32xx/include/mach/board.h b/arch/arm/mach-lpc32xx/include/mach/board.h
new file mode 100644
index 0000000..a810c78
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/board.h
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/board.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_BOARD_H
+#define __ASM_ARCH_BOARD_H
+
+#include <linux/types.h>
+
+/*
+ * lpc32xx touchscreen controller timing platform data.
+ * All timing values are based on a 32KHz clock.
+ */
+struct lpc32xx_tsc_data {
+	u32	dtr_clocks;	/* Clocks to delay start after pen detect */
+	u32	rtr_clocks;	/* Number of settling clocks after mux */
+	u32	dxp_clocks;	/* Number of drain plate discharge clocks */
+	u32	ttr_clocks;	/* Clocks to delay next pen status check */
+	u32	utr_clocks;	/* Interval clocks between scans */
+};
+
+/*
+ * lpc32xx key scanner timing platform data.
+ * All timing values are based on a 32KHz clock.
+ */
+struct lpc32XX_kscan_data {
+	const u32 *keymap_data;	/* Mapped key data to scanner */
+	u8	matrix_sz;	/* Size of matrix in XxY, ie. 3 = 3x3 */
+	u32	deb_clks;	/* Number of debounce clocks */
+	u32	scan_delay;	/* Number of scan delay clocks */
+};
+
+#endif /* __ASM_ARCH_BOARD_H */
-- 
1.7.1.1

ARM: LPC32XX: Various minor fixes and updates

[Wolfram Sang]

Hi Kevin,

On Wed, Aug 18, 2010 at 04:40:53PM -0700, wellsk40 at gmail.com wrote:
> This patch set updates and fixes some minor LPC32xx issues.
> 
> [PATCH 1/6] ARM: LPC32XX: Fix several clock device ID strings
> [PATCH 2/6] ARM: LPC32XX: Fix naming convention issues with some defines
> [PATCH 3/6] ARM: LPC32xx: Fix gpiolib bit mask macro
> [PATCH 4/6] ARM: LPC32xx: Remove MMC peripheral clock enable/disable code
> [PATCH 5/6] ARM: LPC32XX: Remove clock enable code for AMBA driver
> [PATCH 6/6] ARM: LPC32XX: Add board.h for platform_data structures

This looks confusing for me. Those patches come from your branch
'lpc32xx_up1' but some of them are also contained in
'wells/lpc32xx-arch_up1' which you already posted. So, this looks like a
V2 of the series to me or am I wrong? If so, what has changed and why?

If I might add, the increasing number of branches makes it hard to
decide what is currently needed for a board-support; maybe a
"for-mainline"-branch or something similar with all
"state-of-the-art"-branches merged might help here?

Kind regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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ARM: LPC32XX: Various minor fixes and updates

[Kevin Wells]

>> This patch set updates and fixes some minor LPC32xx issues.
>>
>> [PATCH 1/6] ARM: LPC32XX: Fix several clock device ID strings
>> [PATCH 2/6] ARM: LPC32XX: Fix naming convention issues with some defines
>> [PATCH 3/6] ARM: LPC32xx: Fix gpiolib bit mask macro
>> [PATCH 4/6] ARM: LPC32xx: Remove MMC peripheral clock enable/disable code
>> [PATCH 5/6] ARM: LPC32XX: Remove clock enable code for AMBA driver
>> [PATCH 6/6] ARM: LPC32XX: Add board.h for platform_data structures
>
> This looks confusing for me. Those patches come from your branch
> 'lpc32xx_up1' but some of them are also contained in
> 'wells/lpc32xx-arch_up1' which you already posted. So, this looks like a
> V2 of the series to me or am I wrong? If so, what has changed and why?
>

Hi Wolfram,
Thanks for the feedback. This is a v2 patch. I'll post a changelog in a bit.

> If I might add, the increasing number of branches makes it hard to
> decide what is currently needed for a board-support; maybe a
> "for-mainline"-branch or something similar with all
> "state-of-the-art"-branches merged might help here?
>

I'm going to post future patch sets for review without providing a GIT link
on our server until it's ready for mainline. This makes it a bit easier for me
too and this seems to be more the standard approach.

thanks,
Kevin

> Kind regards,
>
> ? Wolfram
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | Wolfram Sang ? ? ? ? ? ? ? ?|
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
>
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>

ARM: LPC32XX: Various minor fixes and updates

[Kevin Wells]

>
> [PATCH 1/6] ARM: LPC32XX: Fix several clock device ID strings
> [PATCH 2/6] ARM: LPC32XX: Fix naming convention issues with some defines
> [PATCH 3/6] ARM: LPC32xx: Fix gpiolib bit mask macro
> [PATCH 4/6] ARM: LPC32xx: Remove MMC peripheral clock enable/disable code
> [PATCH 5/6] ARM: LPC32XX: Remove clock enable code for AMBA driver
> [PATCH 6/6] ARM: LPC32XX: Add board.h for platform_data structures
>

Sorry about the lack of info on changed with this patchset.
This is a v2 update to the v1 patchset. The title should of indicated that :(
v1 was originally posted July 29 (ARM: LPC32xx: Misc arch updates and fixes)

Unchanged from v1:
       LPC definition fixes
       Fix GPIO 3 IN bit mask
       Remove un-needed local MMC clock enable code
       Fix up I2S device ID name for clock registration

Changed from v1:
       Remove un-needed code from IRQ ack handler
         The problem this patch fixed needs more investigation, so
there's no point
          in putting in a partial fix
       Change AMBA pre and post clock init for AMBA registration
          No longer needed with amba clocking fix
       Add a workaround for LCD register access prior to clock enable
          No longer needed with amba clocking fix

Additions in v2:
       Changed the touch screen clock device ID name to match &pdev->dev per
          the driver currently under review
       Added board.h file and platform data for touch screen controller and
          key scanner interface

I sneaked the additions in this series so I can move forward with the
tsc changes.

Note the LCD will still not work correctly with this patch. I'll post
another patch with
the fixes for the AMBA apb_pclk (in mach-lcp32xx/clock.c) soon that will fix the
LCD issue. I want to do the amba clocking patch separately to avoid holding this
series up.

ARM: LPC32XX: Various minor fixes and updates

[Russell King - ARM Linux]

On Fri, Aug 20, 2010 at 03:16:17PM -0700, Kevin Wells wrote:
> >
> > [PATCH 1/6] ARM: LPC32XX: Fix several clock device ID strings
> > [PATCH 2/6] ARM: LPC32XX: Fix naming convention issues with some defines
> > [PATCH 3/6] ARM: LPC32xx: Fix gpiolib bit mask macro
> > [PATCH 4/6] ARM: LPC32xx: Remove MMC peripheral clock enable/disable code
> > [PATCH 5/6] ARM: LPC32XX: Remove clock enable code for AMBA driver
> > [PATCH 6/6] ARM: LPC32XX: Add board.h for platform_data structures
> >
> 
> Sorry about the lack of info on changed with this patchset.
> This is a v2 update to the v1 patchset. The title should of indicated that :(
> v1 was originally posted July 29 (ARM: LPC32xx: Misc arch updates and fixes)
> 
> Unchanged from v1:
>        LPC definition fixes
>        Fix GPIO 3 IN bit mask
>        Remove un-needed local MMC clock enable code
>        Fix up I2S device ID name for clock registration
> 
> Changed from v1:
>        Remove un-needed code from IRQ ack handler
>          The problem this patch fixed needs more investigation, so
> there's no point
>           in putting in a partial fix
>        Change AMBA pre and post clock init for AMBA registration
>           No longer needed with amba clocking fix
>        Add a workaround for LCD register access prior to clock enable
>           No longer needed with amba clocking fix
> 
> Additions in v2:
>        Changed the touch screen clock device ID name to match &pdev->dev per
>           the driver currently under review
>        Added board.h file and platform data for touch screen controller and
>           key scanner interface
> 
> I sneaked the additions in this series so I can move forward with the
> tsc changes.

This patch set looks fine to me.