From: jason77.wang@gmail.com (Jason Wang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/3] ARM: imx: set cache line size to 64 bytes for i.MX5
Date: Sat, 21 Aug 2010 16:24:05 +0800 [thread overview]
Message-ID: <1282379045-32363-4-git-send-email-jason77.wang@gmail.com> (raw)
In-Reply-To: <1282379045-32363-3-git-send-email-jason77.wang@gmail.com>
The core of i.MX5 series is cortex-A8, its cache line size is 64 bytes
instead of 32 bytes. Refer to the OMAP3's selection, we choose 64
bytes for i.MX5, this can increase a little bit performance when
perform cache operations.
Signed-off-by: Jason Wang <jason77.wang@gmail.com>
---
arch/arm/plat-mxc/Kconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 0527e65..6785db4 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -43,6 +43,7 @@ config ARCH_MXC91231
config ARCH_MX5
bool "MX5-based"
select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
help
This enables support for systems based on the Freescale i.MX51 family
--
1.5.6.5
prev parent reply other threads:[~2010-08-21 8:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-21 8:24 [PATCH 0/3] three small fixes for i.MX5 Jason Wang
2010-08-21 8:24 ` [PATCH 1/3] mxc/tzic: add base address when accessing TZIC registers Jason Wang
2010-08-21 8:24 ` [PATCH 2/3] mx5/clock: fix clear bit fields issue in _clk_ccgr_disable function Jason Wang
2010-08-21 8:24 ` Jason Wang [this message]
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