From: stepanm@codeaurora.org (Stepan Moskovchenko)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 02/14] msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU
Date: Fri, 12 Nov 2010 19:29:48 -0800 [thread overview]
Message-ID: <1289619000-13167-3-git-send-email-stepanm@codeaurora.org> (raw)
In-Reply-To: <1289619000-13167-1-git-send-email-stepanm@codeaurora.org>
Add register addresses and IRQ numbers for the IOMMU used
for the second 2D graphics core.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
---
arch/arm/mach-msm/include/mach/irqs-8x60.h | 7 ++++++-
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h | 3 +++
2 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
index 36074cf..f65841c 100644
--- a/arch/arm/mach-msm/include/mach/irqs-8x60.h
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -237,7 +237,12 @@
#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
#define INT_UART12DM_IRQ (GIC_SPI_START + 195)
#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
-/*SPI 197 to 216 arent used in 8x60*/
+
+/*SPI 197 to 209 arent used in 8x60*/
+#define SMMU_GFX2D1_CB_SC_SECURE_IRQ (GIC_SPI_START + 210)
+#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 211)
+
+/*SPI 212 to 216 arent used in 8x60*/
#define SMPSS_SPARE_1 (GIC_SPI_START + 217)
#define SMPSS_SPARE_2 (GIC_SPI_START + 218)
#define SMPSS_SPARE_3 (GIC_SPI_START + 219)
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 45bab50..7c43a9b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -98,4 +98,7 @@
#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000
#define MSM_IOMMU_GFX2D0_SIZE SZ_1M
+#define MSM_IOMMU_GFX2D1_PHYS 0x07E00000
+#define MSM_IOMMU_GFX2D1_SIZE SZ_1M
+
#endif
--
1.7.0.2
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2010-11-13 3:29 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-13 3:29 [PATCH 00/14] Improvements to the MSM IOMMU driver Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 01/14] msm: iommu: Increase maximum MID size to 5 bits Stepan Moskovchenko
2010-11-13 3:29 ` Stepan Moskovchenko [this message]
2010-11-13 3:29 ` [PATCH 03/14] msm: iommu: Use more consistent naming in platform data Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 04/14] msm: iommu: Revise GFX3D IOMMU contexts and M2V mappings Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 05/14] msm: iommu: Revise GFX2D0 " Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 06/14] msm: iommu: Support for the 2nd GFX core's IOMMU Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 07/14] msm: iommu: Mark functions with the right section names Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 08/14] msm: iommu: Don't flush page tables if no devices attached Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 09/14] msm: iommu: Kconfig option for cacheable page tables Stepan Moskovchenko
2010-11-14 20:17 ` Daniel Walker
2010-11-15 2:56 ` Stepan Moskovchenko
2010-11-15 18:20 ` Daniel Walker
2010-11-16 1:47 ` Stepan Moskovchenko
2010-11-16 1:46 ` [PATCH 09/14 v2] msm: iommu: Kconfig item " Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 10/14] msm: iommu: Check if device is already attached Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 11/14] msm: iommu: Kconfig dependency for the IOMMU API Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 12/14] msm: iommu: Definitions for extended memory attributes Stepan Moskovchenko
2010-11-16 2:19 ` [PATCH 12/14 v2] " Stepan Moskovchenko
2010-11-13 3:29 ` [PATCH 13/14] msm: iommu: Support cache-coherent memory access Stepan Moskovchenko
2010-11-16 2:20 ` [PATCH 13/14 v2] " Stepan Moskovchenko
2010-11-13 3:30 ` [PATCH 14/14] msm: iommu: Miscellaneous code cleanup Stepan Moskovchenko
2010-11-16 0:25 ` Daniel Walker
2010-11-16 1:16 ` Stepan Moskovchenko
2010-11-16 20:45 ` Daniel Walker
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