* [PATCH 1/7] OMAP3: remove unused code from the ASM sleep code
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
@ 2010-12-18 15:44 ` jean.pihet at newoldbits.com
2010-12-18 15:44 ` [PATCH 2/7] OMAP2+: use global values for the SRAM PA addresses jean.pihet at newoldbits.com
` (6 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-18 15:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
Remove unused code:
- macros,
- variables,
- unused semaphore locking API. This API shall be added back
when needed,
- infinite loops for debug.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon<nm@ti.com>
---
arch/arm/mach-omap2/pm.h | 1 -
arch/arm/mach-omap2/sleep34xx.S | 58 ++++-----------------------------------
2 files changed, 6 insertions(+), 53 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index aff39d0..e458b2a 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -80,7 +80,6 @@ extern void save_secure_ram_context(u32 *addr);
extern void omap3_save_scratchpad_contents(void);
extern unsigned int omap24xx_idle_loop_suspend_sz;
-extern unsigned int omap34xx_suspend_sz;
extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index d2eda01..2191576 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -35,11 +35,7 @@
#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c
-#define PM_PREPWSTST_CORE_V OMAP34XX_PRM_REGADDR(CORE_MOD, \
- OMAP3430_PM_PREPWSTST)
#define PM_PREPWSTST_CORE_P 0x48306AE8
-#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
- OMAP3430_PM_PREPWSTST)
#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
@@ -62,36 +58,10 @@
#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
- .text
-/* Function to acquire the semaphore in scratchpad */
-ENTRY(lock_scratchpad_sem)
- stmfd sp!, {lr} @ save registers on stack
-wait_sem:
- mov r0,#1
- ldr r1, sdrc_scratchpad_sem
-wait_loop:
- ldr r2, [r1] @ load the lock value
- cmp r2, r0 @ is the lock free ?
- beq wait_loop @ not free...
- swp r2, r0, [r1] @ semaphore free so lock it and proceed
- cmp r2, r0 @ did we succeed ?
- beq wait_sem @ no - try again
- ldmfd sp!, {pc} @ restore regs and return
-sdrc_scratchpad_sem:
- .word SDRC_SCRATCHPAD_SEM_V
-ENTRY(lock_scratchpad_sem_sz)
- .word . - lock_scratchpad_sem
-
- .text
-/* Function to release the scratchpad semaphore */
-ENTRY(unlock_scratchpad_sem)
- stmfd sp!, {lr} @ save registers on stack
- ldr r3, sdrc_scratchpad_sem
- mov r2,#0
- str r2,[r3]
- ldmfd sp!, {pc} @ restore regs and return
-ENTRY(unlock_scratchpad_sem_sz)
- .word . - unlock_scratchpad_sem
+
+/*
+ * API functions
+ */
.text
/* Function call to get the restore pointer for resume from OFF */
@@ -178,8 +148,7 @@ ENTRY(es3_sdrc_fix_sz)
/* Function to call rom code to save secure ram context */
ENTRY(save_secure_ram_context)
stmfd sp!, {r1-r12, lr} @ save registers on stack
-save_secure_ram_debug:
- /* b save_secure_ram_debug */ @ enable to debug save code
+
adr r3, api_params @ r3 points to parameters
str r0, [r3,#0x4] @ r0 has sdram address
ldr r12, high_mask
@@ -219,8 +188,7 @@ ENTRY(save_secure_ram_context_sz)
*/
ENTRY(omap34xx_cpu_suspend)
stmfd sp!, {r0-r12, lr} @ save registers on stack
-loop:
- /*b loop*/ @Enable to debug by stepping through code
+
/* r0 contains restore pointer in sdram */
/* r1 contains information about saving context */
ldr r4, sdrc_power @ read the SDRC_POWER register
@@ -252,7 +220,6 @@ loop:
ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3:
- /*b restore_es3*/ @ Enable to debug restore code
ldr r5, pm_prepwstst_core_p
ldr r4, [r5]
and r4, r4, #0x3
@@ -272,7 +239,6 @@ copy_to_sram:
b restore
restore_3630:
- /*b restore_es3630*/ @ Enable to debug restore code
ldr r1, pm_prepwstst_core_p
ldr r2, [r1]
and r2, r2, #0x3
@@ -284,7 +250,6 @@ restore_3630:
str r2, [r1]
/* Fall thru for the remaining logic */
restore:
- /* b restore*/ @ Enable to debug restore code
/* Check what was the reason for mpu reset and store the reason in r9*/
/* 1 - Only L1 and logic lost */
/* 2 - Only L2 lost - In this case, we wont be here */
@@ -493,7 +458,6 @@ usettbr0:
ldmfd sp!, {r0-r12, pc} @ restore regs and return
save_context_wfi:
- /*b save_context_wfi*/ @ enable to debug save code
mov r8, r0 /* Store SDRAM address in r8 */
mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
mov r4, #0x1 @ Number of parameters for restore call
@@ -672,12 +636,8 @@ sdrc_dlla_status:
.word SDRC_DLLA_STATUS_V
sdrc_dlla_ctrl:
.word SDRC_DLLA_CTRL_V
-pm_prepwstst_core:
- .word PM_PREPWSTST_CORE_V
pm_prepwstst_core_p:
.word PM_PREPWSTST_CORE_P
-pm_prepwstst_mpu:
- .word PM_PREPWSTST_MPU_V
pm_pwstctrl_mpu:
.word PM_PWSTCTRL_MPU_P
scratchpad_base:
@@ -686,12 +646,6 @@ sram_base:
.word SRAM_BASE_P + 0x8000
sdrc_power:
.word SDRC_POWER_V
-clk_stabilize_delay:
- .word 0x000001FF
-assoc_mask:
- .word 0x3ff
-numset_mask:
- .word 0x7fff
ttbrbit_mask:
.word 0xFFFFC000
table_index_mask:
--
1.7.2.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 2/7] OMAP2+: use global values for the SRAM PA addresses
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
2010-12-18 15:44 ` [PATCH 1/7] OMAP3: remove unused code from the " jean.pihet at newoldbits.com
@ 2010-12-18 15:44 ` jean.pihet at newoldbits.com
2010-12-18 15:44 ` [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code jean.pihet at newoldbits.com
` (5 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-18 15:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
The SRAM PA addresses are locally defined and used at
different places, i.e. SRAM management code and idle sleep code.
The macros are now defined at a centralized place, for
easier maintenance.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon<nm@ti.com>
---
arch/arm/mach-omap2/sdrc.h | 1 -
arch/arm/mach-omap2/sleep34xx.S | 1 +
arch/arm/plat-omap/include/plat/sram.h | 11 +++++++++++
arch/arm/plat-omap/sram.c | 7 ++-----
4 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 68f57bb..b3f8379 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg)
*/
#define SDRC_MPURATE_LOOPS 96
-
#endif
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2191576..406cd2a 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,6 +26,7 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
+#include <plat/sram.h>
#include <mach/io.h>
#include "cm.h"
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
index 5905100..9967d5e 100644
--- a/arch/arm/plat-omap/include/plat/sram.h
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -11,6 +11,7 @@
#ifndef __ARCH_ARM_OMAP_SRAM_H
#define __ARCH_ARM_OMAP_SRAM_H
+#ifndef __ASSEMBLY__
extern void * omap_sram_push(void * start, unsigned long size);
extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
@@ -74,4 +75,14 @@ extern void omap_push_sram_idle(void);
static inline void omap_push_sram_idle(void) {}
#endif /* CONFIG_PM */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * OMAP2+: define the SRAM PA addresses.
+ * Used by the SRAM management code and the idle sleep code.
+ */
+#define OMAP2_SRAM_PA 0x40200000
+#define OMAP3_SRAM_PA 0x40200000
+#define OMAP4_SRAM_PA 0x40300000
+
#endif
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 819ea0c..1a686c8 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -41,15 +41,12 @@
#define OMAP1_SRAM_PA 0x20000000
#define OMAP1_SRAM_VA VMALLOC_END
-#define OMAP2_SRAM_PA 0x40200000
-#define OMAP2_SRAM_PUB_PA 0x4020f800
+#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP2_SRAM_VA 0xfe400000
#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
-#define OMAP3_SRAM_PA 0x40200000
#define OMAP3_SRAM_VA 0xfe400000
-#define OMAP3_SRAM_PUB_PA 0x40208000
+#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
-#define OMAP4_SRAM_PA 0x40300000
#define OMAP4_SRAM_VA 0xfe400000
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
--
1.7.2.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
2010-12-18 15:44 ` [PATCH 1/7] OMAP3: remove unused code from the " jean.pihet at newoldbits.com
2010-12-18 15:44 ` [PATCH 2/7] OMAP2+: use global values for the SRAM PA addresses jean.pihet at newoldbits.com
@ 2010-12-18 15:44 ` jean.pihet at newoldbits.com
2010-12-20 11:20 ` Vishwanath Sripathy
2010-12-18 15:44 ` [PATCH 4/7] OMAP3: re-organize " jean.pihet at newoldbits.com
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-18 15:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
Using macros from existing include files for registers addresses.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Based on original patch from Vishwa.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Cc: Vishwanath BS <vishwanath.bs@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/control.h | 2 ++
arch/arm/mach-omap2/sleep34xx.S | 29 ++++++++++++++++++-----------
2 files changed, 20 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d7911c5..72efefb 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -274,6 +274,8 @@
#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
+#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
+ OMAP343X_SCRATCHPAD + reg)
/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 406cd2a..8e9f38f 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -34,20 +34,27 @@
#include "sdrc.h"
#include "control.h"
-#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c
-
-#define PM_PREPWSTST_CORE_P 0x48306AE8
+/*
+ * Registers access definitions
+ */
+#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
+#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
+ (SDRC_SCRATCHPAD_SEM_OFFS)
+#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
+ OMAP3430_PM_PREPWSTST
#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
-#define SRAM_BASE_P 0x40200000
-#define CONTROL_STAT 0x480022F0
-#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
- + OMAP36XX_CONTROL_MEM_RTA_CTRL)
-#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
- * available */
-#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
- + SCRATCHPAD_MEM_OFFS)
+#define SRAM_BASE_P OMAP3_SRAM_PA
+#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
+#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
+ OMAP36XX_CONTROL_MEM_RTA_CTRL)
+
+/* Move this as correct place is available */
+#define SCRATCHPAD_MEM_OFFS 0x310
+#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
+ OMAP343X_CONTROL_MEM_WKUP +\
+ SCRATCHPAD_MEM_OFFS)
#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
--
1.7.2.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code
2010-12-18 15:44 ` [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code jean.pihet at newoldbits.com
@ 2010-12-20 11:20 ` Vishwanath Sripathy
0 siblings, 0 replies; 18+ messages in thread
From: Vishwanath Sripathy @ 2010-12-20 11:20 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: jean.pihet at newoldbits.com [mailto:jean.pihet at newoldbits.com]
> Sent: Saturday, December 18, 2010 9:15 PM
> To: linux-omap at vger.kernel.org
> Cc: khilman at deeprootsystems.com; linux-arm-
> kernel at lists.infradead.org; Jean Pihet; Vishwanath BS
> Subject: [PATCH 3/7] OMAP3: remove hardcoded values from the ASM
> sleep code
>
> From: Jean Pihet <j-pihet@ti.com>
>
> Using macros from existing include files for registers addresses.
>
> Tested on N900 and Beagleboard with full RET and OFF modes,
> using cpuidle and suspend.
>
> Based on original patch from Vishwa.
>
> Signed-off-by: Jean Pihet <j-pihet@ti.com>
> Cc: Vishwanath BS <vishwanath.bs@ti.com>
Acked-by: Vishwanath BS <vishwanath.bs@ti.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Tested-by: Nishanth Menon <nm@ti.com>
> ---
> arch/arm/mach-omap2/control.h | 2 ++
> arch/arm/mach-omap2/sleep34xx.S | 29
> ++++++++++++++++++-----------
> 2 files changed, 20 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-
> omap2/control.h
> index d7911c5..72efefb 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -274,6 +274,8 @@
> #define OMAP343X_SCRATCHPAD_ROM
> (OMAP343X_CTRL_BASE + 0x860)
> #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE +
> 0x910)
> #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
> +#define OMAP343X_SCRATCHPAD_REGADDR(reg)
> OMAP2_L4_IO_ADDRESS(\
> + OMAP343X_SCRATCHPAD +
> reg)
>
> /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
> #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 406cd2a..8e9f38f 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -34,20 +34,27 @@
> #include "sdrc.h"
> #include "control.h"
>
> -#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c
> -
> -#define PM_PREPWSTST_CORE_P 0x48306AE8
> +/*
> + * Registers access definitions
> + */
> +#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
> +#define SDRC_SCRATCHPAD_SEM_V
> OMAP343X_SCRATCHPAD_REGADDR\
> + (SDRC_SCRATCHPAD_SEM_OFFS)
> +#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD
> +\
> + OMAP3430_PM_PREPWSTST
> #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD
> + OMAP2_PM_PWSTCTRL
> #define CM_IDLEST1_CORE_V
> OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD,
> CM_IDLEST)
> -#define SRAM_BASE_P 0x40200000
> -#define CONTROL_STAT 0x480022F0
> -#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
> - +
> OMAP36XX_CONTROL_MEM_RTA_CTRL)
> -#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> - * available */
> -#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +
> OMAP343X_CONTROL_MEM_WKUP\
> - + SCRATCHPAD_MEM_OFFS)
> +#define SRAM_BASE_P OMAP3_SRAM_PA
> +#define CONTROL_STAT OMAP343X_CTRL_BASE +
> OMAP343X_CONTROL_STATUS
> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
> +
> OMAP36XX_CONTROL_MEM_RTA_CTRL)
> +
> +/* Move this as correct place is available */
> +#define SCRATCHPAD_MEM_OFFS 0x310
> +#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
> + OMAP343X_CONTROL_MEM_WKUP +\
> + SCRATCHPAD_MEM_OFFS)
> #define SDRC_POWER_V
> OMAP34XX_SDRC_REGADDR(SDRC_POWER)
> #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE +
> SDRC_SYSCONFIG)
> #define SDRC_MR_0_P (OMAP343X_SDRC_BASE +
> SDRC_MR_0)
> --
> 1.7.2.3
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 4/7] OMAP3: re-organize the ASM sleep code
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
` (2 preceding siblings ...)
2010-12-18 15:44 ` [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code jean.pihet at newoldbits.com
@ 2010-12-18 15:44 ` jean.pihet at newoldbits.com
2010-12-18 15:44 ` [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths jean.pihet at newoldbits.com
` (3 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-18 15:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
Organize the code in the following sections:
- register access macros,
- API functions,
- internal functions.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/sleep34xx.S | 114 +++++++++++++++++++++------------------
1 files changed, 61 insertions(+), 53 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 8e9f38f..beeb682 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -79,6 +79,7 @@ ENTRY(get_restore_pointer)
ldmfd sp!, {pc} @ restore regs and return
ENTRY(get_restore_pointer_sz)
.word . - get_restore_pointer
+
.text
/* Function call to get the restore pointer for 3630 resume from OFF */
ENTRY(get_omap3630_restore_pointer)
@@ -89,9 +90,18 @@ ENTRY(get_omap3630_restore_pointer_sz)
.word . - get_omap3630_restore_pointer
.text
+/* Function call to get the restore pointer for ES3 to resume from OFF */
+ENTRY(get_es3_restore_pointer)
+ stmfd sp!, {lr} @ save registers on stack
+ adr r0, restore_es3
+ ldmfd sp!, {pc} @ restore regs and return
+ENTRY(get_es3_restore_pointer_sz)
+ .word . - get_es3_restore_pointer
+
+ .text
/*
* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
- * This function sets up a fflag that will allow for this toggling to take
+ * This function sets up a flag that will allow for this toggling to take
* place on 3630. Hopefully some version in the future maynot need this
*/
ENTRY(enable_omap3630_toggle_l2_on_restore)
@@ -101,58 +111,6 @@ ENTRY(enable_omap3630_toggle_l2_on_restore)
str r1, l2dis_3630
ldmfd sp!, {pc} @ restore regs and return
- .text
-/* Function call to get the restore pointer for for ES3 to resume from OFF */
-ENTRY(get_es3_restore_pointer)
- stmfd sp!, {lr} @ save registers on stack
- adr r0, restore_es3
- ldmfd sp!, {pc} @ restore regs and return
-ENTRY(get_es3_restore_pointer_sz)
- .word . - get_es3_restore_pointer
-
-ENTRY(es3_sdrc_fix)
- ldr r4, sdrc_syscfg @ get config addr
- ldr r5, [r4] @ get value
- tst r5, #0x100 @ is part access blocked
- it eq
- biceq r5, r5, #0x100 @ clear bit if set
- str r5, [r4] @ write back change
- ldr r4, sdrc_mr_0 @ get config addr
- ldr r5, [r4] @ get value
- str r5, [r4] @ write back change
- ldr r4, sdrc_emr2_0 @ get config addr
- ldr r5, [r4] @ get value
- str r5, [r4] @ write back change
- ldr r4, sdrc_manual_0 @ get config addr
- mov r5, #0x2 @ autorefresh command
- str r5, [r4] @ kick off refreshes
- ldr r4, sdrc_mr_1 @ get config addr
- ldr r5, [r4] @ get value
- str r5, [r4] @ write back change
- ldr r4, sdrc_emr2_1 @ get config addr
- ldr r5, [r4] @ get value
- str r5, [r4] @ write back change
- ldr r4, sdrc_manual_1 @ get config addr
- mov r5, #0x2 @ autorefresh command
- str r5, [r4] @ kick off refreshes
- bx lr
-sdrc_syscfg:
- .word SDRC_SYSCONFIG_P
-sdrc_mr_0:
- .word SDRC_MR_0_P
-sdrc_emr2_0:
- .word SDRC_EMR2_0_P
-sdrc_manual_0:
- .word SDRC_MANUAL_0_P
-sdrc_mr_1:
- .word SDRC_MR_1_P
-sdrc_emr2_1:
- .word SDRC_EMR2_1_P
-sdrc_manual_1:
- .word SDRC_MANUAL_1_P
-ENTRY(es3_sdrc_fix_sz)
- .word . - es3_sdrc_fix
-
/* Function to call rom code to save secure ram context */
ENTRY(save_secure_ram_context)
stmfd sp!, {r1-r12, lr} @ save registers on stack
@@ -577,6 +535,56 @@ skip_l2_inval:
/* restore regs and return */
ldmfd sp!, {r0-r12, pc}
+
+/*
+ * Internal functions
+ */
+
+ .text
+ENTRY(es3_sdrc_fix)
+ ldr r4, sdrc_syscfg @ get config addr
+ ldr r5, [r4] @ get value
+ tst r5, #0x100 @ is part access blocked
+ it eq
+ biceq r5, r5, #0x100 @ clear bit if set
+ str r5, [r4] @ write back change
+ ldr r4, sdrc_mr_0 @ get config addr
+ ldr r5, [r4] @ get value
+ str r5, [r4] @ write back change
+ ldr r4, sdrc_emr2_0 @ get config addr
+ ldr r5, [r4] @ get value
+ str r5, [r4] @ write back change
+ ldr r4, sdrc_manual_0 @ get config addr
+ mov r5, #0x2 @ autorefresh command
+ str r5, [r4] @ kick off refreshes
+ ldr r4, sdrc_mr_1 @ get config addr
+ ldr r5, [r4] @ get value
+ str r5, [r4] @ write back change
+ ldr r4, sdrc_emr2_1 @ get config addr
+ ldr r5, [r4] @ get value
+ str r5, [r4] @ write back change
+ ldr r4, sdrc_manual_1 @ get config addr
+ mov r5, #0x2 @ autorefresh command
+ str r5, [r4] @ kick off refreshes
+ bx lr
+
+sdrc_syscfg:
+ .word SDRC_SYSCONFIG_P
+sdrc_mr_0:
+ .word SDRC_MR_0_P
+sdrc_emr2_0:
+ .word SDRC_EMR2_0_P
+sdrc_manual_0:
+ .word SDRC_MANUAL_0_P
+sdrc_mr_1:
+ .word SDRC_MR_1_P
+sdrc_emr2_1:
+ .word SDRC_EMR2_1_P
+sdrc_manual_1:
+ .word SDRC_MANUAL_1_P
+ENTRY(es3_sdrc_fix_sz)
+ .word . - es3_sdrc_fix
+
/* Make sure SDRC accesses are ok */
wait_sdrc_ok:
--
1.7.2.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
` (3 preceding siblings ...)
2010-12-18 15:44 ` [PATCH 4/7] OMAP3: re-organize " jean.pihet at newoldbits.com
@ 2010-12-18 15:44 ` jean.pihet at newoldbits.com
2010-12-18 15:44 ` [PATCH 6/7] OMAP3: add comments for low power code errata jean.pihet at newoldbits.com
` (2 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-18 15:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
- Reworked and simplified the execution paths for better
readability and to avoid duplication of code,
- Added comments on the entry and exit points and the interaction
with the ROM code for OFF mode restore,
- Reworked the existing comments for better readability.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/control.c | 9 +-
arch/arm/mach-omap2/sleep34xx.S | 317 +++++++++++++++++++++++----------------
2 files changed, 195 insertions(+), 131 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 728f268..f4b19ed 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -239,7 +239,14 @@ void omap3_save_scratchpad_contents(void)
struct omap3_scratchpad_prcm_block prcm_block_contents;
struct omap3_scratchpad_sdrc_block sdrc_block_contents;
- /* Populate the Scratchpad contents */
+ /*
+ * Populate the Scratchpad contents
+ *
+ * The "get_*restore_pointer" functions are used to provide a
+ * physical restore address where the ROM code jumps while waking
+ * up from MPU OFF/OSWR state.
+ * The restore pointer is stored into the scratchpad.
+ */
scratchpad_contents.boot_config_ptr = 0x0;
if (cpu_is_omap3630())
scratchpad_contents.public_restore_ptr =
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index beeb682..0e27429 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -71,6 +71,13 @@
* API functions
*/
+/*
+ * The "get_*restore_pointer" functions are used to provide a
+ * physical restore address where the ROM code jumps while waking
+ * up from MPU OFF/OSWR state.
+ * The restore pointer is stored into the scratchpad.
+ */
+
.text
/* Function call to get the restore pointer for resume from OFF */
ENTRY(get_restore_pointer)
@@ -102,7 +109,7 @@ ENTRY(get_es3_restore_pointer_sz)
/*
* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
* This function sets up a flag that will allow for this toggling to take
- * place on 3630. Hopefully some version in the future maynot need this
+ * place on 3630. Hopefully some version in the future may not need this.
*/
ENTRY(enable_omap3630_toggle_l2_on_restore)
stmfd sp!, {lr} @ save registers on stack
@@ -144,34 +151,162 @@ ENTRY(save_secure_ram_context_sz)
.word . - save_secure_ram_context
/*
+ * ======================
+ * == Idle entry point ==
+ * ======================
+ */
+
+/*
* Forces OMAP into idle state
*
- * omap34xx_suspend() - This bit of code just executes the WFI
- * for normal idles.
+ * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
+ * and executes the WFI instruction. Calling WFI effectively changes the
+ * power domains states to the desired target power states.
+ *
*
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- * wakes up it continues execution at the point it went to sleep.
+ * Notes:
+ * - this code gets copied to internal SRAM at boot. The execution pointer
+ * in SRAM is _omap_sram_idle.
+ * - when the OMAP wakes up it continues at different execution points
+ * depending on the low power mode (non-OFF vs OFF modes),
+ * cf. 'Resume path for xxx mode' comments.
*/
ENTRY(omap34xx_cpu_suspend)
stmfd sp!, {r0-r12, lr} @ save registers on stack
- /* r0 contains restore pointer in sdram */
- /* r1 contains information about saving context */
- ldr r4, sdrc_power @ read the SDRC_POWER register
- ldr r5, [r4] @ read the contents of SDRC_POWER
- orr r5, r5, #0x40 @ enable self refresh on idle req
- str r5, [r4] @ write back to SDRC_POWER register
+ /*
+ * r0 contains restore pointer in sdram
+ * r1 contains information about saving context:
+ * 0 - No context lost
+ * 1 - Only L1 and logic lost
+ * 2 - Only L2 lost
+ * 3 - Both L1 and L2 lost
+ */
+ /* Directly jump to WFI is the context save is not required */
cmp r1, #0x0
- /* If context save is required, do that and execute wfi */
- bne save_context_wfi
+ beq omap3_do_wfi
+
+ /* Otherwise fall through to the save context code */
+save_context_wfi:
+ mov r8, r0 @ Store SDRAM address in r8
+ mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
+ mov r4, #0x1 @ Number of parameters for restore call
+ stmia r8!, {r4-r5} @ Push parameters for restore call
+ mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
+ stmia r8!, {r4-r5} @ Push parameters for restore call
+
+ /* Check what that target sleep state is from r1 */
+ cmp r1, #0x2 @ Only L2 lost, no need to save context
+ beq clean_caches
+
+l1_logic_lost:
+ /* Store sp and spsr to SDRAM */
+ mov r4, sp
+ mrs r5, spsr
+ mov r6, lr
+ stmia r8!, {r4-r6}
+ /* Save all ARM registers */
+ /* Coprocessor access control register */
+ mrc p15, 0, r6, c1, c0, 2
+ stmia r8!, {r6}
+ /* TTBR0, TTBR1 and Translation table base control */
+ mrc p15, 0, r4, c2, c0, 0
+ mrc p15, 0, r5, c2, c0, 1
+ mrc p15, 0, r6, c2, c0, 2
+ stmia r8!, {r4-r6}
+ /*
+ * Domain access control register, data fault status register,
+ * and instruction fault status register
+ */
+ mrc p15, 0, r4, c3, c0, 0
+ mrc p15, 0, r5, c5, c0, 0
+ mrc p15, 0, r6, c5, c0, 1
+ stmia r8!, {r4-r6}
+ /*
+ * Data aux fault status register, instruction aux fault status,
+ * data fault address register and instruction fault address register
+ */
+ mrc p15, 0, r4, c5, c1, 0
+ mrc p15, 0, r5, c5, c1, 1
+ mrc p15, 0, r6, c6, c0, 0
+ mrc p15, 0, r7, c6, c0, 2
+ stmia r8!, {r4-r7}
+ /*
+ * user r/w thread and process ID, user r/o thread and process ID,
+ * priv only thread and process ID, cache size selection
+ */
+ mrc p15, 0, r4, c13, c0, 2
+ mrc p15, 0, r5, c13, c0, 3
+ mrc p15, 0, r6, c13, c0, 4
+ mrc p15, 2, r7, c0, c0, 0
+ stmia r8!, {r4-r7}
+ /* Data TLB lockdown, instruction TLB lockdown registers */
+ mrc p15, 0, r5, c10, c0, 0
+ mrc p15, 0, r6, c10, c0, 1
+ stmia r8!, {r5-r6}
+ /* Secure or non secure vector base address, FCSE PID, Context PID*/
+ mrc p15, 0, r4, c12, c0, 0
+ mrc p15, 0, r5, c13, c0, 0
+ mrc p15, 0, r6, c13, c0, 1
+ stmia r8!, {r4-r6}
+ /* Primary remap, normal remap registers */
+ mrc p15, 0, r4, c10, c2, 0
+ mrc p15, 0, r5, c10, c2, 1
+ stmia r8!,{r4-r5}
+
+ /* Store current cpsr*/
+ mrs r2, cpsr
+ stmia r8!, {r2}
+
+ mrc p15, 0, r4, c1, c0, 0
+ /* save control register */
+ stmia r8!, {r4}
+
+clean_caches:
+ /*
+ * Clean Data or unified cache to POU
+ * How to invalidate only L1 cache???? - #FIX_ME#
+ * mcr p15, 0, r11, c7, c11, 1
+ */
+ cmp r1, #0x1 @ Check whether L2 inval is required
+ beq omap3_do_wfi
+
+clean_l2:
+ /*
+ * jump out to kernel flush routine
+ * - reuse that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
+ */
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
+
+omap3_do_wfi:
+ ldr r4, sdrc_power @ read the SDRC_POWER register
+ ldr r5, [r4] @ read the contents of SDRC_POWER
+ orr r5, r5, #0x40 @ enable self refresh on idle req
+ str r5, [r4] @ write back to SDRC_POWER register
+
/* Data memory barrier and Data sync barrier */
mov r1, #0
mcr p15, 0, r1, c7, c10, 4
mcr p15, 0, r1, c7, c10, 5
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
wfi @ wait for interrupt
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
nop
nop
nop
@@ -184,7 +319,29 @@ ENTRY(omap34xx_cpu_suspend)
nop
bl wait_sdrc_ok
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
+
+
+/*
+ * ==============================
+ * == Resume path for OFF mode ==
+ * ==============================
+ */
+
+/*
+ * The restore_* functions are called by the ROM code
+ * when back from WFI in OFF mode.
+ * Cf. the get_*restore_pointer functions.
+ *
+ * restore_es3: applies to 34xx >= ES3.0
+ * restore_3630: applies to 36xx
+ * restore: common code for 3xxx
+ */
restore_es3:
ldr r5, pm_prepwstst_core_p
ldr r4, [r5]
@@ -214,12 +371,17 @@ restore_3630:
ldr r1, control_mem_rta
mov r2, #OMAP36XX_RTA_DISABLE
str r2, [r1]
- /* Fall thru for the remaining logic */
+
+ /* Fall through to common code for the remaining logic */
+
restore:
- /* Check what was the reason for mpu reset and store the reason in r9*/
- /* 1 - Only L1 and logic lost */
- /* 2 - Only L2 lost - In this case, we wont be here */
- /* 3 - Both L1 and L2 lost */
+ /*
+ * Check what was the reason for mpu reset and store the reason in r9:
+ * 0 - No context lost
+ * 1 - Only L1 and logic lost
+ * 2 - Only L2 lost - In this case, we wont be here
+ * 3 - Both L1 and L2 lost
+ */
ldr r1, pm_pwstctrl_mpu
ldr r2, [r1]
and r2, r2, #0x3
@@ -422,118 +584,12 @@ usettbr0:
and r4, r2
mcr p15, 0, r4, c1, c0, 0
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
ldmfd sp!, {r0-r12, pc} @ restore regs and return
-save_context_wfi:
- mov r8, r0 /* Store SDRAM address in r8 */
- mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
- mov r4, #0x1 @ Number of parameters for restore call
- stmia r8!, {r4-r5} @ Push parameters for restore call
- mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
- stmia r8!, {r4-r5} @ Push parameters for restore call
- /* Check what that target sleep state is:stored in r1*/
- /* 1 - Only L1 and logic lost */
- /* 2 - Only L2 lost */
- /* 3 - Both L1 and L2 lost */
- cmp r1, #0x2 /* Only L2 lost */
- beq clean_l2
- cmp r1, #0x1 /* L2 retained */
- /* r9 stores whether to clean L2 or not*/
- moveq r9, #0x0 /* Dont Clean L2 */
- movne r9, #0x1 /* Clean L2 */
-l1_logic_lost:
- /* Store sp and spsr to SDRAM */
- mov r4, sp
- mrs r5, spsr
- mov r6, lr
- stmia r8!, {r4-r6}
- /* Save all ARM registers */
- /* Coprocessor access control register */
- mrc p15, 0, r6, c1, c0, 2
- stmia r8!, {r6}
- /* TTBR0, TTBR1 and Translation table base control */
- mrc p15, 0, r4, c2, c0, 0
- mrc p15, 0, r5, c2, c0, 1
- mrc p15, 0, r6, c2, c0, 2
- stmia r8!, {r4-r6}
- /* Domain access control register, data fault status register,
- and instruction fault status register */
- mrc p15, 0, r4, c3, c0, 0
- mrc p15, 0, r5, c5, c0, 0
- mrc p15, 0, r6, c5, c0, 1
- stmia r8!, {r4-r6}
- /* Data aux fault status register, instruction aux fault status,
- datat fault address register and instruction fault address register*/
- mrc p15, 0, r4, c5, c1, 0
- mrc p15, 0, r5, c5, c1, 1
- mrc p15, 0, r6, c6, c0, 0
- mrc p15, 0, r7, c6, c0, 2
- stmia r8!, {r4-r7}
- /* user r/w thread and process ID, user r/o thread and process ID,
- priv only thread and process ID, cache size selection */
- mrc p15, 0, r4, c13, c0, 2
- mrc p15, 0, r5, c13, c0, 3
- mrc p15, 0, r6, c13, c0, 4
- mrc p15, 2, r7, c0, c0, 0
- stmia r8!, {r4-r7}
- /* Data TLB lockdown, instruction TLB lockdown registers */
- mrc p15, 0, r5, c10, c0, 0
- mrc p15, 0, r6, c10, c0, 1
- stmia r8!, {r5-r6}
- /* Secure or non secure vector base address, FCSE PID, Context PID*/
- mrc p15, 0, r4, c12, c0, 0
- mrc p15, 0, r5, c13, c0, 0
- mrc p15, 0, r6, c13, c0, 1
- stmia r8!, {r4-r6}
- /* Primary remap, normal remap registers */
- mrc p15, 0, r4, c10, c2, 0
- mrc p15, 0, r5, c10, c2, 1
- stmia r8!,{r4-r5}
-
- /* Store current cpsr*/
- mrs r2, cpsr
- stmia r8!, {r2}
-
- mrc p15, 0, r4, c1, c0, 0
- /* save control register */
- stmia r8!, {r4}
-clean_caches:
- /* Clean Data or unified cache to POU*/
- /* How to invalidate only L1 cache???? - #FIX_ME# */
- /* mcr p15, 0, r11, c7, c11, 1 */
- cmp r9, #1 /* Check whether L2 inval is required or not*/
- bne skip_l2_inval
-clean_l2:
- /*
- * Jump out to kernel flush routine
- * - reuse that code is better
- * - it executes in a cached space so is faster than refetch per-block
- * - should be faster and will change with kernel
- * - 'might' have to copy address, load and jump to it
- */
- ldr r1, kernel_flush
- mov lr, pc
- bx r1
-
-skip_l2_inval:
- /* Data memory barrier and Data sync barrier */
- mov r1, #0
- mcr p15, 0, r1, c7, c10, 4
- mcr p15, 0, r1, c7, c10, 5
-
- wfi @ wait for interrupt
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- bl wait_sdrc_ok
- /* restore regs and return */
- ldmfd sp!, {r0-r12, pc}
/*
@@ -683,5 +739,6 @@ kick_counter:
.word 0
wait_dll_lock_counter:
.word 0
+
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.7.2.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 6/7] OMAP3: add comments for low power code errata
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
` (4 preceding siblings ...)
2010-12-18 15:44 ` [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths jean.pihet at newoldbits.com
@ 2010-12-18 15:44 ` jean.pihet at newoldbits.com
2010-12-18 15:49 ` [PATCH 7/7] OMAP3: ASM sleep code format rework jean.pihet at newoldbits.com
2010-12-18 22:56 ` [PATCH 0/7 v6] OMAP3: clean up ASM sleep code Nishanth Menon
7 siblings, 0 replies; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-18 15:44 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
Errata covered:
- 1.157 & 1.185
- i443
- i581
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/pm34xx.c | 4 ++--
arch/arm/mach-omap2/sleep34xx.S | 11 +++++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index adc0917..267f015 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -148,7 +148,7 @@ static void omap3_core_save_context(void)
/*
* Force write last pad into memory, as this can fail in some
- * cases according to erratas 1.157, 1.185
+ * cases according to errata 1.157, 1.185
*/
omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
@@ -446,7 +446,7 @@ void omap_sram_idle(void)
/*
* On EMU/HS devices ROM code restores a SRDC value
* from scratchpad which has automatic self refresh on timeout
- * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
+ * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
* Hence store/restore the SDRC_POWER register here.
*/
if (omap_rev() >= OMAP3430_REV_ES3_0 &&
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 0e27429..7a63da2 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -596,6 +596,7 @@ usettbr0:
* Internal functions
*/
+/* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
.text
ENTRY(es3_sdrc_fix)
ldr r4, sdrc_syscfg @ get config addr
@@ -641,6 +642,16 @@ sdrc_manual_1:
ENTRY(es3_sdrc_fix_sz)
.word . - es3_sdrc_fix
+/*
+ * This function implements the erratum ID i581 WA:
+ * SDRC state restore before accessing the SDRAM
+ *
+ * Only used at return from non-OFF mode. For OFF
+ * mode the ROM code configures the SDRC and
+ * the DPLL before calling the restore code directly
+ * from DDR.
+ */
+
/* Make sure SDRC accesses are ok */
wait_sdrc_ok:
--
1.7.2.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 7/7] OMAP3: ASM sleep code format rework
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
` (5 preceding siblings ...)
2010-12-18 15:44 ` [PATCH 6/7] OMAP3: add comments for low power code errata jean.pihet at newoldbits.com
@ 2010-12-18 15:49 ` jean.pihet at newoldbits.com
2010-12-18 22:56 ` [PATCH 0/7 v6] OMAP3: clean up ASM sleep code Nishanth Menon
7 siblings, 0 replies; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-18 15:49 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
Cosmetic fixes to the code:
- white spaces and tabs,
- alignement,
- comments rephrase and typos,
- multi-line comments
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/sleep34xx.S | 224 ++++++++++++++++++++-------------------
1 files changed, 117 insertions(+), 107 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 7a63da2..29f4bf7 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -1,6 +1,4 @@
/*
- * linux/arch/arm/mach-omap2/sleep.S
- *
* (C) Copyright 2007
* Texas Instruments
* Karthik Dasu <karthik-dp@ti.com>
@@ -81,20 +79,20 @@
.text
/* Function call to get the restore pointer for resume from OFF */
ENTRY(get_restore_pointer)
- stmfd sp!, {lr} @ save registers on stack
+ stmfd sp!, {lr} @ save registers on stack
adr r0, restore
- ldmfd sp!, {pc} @ restore regs and return
+ ldmfd sp!, {pc} @ restore regs and return
ENTRY(get_restore_pointer_sz)
- .word . - get_restore_pointer
+ .word . - get_restore_pointer
.text
/* Function call to get the restore pointer for 3630 resume from OFF */
ENTRY(get_omap3630_restore_pointer)
- stmfd sp!, {lr} @ save registers on stack
+ stmfd sp!, {lr} @ save registers on stack
adr r0, restore_3630
- ldmfd sp!, {pc} @ restore regs and return
+ ldmfd sp!, {pc} @ restore regs and return
ENTRY(get_omap3630_restore_pointer_sz)
- .word . - get_omap3630_restore_pointer
+ .word . - get_omap3630_restore_pointer
.text
/* Function call to get the restore pointer for ES3 to resume from OFF */
@@ -112,16 +110,16 @@ ENTRY(get_es3_restore_pointer_sz)
* place on 3630. Hopefully some version in the future may not need this.
*/
ENTRY(enable_omap3630_toggle_l2_on_restore)
- stmfd sp!, {lr} @ save registers on stack
+ stmfd sp!, {lr} @ save registers on stack
/* Setup so that we will disable and enable l2 */
mov r1, #0x1
str r1, l2dis_3630
- ldmfd sp!, {pc} @ restore regs and return
+ ldmfd sp!, {pc} @ restore regs and return
+ .text
/* Function to call rom code to save secure ram context */
ENTRY(save_secure_ram_context)
stmfd sp!, {r1-r12, lr} @ save registers on stack
-
adr r3, api_params @ r3 points to parameters
str r0, [r3,#0x4] @ r0 has sdram address
ldr r12, high_mask
@@ -165,14 +163,14 @@ ENTRY(save_secure_ram_context_sz)
*
*
* Notes:
- * - this code gets copied to internal SRAM at boot. The execution pointer
- * in SRAM is _omap_sram_idle.
+ * - this code gets copied to internal SRAM at boot and after wake-up
+ * from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
* - when the OMAP wakes up it continues at different execution points
* depending on the low power mode (non-OFF vs OFF modes),
* cf. 'Resume path for xxx mode' comments.
*/
ENTRY(omap34xx_cpu_suspend)
- stmfd sp!, {r0-r12, lr} @ save registers on stack
+ stmfd sp!, {r0-r12, lr} @ save registers on stack
/*
* r0 contains restore pointer in sdram
@@ -280,9 +278,9 @@ clean_l2:
* - should be faster and will change with kernel
* - 'might' have to copy address, load and jump to it
*/
- ldr r1, kernel_flush
- mov lr, pc
- bx r1
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
omap3_do_wfi:
ldr r4, sdrc_power @ read the SDRC_POWER register
@@ -375,18 +373,18 @@ restore_3630:
/* Fall through to common code for the remaining logic */
restore:
- /*
+ /*
* Check what was the reason for mpu reset and store the reason in r9:
* 0 - No context lost
- * 1 - Only L1 and logic lost
- * 2 - Only L2 lost - In this case, we wont be here
- * 3 - Both L1 and L2 lost
+ * 1 - Only L1 and logic lost
+ * 2 - Only L2 lost - In this case, we wont be here
+ * 3 - Both L1 and L2 lost
*/
- ldr r1, pm_pwstctrl_mpu
+ ldr r1, pm_pwstctrl_mpu
ldr r2, [r1]
- and r2, r2, #0x3
- cmp r2, #0x0 @ Check if target power state was OFF or RET
- moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
+ and r2, r2, #0x3
+ cmp r2, #0x0 @ Check if target power state was OFF or RET
+ moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
bne logic_l1_restore
@@ -402,71 +400,74 @@ skipl2dis:
and r1, #0x700
cmp r1, #0x300
beq l2_inv_gp
- mov r0, #40 @ set service ID for PPA
- mov r12, r0 @ copy secure Service ID in r12
- mov r1, #0 @ set task id for ROM code in r1
- mov r2, #4 @ set some flags in r2, r6
+ mov r0, #40 @ set service ID for PPA
+ mov r12, r0 @ copy secure Service ID in r12
+ mov r1, #0 @ set task id for ROM code in r1
+ mov r2, #4 @ set some flags in r2, r6
mov r6, #0xff
adr r3, l2_inv_api_params @ r3 points to dummy parameters
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
.word 0xE1600071 @ call SMI monitor (smi #1)
/* Write to Aux control register to set some bits */
- mov r0, #42 @ set service ID for PPA
- mov r12, r0 @ copy secure Service ID in r12
- mov r1, #0 @ set task id for ROM code in r1
- mov r2, #4 @ set some flags in r2, r6
+ mov r0, #42 @ set service ID for PPA
+ mov r12, r0 @ copy secure Service ID in r12
+ mov r1, #0 @ set task id for ROM code in r1
+ mov r2, #4 @ set some flags in r2, r6
mov r6, #0xff
ldr r4, scratchpad_base
- ldr r3, [r4, #0xBC] @ r3 points to parameters
+ ldr r3, [r4, #0xBC] @ r3 points to parameters
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
.word 0xE1600071 @ call SMI monitor (smi #1)
#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
/* Restore L2 aux control register */
- @ set service ID for PPA
+ @ set service ID for PPA
mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
- mov r12, r0 @ copy service ID in r12
- mov r1, #0 @ set task ID for ROM code in r1
- mov r2, #4 @ set some flags in r2, r6
+ mov r12, r0 @ copy service ID in r12
+ mov r1, #0 @ set task ID for ROM code in r1
+ mov r2, #4 @ set some flags in r2, r6
mov r6, #0xff
ldr r4, scratchpad_base
ldr r3, [r4, #0xBC]
- adds r3, r3, #8 @ r3 points to parameters
+ adds r3, r3, #8 @ r3 points to parameters
mcr p15, 0, r0, c7, c10, 4 @ data write barrier
mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
.word 0xE1600071 @ call SMI monitor (smi #1)
#endif
b logic_l1_restore
+
l2_inv_api_params:
- .word 0x1, 0x00
+ .word 0x1, 0x00
l2_inv_gp:
/* Execute smi to invalidate L2 cache */
- mov r12, #0x1 @ set up to invalide L2
-smi: .word 0xE1600070 @ Call SMI monitor (smieq)
+ mov r12, #0x1 @ set up to invalidate L2
+ .word 0xE1600070 @ Call SMI monitor (smieq)
/* Write to Aux control register to set some bits */
ldr r4, scratchpad_base
ldr r3, [r4,#0xBC]
ldr r0, [r3,#4]
mov r12, #0x3
- .word 0xE1600070 @ Call SMI monitor (smieq)
+ .word 0xE1600070 @ Call SMI monitor (smieq)
ldr r4, scratchpad_base
ldr r3, [r4,#0xBC]
ldr r0, [r3,#12]
mov r12, #0x2
- .word 0xE1600070 @ Call SMI monitor (smieq)
+ .word 0xE1600070 @ Call SMI monitor (smieq)
logic_l1_restore:
ldr r1, l2dis_3630
- cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
+ cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
bne skipl2reen
mrc p15, 0, r1, c1, c0, 1
- orr r1, r1, #2 @ re-enable L2 cache
+ orr r1, r1, #2 @ re-enable L2 cache
mcr p15, 0, r1, c1, c0, 1
skipl2reen:
mov r1, #0
- /* Invalidate all instruction caches to PoU
- * and flush branch target cache */
+ /*
+ * Invalidate all instruction caches to PoU
+ * and flush branch target cache
+ */
mcr p15, 0, r1, c7, c5, 0
ldr r4, scratchpad_base
@@ -487,33 +488,33 @@ skipl2reen:
MCR p15, 0, r6, c2, c0, 1
/* Translation table base control register */
MCR p15, 0, r7, c2, c0, 2
- /*domain access Control Register */
+ /* Domain access Control Register */
MCR p15, 0, r8, c3, c0, 0
- /* data fault status Register */
+ /* Data fault status Register */
MCR p15, 0, r9, c5, c0, 0
- ldmia r3!,{r4-r8}
- /* instruction fault status Register */
+ ldmia r3!,{r4-r8}
+ /* Instruction fault status Register */
MCR p15, 0, r4, c5, c0, 1
- /*Data Auxiliary Fault Status Register */
+ /* Data Auxiliary Fault Status Register */
MCR p15, 0, r5, c5, c1, 0
- /*Instruction Auxiliary Fault Status Register*/
+ /* Instruction Auxiliary Fault Status Register*/
MCR p15, 0, r6, c5, c1, 1
- /*Data Fault Address Register */
+ /* Data Fault Address Register */
MCR p15, 0, r7, c6, c0, 0
- /*Instruction Fault Address Register*/
+ /* Instruction Fault Address Register*/
MCR p15, 0, r8, c6, c0, 2
- ldmia r3!,{r4-r7}
+ ldmia r3!,{r4-r7}
- /* user r/w thread and process ID */
+ /* User r/w thread and process ID */
MCR p15, 0, r4, c13, c0, 2
- /* user ro thread and process ID */
+ /* User ro thread and process ID */
MCR p15, 0, r5, c13, c0, 3
- /*Privileged only thread and process ID */
+ /* Privileged only thread and process ID */
MCR p15, 0, r6, c13, c0, 4
- /* cache size selection */
+ /* Cache size selection */
MCR p15, 2, r7, c0, c0, 0
- ldmia r3!,{r4-r8}
+ ldmia r3!,{r4-r8}
/* Data TLB lockdown registers */
MCR p15, 0, r4, c10, c0, 0
/* Instruction TLB lockdown registers */
@@ -525,26 +526,27 @@ skipl2reen:
/* Context PID */
MCR p15, 0, r8, c13, c0, 1
- ldmia r3!,{r4-r5}
- /* primary memory remap register */
+ ldmia r3!,{r4-r5}
+ /* Primary memory remap register */
MCR p15, 0, r4, c10, c2, 0
- /*normal memory remap register */
+ /* Normal memory remap register */
MCR p15, 0, r5, c10, c2, 1
/* Restore cpsr */
- ldmia r3!,{r4} /*load CPSR from SDRAM*/
- msr cpsr, r4 /*store cpsr */
+ ldmia r3!,{r4} @ load CPSR from SDRAM
+ msr cpsr, r4 @ store cpsr
/* Enabling MMU here */
- mrc p15, 0, r7, c2, c0, 2 /* Read TTBRControl */
- /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1*/
+ mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
+ /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
and r7, #0x7
cmp r7, #0x0
beq usettbr0
ttbr_error:
- /* More work needs to be done to support N[0:2] value other than 0
- * So looping here so that the error can be detected
- */
+ /*
+ * More work needs to be done to support N[0:2] value other than 0
+ * So looping here so that the error can be detected
+ */
b ttbr_error
usettbr0:
mrc p15, 0, r2, c2, c0, 0
@@ -552,21 +554,25 @@ usettbr0:
and r2, r5
mov r4, pc
ldr r5, table_index_mask
- and r4, r5 /* r4 = 31 to 20 bits of pc */
+ and r4, r5 @ r4 = 31 to 20 bits of pc
/* Extract the value to be written to table entry */
ldr r1, table_entry
- add r1, r1, r4 /* r1 has value to be written to table entry*/
+ /* r1 has the value to be written to table entry*/
+ add r1, r1, r4
/* Getting the address of table entry to modify */
lsr r4, #18
- add r2, r4 /* r2 has the location which needs to be modified */
+ /* r2 has the location which needs to be modified */
+ add r2, r4
/* Storing previous entry of location being modified */
ldr r5, scratchpad_base
ldr r4, [r2]
str r4, [r5, #0xC0]
/* Modify the table entry */
str r1, [r2]
- /* Storing address of entry being modified
- * - will be restored after enabling MMU */
+ /*
+ * Storing address of entry being modified
+ * - will be restored after enabling MMU
+ */
ldr r5, scratchpad_base
str r2, [r5, #0xC4]
@@ -575,8 +581,11 @@ usettbr0:
mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
- /* Restore control register but dont enable caches here*/
- /* Caches will be enabled after restoring MMU table entry */
+ /*
+ * Restore control register. This enables the MMU.
+ * The caches and prediction are not enabled here, they
+ * will be enabled after restoring the MMU table entry.
+ */
ldmia r3!, {r4}
/* Store previous value of control register in scratchpad */
str r4, [r5, #0xC8]
@@ -589,7 +598,7 @@ usettbr0:
* == Exit point from OFF mode ==
* ==============================
*/
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
/*
@@ -655,55 +664,56 @@ ENTRY(es3_sdrc_fix_sz)
/* Make sure SDRC accesses are ok */
wait_sdrc_ok:
-/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
+/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
ldr r4, cm_idlest_ckgen
wait_dpll3_lock:
ldr r5, [r4]
tst r5, #1
beq wait_dpll3_lock
- ldr r4, cm_idlest1_core
+ ldr r4, cm_idlest1_core
wait_sdrc_ready:
- ldr r5, [r4]
- tst r5, #0x2
- bne wait_sdrc_ready
+ ldr r5, [r4]
+ tst r5, #0x2
+ bne wait_sdrc_ready
/* allow DLL powerdown upon hw idle req */
- ldr r4, sdrc_power
- ldr r5, [r4]
- bic r5, r5, #0x40
- str r5, [r4]
-is_dll_in_lock_mode:
+ ldr r4, sdrc_power
+ ldr r5, [r4]
+ bic r5, r5, #0x40
+ str r5, [r4]
- /* Is dll in lock mode? */
- ldr r4, sdrc_dlla_ctrl
- ldr r5, [r4]
- tst r5, #0x4
- bxne lr
- /* wait till dll locks */
+is_dll_in_lock_mode:
+ /* Is dll in lock mode? */
+ ldr r4, sdrc_dlla_ctrl
+ ldr r5, [r4]
+ tst r5, #0x4
+ bxne lr @ Return if locked
+ /* wait till dll locks */
wait_dll_lock_timed:
ldr r4, wait_dll_lock_counter
add r4, r4, #1
str r4, wait_dll_lock_counter
ldr r4, sdrc_dlla_status
- mov r6, #8 /* Wait 20uS for lock */
+ /* Wait 20uS for lock */
+ mov r6, #8
wait_dll_lock:
subs r6, r6, #0x1
beq kick_dll
- ldr r5, [r4]
- and r5, r5, #0x4
- cmp r5, #0x4
- bne wait_dll_lock
- bx lr
+ ldr r5, [r4]
+ and r5, r5, #0x4
+ cmp r5, #0x4
+ bne wait_dll_lock
+ bx lr @ Return when locked
/* disable/reenable DLL if not locked */
kick_dll:
ldr r4, sdrc_dlla_ctrl
ldr r5, [r4]
mov r6, r5
- bic r6, #(1<<3) /* disable dll */
+ bic r6, #(1<<3) @ disable dll
str r6, [r4]
dsb
- orr r6, r6, #(1<<3) /* enable dll */
+ orr r6, r6, #(1<<3) @ enable dll
str r6, [r4]
dsb
ldr r4, kick_counter
@@ -728,7 +738,7 @@ scratchpad_base:
sram_base:
.word SRAM_BASE_P + 0x8000
sdrc_power:
- .word SDRC_POWER_V
+ .word SDRC_POWER_V
ttbrbit_mask:
.word 0xFFFFC000
table_index_mask:
@@ -742,9 +752,9 @@ control_stat:
control_mem_rta:
.word CONTROL_MEM_RTA_CTRL
kernel_flush:
- .word v7_flush_dcache_all
+ .word v7_flush_dcache_all
l2dis_3630:
- .word 0
+ .word 0
/* these 2 words need to be@the end !!! */
kick_counter:
.word 0
--
1.7.2.3
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 0/7 v6] OMAP3: clean up ASM sleep code
2010-12-18 15:44 [PATCH 0/7 v6] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
` (6 preceding siblings ...)
2010-12-18 15:49 ` [PATCH 7/7] OMAP3: ASM sleep code format rework jean.pihet at newoldbits.com
@ 2010-12-18 22:56 ` Nishanth Menon
2010-12-20 8:29 ` Jean Pihet
7 siblings, 1 reply; 18+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:56 UTC (permalink / raw)
To: linux-arm-kernel
jean.pihet at newoldbits.com had written, on 12/18/2010 09:44 AM, the
following:
>
> Applies on top of Nishant's latest idle path errata fixes step 2,
> cf. http://marc.info/?l=linux-omap&m=129139584919242&w=2
>
> Jean Pihet (7):
> OMAP3: remove unused code from the ASM sleep code
> OMAP2+: use global values for the SRAM PA addresses
> OMAP3: remove hardcoded values from the ASM sleep code
> OMAP3: re-organize the ASM sleep code
> OMAP3: rework of the ASM sleep code execution paths
> OMAP3: add comments for low power code errata
> OMAP3: ASM sleep code format rework
>
just FYI - tested the series v6 as well with:
SDP3430 and SDP3630 with script:
http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality
Tested against v4 of my series. I have ensured that your series still
applies cleanly on top of my new series.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 0/7 v6] OMAP3: clean up ASM sleep code
2010-12-18 22:56 ` [PATCH 0/7 v6] OMAP3: clean up ASM sleep code Nishanth Menon
@ 2010-12-20 8:29 ` Jean Pihet
0 siblings, 0 replies; 18+ messages in thread
From: Jean Pihet @ 2010-12-20 8:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi Nishant,
On Sat, Dec 18, 2010 at 11:56 PM, Nishanth Menon <nm@ti.com> wrote:
> jean.pihet at newoldbits.com had written, on 12/18/2010 09:44 AM, the
> following:
>>
>> Applies on top of Nishant's latest idle path errata fixes step 2,
>> cf. http://marc.info/?l=linux-omap&m=129139584919242&w=2
>>
>> Jean Pihet (7):
>> ?OMAP3: remove unused code from the ASM sleep code
>> ?OMAP2+: use global values for the SRAM PA addresses
>> ?OMAP3: remove hardcoded values from the ASM sleep code
>> ?OMAP3: re-organize the ASM sleep code
>> ?OMAP3: rework of the ASM sleep code execution paths
>> ?OMAP3: add comments for low power code errata
>> ?OMAP3: ASM sleep code format rework
>>
>
> just FYI - tested the series v6 as well with:
> SDP3430 and SDP3630 with script:
> http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality
>
> Tested against v4 of my series. I have ensured that your series still
> applies cleanly on top of my new series.
Thanks for that!
Let me check and ack your latest v4 patches.
>
> --
> Regards,
> Nishanth Menon
>
>
Regards,
Jean
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-17 10:08 [PATCH 0/7 v5] " jean.pihet at newoldbits.com
@ 2010-12-17 10:08 ` jean.pihet at newoldbits.com
2010-12-17 10:37 ` Santosh Shilimkar
2010-12-17 15:35 ` Nishanth Menon
0 siblings, 2 replies; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-17 10:08 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
- Reworked and simplified the execution paths for better
readability and to avoid duplication of code,
- Added comments on the entry and exit points and the interaction
with the ROM code for OFF mode restore,
- Reworked the existing comments for better readability.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
---
arch/arm/mach-omap2/control.c | 9 +-
arch/arm/mach-omap2/sleep34xx.S | 313 +++++++++++++++++++++++----------------
2 files changed, 191 insertions(+), 131 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 728f268..f4b19ed 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -239,7 +239,14 @@ void omap3_save_scratchpad_contents(void)
struct omap3_scratchpad_prcm_block prcm_block_contents;
struct omap3_scratchpad_sdrc_block sdrc_block_contents;
- /* Populate the Scratchpad contents */
+ /*
+ * Populate the Scratchpad contents
+ *
+ * The "get_*restore_pointer" functions are used to provide a
+ * physical restore address where the ROM code jumps while waking
+ * up from MPU OFF/OSWR state.
+ * The restore pointer is stored into the scratchpad.
+ */
scratchpad_contents.boot_config_ptr = 0x0;
if (cpu_is_omap3630())
scratchpad_contents.public_restore_ptr =
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index beeb682..12061fd 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -71,6 +71,13 @@
* API functions
*/
+/*
+ * The "get_*restore_pointer" functions are used to provide a
+ * physical restore address where the ROM code jumps while waking
+ * up from MPU OFF/OSWR state.
+ * The restore pointer is stored into the scratchpad.
+ */
+
.text
/* Function call to get the restore pointer for resume from OFF */
ENTRY(get_restore_pointer)
@@ -102,7 +109,7 @@ ENTRY(get_es3_restore_pointer_sz)
/*
* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
* This function sets up a flag that will allow for this toggling to take
- * place on 3630. Hopefully some version in the future maynot need this
+ * place on 3630. Hopefully some version in the future may not need this.
*/
ENTRY(enable_omap3630_toggle_l2_on_restore)
stmfd sp!, {lr} @ save registers on stack
@@ -144,34 +151,158 @@ ENTRY(save_secure_ram_context_sz)
.word . - save_secure_ram_context
/*
+ * ======================
+ * == Idle entry point ==
+ * ======================
+ */
+
+/*
* Forces OMAP into idle state
*
- * omap34xx_suspend() - This bit of code just executes the WFI
- * for normal idles.
+ * omap34xx_suspend() - This bit of code saves the CPU context if needed
+ * and executes the WFI instruction
*
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- * wakes up it continues execution at the point it went to sleep.
+ * Notes:
+ * - this code gets copied to internal SRAM at boot.
+ * - when the OMAP wakes up it continues at different execution points
+ * depending on the low power mode (non-OFF vs OFF modes),
+ * cf. 'Resume path for xxx mode' comments.
*/
ENTRY(omap34xx_cpu_suspend)
stmfd sp!, {r0-r12, lr} @ save registers on stack
- /* r0 contains restore pointer in sdram */
- /* r1 contains information about saving context */
- ldr r4, sdrc_power @ read the SDRC_POWER register
- ldr r5, [r4] @ read the contents of SDRC_POWER
- orr r5, r5, #0x40 @ enable self refresh on idle req
- str r5, [r4] @ write back to SDRC_POWER register
+ /*
+ * r0 contains restore pointer in sdram
+ * r1 contains information about saving context:
+ * 0 - No context lost
+ * 1 - Only L1 and logic lost
+ * 2 - Only L2 lost
+ * 3 - Both L1 and L2 lost
+ */
+ /* Save context only if required */
cmp r1, #0x0
- /* If context save is required, do that and execute wfi */
- bne save_context_wfi
+ beq omap3_do_wfi
+
+save_context_wfi:
+ mov r8, r0 @ Store SDRAM address in r8
+ mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
+ mov r4, #0x1 @ Number of parameters for restore call
+ stmia r8!, {r4-r5} @ Push parameters for restore call
+ mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
+ stmia r8!, {r4-r5} @ Push parameters for restore call
+
+ /* Check what that target sleep state is from r1 */
+ cmp r1, #0x2 @ Only L2 lost, no need to save context
+ beq clean_caches
+
+l1_logic_lost:
+ /* Store sp and spsr to SDRAM */
+ mov r4, sp
+ mrs r5, spsr
+ mov r6, lr
+ stmia r8!, {r4-r6}
+ /* Save all ARM registers */
+ /* Coprocessor access control register */
+ mrc p15, 0, r6, c1, c0, 2
+ stmia r8!, {r6}
+ /* TTBR0, TTBR1 and Translation table base control */
+ mrc p15, 0, r4, c2, c0, 0
+ mrc p15, 0, r5, c2, c0, 1
+ mrc p15, 0, r6, c2, c0, 2
+ stmia r8!, {r4-r6}
+ /*
+ * Domain access control register, data fault status register,
+ * and instruction fault status register
+ */
+ mrc p15, 0, r4, c3, c0, 0
+ mrc p15, 0, r5, c5, c0, 0
+ mrc p15, 0, r6, c5, c0, 1
+ stmia r8!, {r4-r6}
+ /*
+ * Data aux fault status register, instruction aux fault status,
+ * data fault address register and instruction fault address register
+ */
+ mrc p15, 0, r4, c5, c1, 0
+ mrc p15, 0, r5, c5, c1, 1
+ mrc p15, 0, r6, c6, c0, 0
+ mrc p15, 0, r7, c6, c0, 2
+ stmia r8!, {r4-r7}
+ /*
+ * user r/w thread and process ID, user r/o thread and process ID,
+ * priv only thread and process ID, cache size selection
+ */
+ mrc p15, 0, r4, c13, c0, 2
+ mrc p15, 0, r5, c13, c0, 3
+ mrc p15, 0, r6, c13, c0, 4
+ mrc p15, 2, r7, c0, c0, 0
+ stmia r8!, {r4-r7}
+ /* Data TLB lockdown, instruction TLB lockdown registers */
+ mrc p15, 0, r5, c10, c0, 0
+ mrc p15, 0, r6, c10, c0, 1
+ stmia r8!, {r5-r6}
+ /* Secure or non secure vector base address, FCSE PID, Context PID*/
+ mrc p15, 0, r4, c12, c0, 0
+ mrc p15, 0, r5, c13, c0, 0
+ mrc p15, 0, r6, c13, c0, 1
+ stmia r8!, {r4-r6}
+ /* Primary remap, normal remap registers */
+ mrc p15, 0, r4, c10, c2, 0
+ mrc p15, 0, r5, c10, c2, 1
+ stmia r8!,{r4-r5}
+
+ /* Store current cpsr*/
+ mrs r2, cpsr
+ stmia r8!, {r2}
+
+ mrc p15, 0, r4, c1, c0, 0
+ /* save control register */
+ stmia r8!, {r4}
+
+clean_caches:
+ /*
+ * Clean Data or unified cache to POU
+ * How to invalidate only L1 cache???? - #FIX_ME#
+ * mcr p15, 0, r11, c7, c11, 1
+ */
+ cmp r1, #0x1 @ Check whether L2 inval is required
+ beq omap3_do_wfi
+
+clean_l2:
+ /*
+ * jump out to kernel flush routine
+ * - reuse that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
+ */
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
+
+omap3_do_wfi:
+ ldr r4, sdrc_power @ read the SDRC_POWER register
+ ldr r5, [r4] @ read the contents of SDRC_POWER
+ orr r5, r5, #0x40 @ enable self refresh on idle req
+ str r5, [r4] @ write back to SDRC_POWER register
+
/* Data memory barrier and Data sync barrier */
mov r1, #0
mcr p15, 0, r1, c7, c10, 4
mcr p15, 0, r1, c7, c10, 5
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
wfi @ wait for interrupt
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
nop
nop
nop
@@ -184,7 +315,29 @@ ENTRY(omap34xx_cpu_suspend)
nop
bl wait_sdrc_ok
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
+
+
+/*
+ * ==============================
+ * == Resume path for OFF mode ==
+ * ==============================
+ */
+
+/*
+ * The restore_* functions are called by the ROM code
+ * when back from WFI in OFF mode.
+ * Cf. the get_*restore_pointer functions.
+ *
+ * restore_es3: applies to 34xx >= ES3.0
+ * restore_3630: applies to 36xx
+ * restore: common code for 3xxx
+ */
restore_es3:
ldr r5, pm_prepwstst_core_p
ldr r4, [r5]
@@ -214,12 +367,17 @@ restore_3630:
ldr r1, control_mem_rta
mov r2, #OMAP36XX_RTA_DISABLE
str r2, [r1]
- /* Fall thru for the remaining logic */
+
+ /* Fall thru to common code for the remaining logic */
+
restore:
- /* Check what was the reason for mpu reset and store the reason in r9*/
- /* 1 - Only L1 and logic lost */
- /* 2 - Only L2 lost - In this case, we wont be here */
- /* 3 - Both L1 and L2 lost */
+ /*
+ * Check what was the reason for mpu reset and store the reason in r9:
+ * 0 - No context lost
+ * 1 - Only L1 and logic lost
+ * 2 - Only L2 lost - In this case, we wont be here
+ * 3 - Both L1 and L2 lost
+ */
ldr r1, pm_pwstctrl_mpu
ldr r2, [r1]
and r2, r2, #0x3
@@ -422,118 +580,12 @@ usettbr0:
and r4, r2
mcr p15, 0, r4, c1, c0, 0
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
ldmfd sp!, {r0-r12, pc} @ restore regs and return
-save_context_wfi:
- mov r8, r0 /* Store SDRAM address in r8 */
- mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
- mov r4, #0x1 @ Number of parameters for restore call
- stmia r8!, {r4-r5} @ Push parameters for restore call
- mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
- stmia r8!, {r4-r5} @ Push parameters for restore call
- /* Check what that target sleep state is:stored in r1*/
- /* 1 - Only L1 and logic lost */
- /* 2 - Only L2 lost */
- /* 3 - Both L1 and L2 lost */
- cmp r1, #0x2 /* Only L2 lost */
- beq clean_l2
- cmp r1, #0x1 /* L2 retained */
- /* r9 stores whether to clean L2 or not*/
- moveq r9, #0x0 /* Dont Clean L2 */
- movne r9, #0x1 /* Clean L2 */
-l1_logic_lost:
- /* Store sp and spsr to SDRAM */
- mov r4, sp
- mrs r5, spsr
- mov r6, lr
- stmia r8!, {r4-r6}
- /* Save all ARM registers */
- /* Coprocessor access control register */
- mrc p15, 0, r6, c1, c0, 2
- stmia r8!, {r6}
- /* TTBR0, TTBR1 and Translation table base control */
- mrc p15, 0, r4, c2, c0, 0
- mrc p15, 0, r5, c2, c0, 1
- mrc p15, 0, r6, c2, c0, 2
- stmia r8!, {r4-r6}
- /* Domain access control register, data fault status register,
- and instruction fault status register */
- mrc p15, 0, r4, c3, c0, 0
- mrc p15, 0, r5, c5, c0, 0
- mrc p15, 0, r6, c5, c0, 1
- stmia r8!, {r4-r6}
- /* Data aux fault status register, instruction aux fault status,
- datat fault address register and instruction fault address register*/
- mrc p15, 0, r4, c5, c1, 0
- mrc p15, 0, r5, c5, c1, 1
- mrc p15, 0, r6, c6, c0, 0
- mrc p15, 0, r7, c6, c0, 2
- stmia r8!, {r4-r7}
- /* user r/w thread and process ID, user r/o thread and process ID,
- priv only thread and process ID, cache size selection */
- mrc p15, 0, r4, c13, c0, 2
- mrc p15, 0, r5, c13, c0, 3
- mrc p15, 0, r6, c13, c0, 4
- mrc p15, 2, r7, c0, c0, 0
- stmia r8!, {r4-r7}
- /* Data TLB lockdown, instruction TLB lockdown registers */
- mrc p15, 0, r5, c10, c0, 0
- mrc p15, 0, r6, c10, c0, 1
- stmia r8!, {r5-r6}
- /* Secure or non secure vector base address, FCSE PID, Context PID*/
- mrc p15, 0, r4, c12, c0, 0
- mrc p15, 0, r5, c13, c0, 0
- mrc p15, 0, r6, c13, c0, 1
- stmia r8!, {r4-r6}
- /* Primary remap, normal remap registers */
- mrc p15, 0, r4, c10, c2, 0
- mrc p15, 0, r5, c10, c2, 1
- stmia r8!,{r4-r5}
-
- /* Store current cpsr*/
- mrs r2, cpsr
- stmia r8!, {r2}
-
- mrc p15, 0, r4, c1, c0, 0
- /* save control register */
- stmia r8!, {r4}
-clean_caches:
- /* Clean Data or unified cache to POU*/
- /* How to invalidate only L1 cache???? - #FIX_ME# */
- /* mcr p15, 0, r11, c7, c11, 1 */
- cmp r9, #1 /* Check whether L2 inval is required or not*/
- bne skip_l2_inval
-clean_l2:
- /*
- * Jump out to kernel flush routine
- * - reuse that code is better
- * - it executes in a cached space so is faster than refetch per-block
- * - should be faster and will change with kernel
- * - 'might' have to copy address, load and jump to it
- */
- ldr r1, kernel_flush
- mov lr, pc
- bx r1
-
-skip_l2_inval:
- /* Data memory barrier and Data sync barrier */
- mov r1, #0
- mcr p15, 0, r1, c7, c10, 4
- mcr p15, 0, r1, c7, c10, 5
-
- wfi @ wait for interrupt
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- bl wait_sdrc_ok
- /* restore regs and return */
- ldmfd sp!, {r0-r12, pc}
/*
@@ -683,5 +735,6 @@ kick_counter:
.word 0
wait_dll_lock_counter:
.word 0
+
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-17 10:08 ` [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths jean.pihet at newoldbits.com
@ 2010-12-17 10:37 ` Santosh Shilimkar
2010-12-17 15:35 ` Nishanth Menon
1 sibling, 0 replies; 18+ messages in thread
From: Santosh Shilimkar @ 2010-12-17 10:37 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of jean.pihet at newoldbits.com
> Sent: Friday, December 17, 2010 3:38 PM
> To: linux-omap at vger.kernel.org
> Cc: khilman at deeprootsystems.com; linux-arm-kernel at lists.infradead.org;
> Jean Pihet
> Subject: [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
>
> From: Jean Pihet <j-pihet@ti.com>
>
> - Reworked and simplified the execution paths for better
> readability and to avoid duplication of code,
> - Added comments on the entry and exit points and the interaction
> with the ROM code for OFF mode restore,
> - Reworked the existing comments for better readability.
>
> Tested on N900 and Beagleboard with full RET and OFF modes,
> using cpuidle and suspend.
>
> Signed-off-by: Jean Pihet <j-pihet@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/control.c | 9 +-
> arch/arm/mach-omap2/sleep34xx.S | 313
+++++++++++++++++++++++-----------
> -----
> 2 files changed, 191 insertions(+), 131 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c
b/arch/arm/mach-omap2/control.c
> index 728f268..f4b19ed 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -239,7 +239,14 @@ void omap3_save_scratchpad_contents(void)
> struct omap3_scratchpad_prcm_block prcm_block_contents;
> struct omap3_scratchpad_sdrc_block sdrc_block_contents;
>
> - /* Populate the Scratchpad contents */
> + /*
> + * Populate the Scratchpad contents
> + *
> + * The "get_*restore_pointer" functions are used to provide a
> + * physical restore address where the ROM code jumps while waking
> + * up from MPU OFF/OSWR state.
> + * The restore pointer is stored into the scratchpad.
> + */
> scratchpad_contents.boot_config_ptr = 0x0;
> if (cpu_is_omap3630())
> scratchpad_contents.public_restore_ptr =
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index beeb682..12061fd 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -71,6 +71,13 @@
> * API functions
> */
>
> +/*
> + * The "get_*restore_pointer" functions are used to provide a
> + * physical restore address where the ROM code jumps while waking
> + * up from MPU OFF/OSWR state.
> + * The restore pointer is stored into the scratchpad.
> + */
> +
> .text
> /* Function call to get the restore pointer for resume from OFF */
> ENTRY(get_restore_pointer)
> @@ -102,7 +109,7 @@ ENTRY(get_es3_restore_pointer_sz)
> /*
> * L2 cache needs to be toggled for stable OFF mode functionality on
3630.
> * This function sets up a flag that will allow for this toggling to
take
> - * place on 3630. Hopefully some version in the future maynot need this
> + * place on 3630. Hopefully some version in the future may not need
this.
> */
> ENTRY(enable_omap3630_toggle_l2_on_restore)
> stmfd sp!, {lr} @ save registers on stack
> @@ -144,34 +151,158 @@ ENTRY(save_secure_ram_context_sz)
> .word . - save_secure_ram_context
>
> /*
> + * ======================
> + * == Idle entry point ==
> + * ======================
> + */
> +
> +/*
> * Forces OMAP into idle state
> *
> - * omap34xx_suspend() - This bit of code just executes the WFI
> - * for normal idles.
> + * omap34xx_suspend() - This bit of code saves the CPU context if
needed
> + * and executes the WFI instruction
> *
> - * Note: This code get's copied to internal SRAM at boot. When the OMAP
> - * wakes up it continues execution at the point it went to sleep.
> + * Notes:
> + * - this code gets copied to internal SRAM at boot.
> + * - when the OMAP wakes up it continues at different execution points
> + * depending on the low power mode (non-OFF vs OFF modes),
> + * cf. 'Resume path for xxx mode' comments.
> */
> ENTRY(omap34xx_cpu_suspend)
> stmfd sp!, {r0-r12, lr} @ save registers on stack
>
> - /* r0 contains restore pointer in sdram */
> - /* r1 contains information about saving context */
> - ldr r4, sdrc_power @ read the SDRC_POWER register
> - ldr r5, [r4] @ read the contents of SDRC_POWER
> - orr r5, r5, #0x40 @ enable self refresh on idle req
> - str r5, [r4] @ write back to SDRC_POWER
register
> + /*
> + * r0 contains restore pointer in sdram
> + * r1 contains information about saving context:
> + * 0 - No context lost
> + * 1 - Only L1 and logic lost
> + * 2 - Only L2 lost
> + * 3 - Both L1 and L2 lost
> + */
>
> + /* Save context only if required */
> cmp r1, #0x0
> - /* If context save is required, do that and execute wfi */
> - bne save_context_wfi
> + beq omap3_do_wfi
> +
> +save_context_wfi:
> + mov r8, r0 @ Store SDRAM address in r8
> + mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
> + mov r4, #0x1 @ Number of parameters for restore
call
> + stmia r8!, {r4-r5} @ Push parameters for restore call
> + mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
> + stmia r8!, {r4-r5} @ Push parameters for restore call
> +
> + /* Check what that target sleep state is from r1 */
> + cmp r1, #0x2 @ Only L2 lost, no need to save
context
> + beq clean_caches
> +
> +l1_logic_lost:
> + /* Store sp and spsr to SDRAM */
> + mov r4, sp
> + mrs r5, spsr
> + mov r6, lr
> + stmia r8!, {r4-r6}
> + /* Save all ARM registers */
> + /* Coprocessor access control register */
> + mrc p15, 0, r6, c1, c0, 2
> + stmia r8!, {r6}
> + /* TTBR0, TTBR1 and Translation table base control */
> + mrc p15, 0, r4, c2, c0, 0
> + mrc p15, 0, r5, c2, c0, 1
> + mrc p15, 0, r6, c2, c0, 2
> + stmia r8!, {r4-r6}
> + /*
> + * Domain access control register, data fault status register,
> + * and instruction fault status register
> + */
> + mrc p15, 0, r4, c3, c0, 0
> + mrc p15, 0, r5, c5, c0, 0
> + mrc p15, 0, r6, c5, c0, 1
> + stmia r8!, {r4-r6}
> + /*
> + * Data aux fault status register, instruction aux fault status,
> + * data fault address register and instruction fault address
> register
> + */
> + mrc p15, 0, r4, c5, c1, 0
> + mrc p15, 0, r5, c5, c1, 1
> + mrc p15, 0, r6, c6, c0, 0
> + mrc p15, 0, r7, c6, c0, 2
> + stmia r8!, {r4-r7}
> + /*
> + * user r/w thread and process ID, user r/o thread and process ID,
> + * priv only thread and process ID, cache size selection
> + */
> + mrc p15, 0, r4, c13, c0, 2
> + mrc p15, 0, r5, c13, c0, 3
> + mrc p15, 0, r6, c13, c0, 4
> + mrc p15, 2, r7, c0, c0, 0
> + stmia r8!, {r4-r7}
> + /* Data TLB lockdown, instruction TLB lockdown registers */
> + mrc p15, 0, r5, c10, c0, 0
> + mrc p15, 0, r6, c10, c0, 1
> + stmia r8!, {r5-r6}
> + /* Secure or non secure vector base address, FCSE PID, Context
PID*/
> + mrc p15, 0, r4, c12, c0, 0
> + mrc p15, 0, r5, c13, c0, 0
> + mrc p15, 0, r6, c13, c0, 1
> + stmia r8!, {r4-r6}
> + /* Primary remap, normal remap registers */
> + mrc p15, 0, r4, c10, c2, 0
> + mrc p15, 0, r5, c10, c2, 1
> + stmia r8!,{r4-r5}
> +
> + /* Store current cpsr*/
> + mrs r2, cpsr
> + stmia r8!, {r2}
> +
> + mrc p15, 0, r4, c1, c0, 0
> + /* save control register */
> + stmia r8!, {r4}
> +
> +clean_caches:
> + /*
> + * Clean Data or unified cache to POU
> + * How to invalidate only L1 cache???? - #FIX_ME#
> + * mcr p15, 0, r11, c7, c11, 1
> + */
> + cmp r1, #0x1 @ Check whether L2 inval is
required
> + beq omap3_do_wfi
> +
> +clean_l2:
> + /*
> + * jump out to kernel flush routine
> + * - reuse that code is better
> + * - it executes in a cached space so is faster than refetch per-
> block
> + * - should be faster and will change with kernel
> + * - 'might' have to copy address, load and jump to it
> + */
> + ldr r1, kernel_flush
> + mov lr, pc
> + bx r1
> +
> +omap3_do_wfi:
> + ldr r4, sdrc_power @ read the SDRC_POWER register
> + ldr r5, [r4] @ read the contents of SDRC_POWER
> + orr r5, r5, #0x40 @ enable self refresh on idle req
> + str r5, [r4] @ write back to SDRC_POWER
register
> +
> /* Data memory barrier and Data sync barrier */
> mov r1, #0
> mcr p15, 0, r1, c7, c10, 4
> mcr p15, 0, r1, c7, c10, 5
>
> +/*
> + * ===================================
> + * == WFI instruction => Enter idle ==
> + * ===================================
> + */
> wfi @ wait for interrupt
>
> +/*
> + * ===================================
> + * == Resume path for non-OFF modes ==
> + * ===================================
> + */
> nop
> nop
> nop
> @@ -184,7 +315,29 @@ ENTRY(omap34xx_cpu_suspend)
> nop
> bl wait_sdrc_ok
>
> - ldmfd sp!, {r0-r12, pc} @ restore regs and return
> +/*
> + * ===================================
> + * == Exit point from non-OFF modes ==
> + * ===================================
> + */
> + ldmfd sp!, {r0-r12, pc} @ restore regs and return
> +
> +
> +/*
> + * ==============================
> + * == Resume path for OFF mode ==
> + * ==============================
> + */
> +
> +/*
> + * The restore_* functions are called by the ROM code
> + * when back from WFI in OFF mode.
> + * Cf. the get_*restore_pointer functions.
> + *
> + * restore_es3: applies to 34xx >= ES3.0
> + * restore_3630: applies to 36xx
> + * restore: common code for 3xxx
> + */
> restore_es3:
> ldr r5, pm_prepwstst_core_p
> ldr r4, [r5]
> @@ -214,12 +367,17 @@ restore_3630:
> ldr r1, control_mem_rta
> mov r2, #OMAP36XX_RTA_DISABLE
> str r2, [r1]
> - /* Fall thru for the remaining logic */
> +
> + /* Fall thru to common code for the remaining logic */
> +
> restore:
> - /* Check what was the reason for mpu reset and store the reason
> in r9*/
> - /* 1 - Only L1 and logic lost */
> - /* 2 - Only L2 lost - In this case, we wont be here */
> - /* 3 - Both L1 and L2 lost */
> + /*
> + * Check what was the reason for mpu reset and store the reason in
> r9:
> + * 0 - No context lost
> + * 1 - Only L1 and logic lost
> + * 2 - Only L2 lost - In this case, we wont be here
> + * 3 - Both L1 and L2 lost
> + */
> ldr r1, pm_pwstctrl_mpu
> ldr r2, [r1]
> and r2, r2, #0x3
> @@ -422,118 +580,12 @@ usettbr0:
> and r4, r2
> mcr p15, 0, r4, c1, c0, 0
>
> +/*
> + * ==============================
> + * == Exit point from OFF mode ==
> + * ==============================
> + */
> ldmfd sp!, {r0-r12, pc} @ restore regs and return
> -save_context_wfi:
> - mov r8, r0 /* Store SDRAM address in r8 */
> - mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
> - mov r4, #0x1 @ Number of parameters for restore
call
> - stmia r8!, {r4-r5} @ Push parameters for restore call
> - mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
> - stmia r8!, {r4-r5} @ Push parameters for restore call
> - /* Check what that target sleep state is:stored in r1*/
> - /* 1 - Only L1 and logic lost */
> - /* 2 - Only L2 lost */
> - /* 3 - Both L1 and L2 lost */
> - cmp r1, #0x2 /* Only L2 lost */
> - beq clean_l2
> - cmp r1, #0x1 /* L2 retained */
> - /* r9 stores whether to clean L2 or not*/
> - moveq r9, #0x0 /* Dont Clean L2 */
> - movne r9, #0x1 /* Clean L2 */
> -l1_logic_lost:
> - /* Store sp and spsr to SDRAM */
> - mov r4, sp
> - mrs r5, spsr
> - mov r6, lr
> - stmia r8!, {r4-r6}
> - /* Save all ARM registers */
> - /* Coprocessor access control register */
> - mrc p15, 0, r6, c1, c0, 2
> - stmia r8!, {r6}
> - /* TTBR0, TTBR1 and Translation table base control */
> - mrc p15, 0, r4, c2, c0, 0
> - mrc p15, 0, r5, c2, c0, 1
> - mrc p15, 0, r6, c2, c0, 2
> - stmia r8!, {r4-r6}
> - /* Domain access control register, data fault status register,
> - and instruction fault status register */
> - mrc p15, 0, r4, c3, c0, 0
> - mrc p15, 0, r5, c5, c0, 0
> - mrc p15, 0, r6, c5, c0, 1
> - stmia r8!, {r4-r6}
> - /* Data aux fault status register, instruction aux fault status,
> - datat fault address register and instruction fault address
> register*/
> - mrc p15, 0, r4, c5, c1, 0
> - mrc p15, 0, r5, c5, c1, 1
> - mrc p15, 0, r6, c6, c0, 0
> - mrc p15, 0, r7, c6, c0, 2
> - stmia r8!, {r4-r7}
> - /* user r/w thread and process ID, user r/o thread and process ID,
> - priv only thread and process ID, cache size selection */
> - mrc p15, 0, r4, c13, c0, 2
> - mrc p15, 0, r5, c13, c0, 3
> - mrc p15, 0, r6, c13, c0, 4
> - mrc p15, 2, r7, c0, c0, 0
> - stmia r8!, {r4-r7}
> - /* Data TLB lockdown, instruction TLB lockdown registers */
> - mrc p15, 0, r5, c10, c0, 0
> - mrc p15, 0, r6, c10, c0, 1
> - stmia r8!, {r5-r6}
> - /* Secure or non secure vector base address, FCSE PID, Context
PID*/
> - mrc p15, 0, r4, c12, c0, 0
> - mrc p15, 0, r5, c13, c0, 0
> - mrc p15, 0, r6, c13, c0, 1
> - stmia r8!, {r4-r6}
> - /* Primary remap, normal remap registers */
> - mrc p15, 0, r4, c10, c2, 0
> - mrc p15, 0, r5, c10, c2, 1
> - stmia r8!,{r4-r5}
> -
> - /* Store current cpsr*/
> - mrs r2, cpsr
> - stmia r8!, {r2}
> -
> - mrc p15, 0, r4, c1, c0, 0
> - /* save control register */
> - stmia r8!, {r4}
> -clean_caches:
> - /* Clean Data or unified cache to POU*/
> - /* How to invalidate only L1 cache???? - #FIX_ME# */
> - /* mcr p15, 0, r11, c7, c11, 1 */
> - cmp r9, #1 /* Check whether L2 inval is required or not*/
> - bne skip_l2_inval
> -clean_l2:
> - /*
> - * Jump out to kernel flush routine
> - * - reuse that code is better
> - * - it executes in a cached space so is faster than refetch per-
> block
> - * - should be faster and will change with kernel
> - * - 'might' have to copy address, load and jump to it
> - */
> - ldr r1, kernel_flush
> - mov lr, pc
> - bx r1
> -
> -skip_l2_inval:
> - /* Data memory barrier and Data sync barrier */
> - mov r1, #0
> - mcr p15, 0, r1, c7, c10, 4
> - mcr p15, 0, r1, c7, c10, 5
> -
> - wfi @ wait for interrupt
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - bl wait_sdrc_ok
> - /* restore regs and return */
> - ldmfd sp!, {r0-r12, pc}
>
>
> /*
> @@ -683,5 +735,6 @@ kick_counter:
> .word 0
> wait_dll_lock_counter:
> .word 0
> +
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-17 10:08 ` [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths jean.pihet at newoldbits.com
2010-12-17 10:37 ` Santosh Shilimkar
@ 2010-12-17 15:35 ` Nishanth Menon
2010-12-18 15:54 ` Jean Pihet
1 sibling, 1 reply; 18+ messages in thread
From: Nishanth Menon @ 2010-12-17 15:35 UTC (permalink / raw)
To: linux-arm-kernel
jean.pihet at newoldbits.com had written, on 12/17/2010 04:08 AM, the
following:
> From: Jean Pihet <j-pihet@ti.com>
>
> - Reworked and simplified the execution paths for better
> readability and to avoid duplication of code,
is it possible to split this good rewrite into logical chunks for better
and easier reviewability?
my suggestion clean each of the paths independently - like the code upto
wfi.. and then we can clean up the resume path as well separately.
> - Added comments on the entry and exit points and the interaction
> with the ROM code for OFF mode restore,
> - Reworked the existing comments for better readability.
thanks for doing this, but, just my suggestion, looking at the amount of
changes done in this patch -> if you can keep one patch for functional
change which is separate from cosmetic change (such as comment cleanup
and addition), it makes a reviewer's life easier :)
>
> Tested on N900 and Beagleboard with full RET and OFF modes,
> using cpuidle and suspend.
>
> Signed-off-by: Jean Pihet <j-pihet@ti.com>
> ---
> arch/arm/mach-omap2/control.c | 9 +-
> arch/arm/mach-omap2/sleep34xx.S | 313 +++++++++++++++++++++++----------------
> 2 files changed, 191 insertions(+), 131 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 728f268..f4b19ed 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -239,7 +239,14 @@ void omap3_save_scratchpad_contents(void)
> struct omap3_scratchpad_prcm_block prcm_block_contents;
> struct omap3_scratchpad_sdrc_block sdrc_block_contents;
>
> - /* Populate the Scratchpad contents */
> + /*
> + * Populate the Scratchpad contents
> + *
> + * The "get_*restore_pointer" functions are used to provide a
> + * physical restore address where the ROM code jumps while waking
> + * up from MPU OFF/OSWR state.
Just curious: we dont have OSWR(open switch retention) in l-o unless I
am mistaken.. we have cswr (closed switch retention).
> + * The restore pointer is stored into the scratchpad.
> + */
> scratchpad_contents.boot_config_ptr = 0x0;
> if (cpu_is_omap3630())
> scratchpad_contents.public_restore_ptr =
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index beeb682..12061fd 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -71,6 +71,13 @@
> * API functions
> */
>
> +/*
> + * The "get_*restore_pointer" functions are used to provide a
> + * physical restore address where the ROM code jumps while waking
> + * up from MPU OFF/OSWR state.
> + * The restore pointer is stored into the scratchpad.
> + */
> +
we need to cleanup comments such as those used below:
> .text
> /* Function call to get the restore pointer for resume from OFF */
^^^^
may be make it explicit what the difference for get_restore_pointer is etc..
> ENTRY(get_restore_pointer)
> @@ -102,7 +109,7 @@ ENTRY(get_es3_restore_pointer_sz)
> /*
> * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
> * This function sets up a flag that will allow for this toggling to take
> - * place on 3630. Hopefully some version in the future maynot need this
> + * place on 3630. Hopefully some version in the future may not need this.
I think we should split the patch up for the comment cleanup -> it is a
little nuisance trying to review the actual functional change mixed with
comment cleanups together..
> */
> ENTRY(enable_omap3630_toggle_l2_on_restore)
> stmfd sp!, {lr} @ save registers on stack
> @@ -144,34 +151,158 @@ ENTRY(save_secure_ram_context_sz)
> .word . - save_secure_ram_context
>
> /*
> + * ======================
> + * == Idle entry point ==
> + * ======================
> + */
> +
> +/*
> * Forces OMAP into idle state
> *
> - * omap34xx_suspend() - This bit of code just executes the WFI
> - * for normal idles.
> + * omap34xx_suspend() - This bit of code saves the CPU context if needed
> + * and executes the WFI instruction
since we are cleaning up, I might as well suggest - what condition do we
save the CPU context might be worth mentioning. is this called during
RET transition or OFF transition is not clear..
> *
> - * Note: This code get's copied to internal SRAM at boot. When the OMAP
> - * wakes up it continues execution at the point it went to sleep.
> + * Notes:
> + * - this code gets copied to internal SRAM at boot.
> + * - when the OMAP wakes up it continues at different execution points
> + * depending on the low power mode (non-OFF vs OFF modes),
> + * cf. 'Resume path for xxx mode' comments.
Further, might as well help people and say that this is the call
_omap_sram_idle actually takes ;)
Also might be a little indepth pseudo code overview of this complex code
flow might help for code maintainers later on..
omap34xx_cpu_suspend
|- if Context save not required -> omap3_do_wfi -> wfi
\- if context save required: -> save_context_wfi
|
cache maintenance:
cache maintenance:
- what happens when l1 is lost, what happens when l2 is lost..
> */
> ENTRY(omap34xx_cpu_suspend)
> stmfd sp!, {r0-r12, lr} @ save registers on stack
>
> - /* r0 contains restore pointer in sdram */
> - /* r1 contains information about saving context */
> - ldr r4, sdrc_power @ read the SDRC_POWER register
> - ldr r5, [r4] @ read the contents of SDRC_POWER
> - orr r5, r5, #0x40 @ enable self refresh on idle req
> - str r5, [r4] @ write back to SDRC_POWER register
> + /*
> + * r0 contains restore pointer in sdram
> + * r1 contains information about saving context:
> + * 0 - No context lost
> + * 1 - Only L1 and logic lost
> + * 2 - Only L2 lost
> + * 3 - Both L1 and L2 lost
Since we are cleaning up, one generic Suggestion:
since these 0 1 2 3 are used by pm34xx.c and this code alone, we might
as well define it in a common header and save ourselves the pain of
defining this in 2 places and some one screwing things up later on..
looking at pm34xx.c, I dont see 2 being defined at all :( unless I
missed something, pm34xx.c:
switch (mpu_next_state) {
case PWRDM_POWER_ON:
case PWRDM_POWER_RET:
/* No need to save context */
Which is kind of funny for me. since we use this parameter to determine
to clean cache or not :D - another misinterpretation of using values
instead of readable macros ;)
save_state = 0;
break;
case PWRDM_POWER_OFF:
save_state = 3;
break;
> + */
>
> + /* Save context only if required */
> cmp r1, #0x0
> - /* If context save is required, do that and execute wfi */
> - bne save_context_wfi
> + beq omap3_do_wfi
> +
Add comment to fall through here.
> +save_context_wfi:
> + mov r8, r0 @ Store SDRAM address in r8
> + mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
> + mov r4, #0x1 @ Number of parameters for restore call
> + stmia r8!, {r4-r5} @ Push parameters for restore call
> + mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
> + stmia r8!, {r4-r5} @ Push parameters for restore call
> +
> + /* Check what that target sleep state is from r1 */
> + cmp r1, #0x2 @ Only L2 lost, no need to save context
> + beq clean_caches
one suggestion here:
how about:
and rn, r1, #L2_LOGIC_LOST
cmp rn, #L2_LOGIC_LOST
bleq l2_cleanup
and rn, r1, #L1_LOGIC_LOST
cmp rn, #L1_LOGIC_LOST
bleq l1_cleanup
move the omap3_do_wfi code here
l1_cleanup:
...
save_context
...
return back
l2_cleanup:
...
...
return back
or am I simplifying things too much here?
> +
> +l1_logic_lost:
> + /* Store sp and spsr to SDRAM */
> + mov r4, sp
> + mrs r5, spsr
> + mov r6, lr
> + stmia r8!, {r4-r6}
> + /* Save all ARM registers */
> + /* Coprocessor access control register */
> + mrc p15, 0, r6, c1, c0, 2
> + stmia r8!, {r6}
> + /* TTBR0, TTBR1 and Translation table base control */
> + mrc p15, 0, r4, c2, c0, 0
> + mrc p15, 0, r5, c2, c0, 1
> + mrc p15, 0, r6, c2, c0, 2
> + stmia r8!, {r4-r6}
> + /*
> + * Domain access control register, data fault status register,
> + * and instruction fault status register
> + */
> + mrc p15, 0, r4, c3, c0, 0
> + mrc p15, 0, r5, c5, c0, 0
> + mrc p15, 0, r6, c5, c0, 1
> + stmia r8!, {r4-r6}
> + /*
> + * Data aux fault status register, instruction aux fault status,
> + * data fault address register and instruction fault address register
> + */
> + mrc p15, 0, r4, c5, c1, 0
> + mrc p15, 0, r5, c5, c1, 1
> + mrc p15, 0, r6, c6, c0, 0
> + mrc p15, 0, r7, c6, c0, 2
> + stmia r8!, {r4-r7}
> + /*
> + * user r/w thread and process ID, user r/o thread and process ID,
> + * priv only thread and process ID, cache size selection
> + */
> + mrc p15, 0, r4, c13, c0, 2
> + mrc p15, 0, r5, c13, c0, 3
> + mrc p15, 0, r6, c13, c0, 4
> + mrc p15, 2, r7, c0, c0, 0
> + stmia r8!, {r4-r7}
> + /* Data TLB lockdown, instruction TLB lockdown registers */
> + mrc p15, 0, r5, c10, c0, 0
> + mrc p15, 0, r6, c10, c0, 1
> + stmia r8!, {r5-r6}
> + /* Secure or non secure vector base address, FCSE PID, Context PID*/
> + mrc p15, 0, r4, c12, c0, 0
> + mrc p15, 0, r5, c13, c0, 0
> + mrc p15, 0, r6, c13, c0, 1
> + stmia r8!, {r4-r6}
> + /* Primary remap, normal remap registers */
> + mrc p15, 0, r4, c10, c2, 0
> + mrc p15, 0, r5, c10, c2, 1
> + stmia r8!,{r4-r5}
> +
> + /* Store current cpsr*/
> + mrs r2, cpsr
> + stmia r8!, {r2}
> +
> + mrc p15, 0, r4, c1, c0, 0
> + /* save control register */
> + stmia r8!, {r4}
> +
> +clean_caches:
> + /*
> + * Clean Data or unified cache to POU
> + * How to invalidate only L1 cache???? - #FIX_ME#
> + * mcr p15, 0, r11, c7, c11, 1
> + */
> + cmp r1, #0x1 @ Check whether L2 inval is required
> + beq omap3_do_wfi
> +
> +clean_l2:
> + /*
> + * jump out to kernel flush routine
> + * - reuse that code is better
> + * - it executes in a cached space so is faster than refetch per-block
> + * - should be faster and will change with kernel
> + * - 'might' have to copy address, load and jump to it
> + */
> + ldr r1, kernel_flush
> + mov lr, pc
> + bx r1
> +
> +omap3_do_wfi:
recommend changing the name -> basically the flow is split into two:
wfi with save of context: save_context_wfi
wfi without save of context: omap3_do_wfi (I suppose the naming is
because it is being used in multiple paths)
> + ldr r4, sdrc_power @ read the SDRC_POWER register
> + ldr r5, [r4] @ read the contents of SDRC_POWER
> + orr r5, r5, #0x40 @ enable self refresh on idle req
> + str r5, [r4] @ write back to SDRC_POWER register
> +
we just changed the functional sequence of when we enable self refresh
on idle req (previously - this was the first step on entry, now, we do
this after context save) -> this should be a separate patch of it's own
for tracking any issues that may be detected by this change i suppose.
> /* Data memory barrier and Data sync barrier */
> mov r1, #0
> mcr p15, 0, r1, c7, c10, 4
> mcr p15, 0, r1, c7, c10, 5
>
> +/*
> + * ===================================
> + * == WFI instruction => Enter idle ==
idle is a bit confusing -> cpu idle can hit both RET and OFF..
> + * ===================================
> + */
> wfi @ wait for interrupt
>
> +/*
> + * ===================================
> + * == Resume path for non-OFF modes ==
> + * ===================================
> + */
> nop
> nop
> nop
> @@ -184,7 +315,29 @@ ENTRY(omap34xx_cpu_suspend)
> nop
> bl wait_sdrc_ok
>
> - ldmfd sp!, {r0-r12, pc} @ restore regs and return
> +/*
> + * ===================================
> + * == Exit point from non-OFF modes ==
> + * ===================================
> + */
> + ldmfd sp!, {r0-r12, pc} @ restore regs and return
cosmetic changes like this belong it's own patch to help the reviewer.
> +
> +
additional EOL?
> +/*
> + * ==============================
> + * == Resume path for OFF mode ==
> + * ==============================
> + */
> +
> +/*
> + * The restore_* functions are called by the ROM code
> + * when back from WFI in OFF mode.
> + * Cf. the get_*restore_pointer functions.
> + *
> + * restore_es3: applies to 34xx >= ES3.0
> + * restore_3630: applies to 36xx
> + * restore: common code for 3xxx
> + */
> restore_es3:
> ldr r5, pm_prepwstst_core_p
> ldr r4, [r5]
> @@ -214,12 +367,17 @@ restore_3630:
> ldr r1, control_mem_rta
> mov r2, #OMAP36XX_RTA_DISABLE
> str r2, [r1]
> - /* Fall thru for the remaining logic */
> +
> + /* Fall thru to common code for the remaining logic */
might as well replace thru with through ;)
> +
> restore:
> - /* Check what was the reason for mpu reset and store the reason in r9*/
> - /* 1 - Only L1 and logic lost */
> - /* 2 - Only L2 lost - In this case, we wont be here */
> - /* 3 - Both L1 and L2 lost */
> + /*
> + * Check what was the reason for mpu reset and store the reason in r9:
> + * 0 - No context lost
> + * 1 - Only L1 and logic lost
> + * 2 - Only L2 lost - In this case, we wont be here
> + * 3 - Both L1 and L2 lost
> + */
again something we can skip if we were to use #defines.
> ldr r1, pm_pwstctrl_mpu
> ldr r2, [r1]
> and r2, r2, #0x3
> @@ -422,118 +580,12 @@ usettbr0:
> and r4, r2
> mcr p15, 0, r4, c1, c0, 0
>
> +/*
> + * ==============================
> + * == Exit point from OFF mode ==
> + * ==============================
> + */
> ldmfd sp!, {r0-r12, pc} @ restore regs and return
> -save_context_wfi:
> - mov r8, r0 /* Store SDRAM address in r8 */
> - mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
> - mov r4, #0x1 @ Number of parameters for restore call
> - stmia r8!, {r4-r5} @ Push parameters for restore call
> - mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
> - stmia r8!, {r4-r5} @ Push parameters for restore call
> - /* Check what that target sleep state is:stored in r1*/
> - /* 1 - Only L1 and logic lost */
> - /* 2 - Only L2 lost */
> - /* 3 - Both L1 and L2 lost */
> - cmp r1, #0x2 /* Only L2 lost */
> - beq clean_l2
> - cmp r1, #0x1 /* L2 retained */
> - /* r9 stores whether to clean L2 or not*/
> - moveq r9, #0x0 /* Dont Clean L2 */
> - movne r9, #0x1 /* Clean L2 */
> -l1_logic_lost:
> - /* Store sp and spsr to SDRAM */
> - mov r4, sp
> - mrs r5, spsr
> - mov r6, lr
> - stmia r8!, {r4-r6}
> - /* Save all ARM registers */
> - /* Coprocessor access control register */
> - mrc p15, 0, r6, c1, c0, 2
> - stmia r8!, {r6}
> - /* TTBR0, TTBR1 and Translation table base control */
> - mrc p15, 0, r4, c2, c0, 0
> - mrc p15, 0, r5, c2, c0, 1
> - mrc p15, 0, r6, c2, c0, 2
> - stmia r8!, {r4-r6}
> - /* Domain access control register, data fault status register,
> - and instruction fault status register */
> - mrc p15, 0, r4, c3, c0, 0
> - mrc p15, 0, r5, c5, c0, 0
> - mrc p15, 0, r6, c5, c0, 1
> - stmia r8!, {r4-r6}
> - /* Data aux fault status register, instruction aux fault status,
> - datat fault address register and instruction fault address register*/
> - mrc p15, 0, r4, c5, c1, 0
> - mrc p15, 0, r5, c5, c1, 1
> - mrc p15, 0, r6, c6, c0, 0
> - mrc p15, 0, r7, c6, c0, 2
> - stmia r8!, {r4-r7}
> - /* user r/w thread and process ID, user r/o thread and process ID,
> - priv only thread and process ID, cache size selection */
> - mrc p15, 0, r4, c13, c0, 2
> - mrc p15, 0, r5, c13, c0, 3
> - mrc p15, 0, r6, c13, c0, 4
> - mrc p15, 2, r7, c0, c0, 0
> - stmia r8!, {r4-r7}
> - /* Data TLB lockdown, instruction TLB lockdown registers */
> - mrc p15, 0, r5, c10, c0, 0
> - mrc p15, 0, r6, c10, c0, 1
> - stmia r8!, {r5-r6}
> - /* Secure or non secure vector base address, FCSE PID, Context PID*/
> - mrc p15, 0, r4, c12, c0, 0
> - mrc p15, 0, r5, c13, c0, 0
> - mrc p15, 0, r6, c13, c0, 1
> - stmia r8!, {r4-r6}
> - /* Primary remap, normal remap registers */
> - mrc p15, 0, r4, c10, c2, 0
> - mrc p15, 0, r5, c10, c2, 1
> - stmia r8!,{r4-r5}
> -
> - /* Store current cpsr*/
> - mrs r2, cpsr
> - stmia r8!, {r2}
> -
> - mrc p15, 0, r4, c1, c0, 0
> - /* save control register */
> - stmia r8!, {r4}
> -clean_caches:
> - /* Clean Data or unified cache to POU*/
> - /* How to invalidate only L1 cache???? - #FIX_ME# */
> - /* mcr p15, 0, r11, c7, c11, 1 */
> - cmp r9, #1 /* Check whether L2 inval is required or not*/
> - bne skip_l2_inval
> -clean_l2:
> - /*
> - * Jump out to kernel flush routine
> - * - reuse that code is better
> - * - it executes in a cached space so is faster than refetch per-block
> - * - should be faster and will change with kernel
> - * - 'might' have to copy address, load and jump to it
> - */
> - ldr r1, kernel_flush
> - mov lr, pc
> - bx r1
> -
> -skip_l2_inval:
> - /* Data memory barrier and Data sync barrier */
> - mov r1, #0
> - mcr p15, 0, r1, c7, c10, 4
> - mcr p15, 0, r1, c7, c10, 5
> -
> - wfi @ wait for interrupt
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - bl wait_sdrc_ok
> - /* restore regs and return */
> - ldmfd sp!, {r0-r12, pc}
>
>
> /*
> @@ -683,5 +735,6 @@ kick_counter:
> .word 0
> wait_dll_lock_counter:
> .word 0
> +
spurious change.
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
as such, this patch:
Tested-by: Nishanth Menon <nm@ti.com>
Tested on:
SDP3630
SDP3430
Test script:
http://pastebin.mozilla.org/889933
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-17 15:35 ` Nishanth Menon
@ 2010-12-18 15:54 ` Jean Pihet
0 siblings, 0 replies; 18+ messages in thread
From: Jean Pihet @ 2010-12-18 15:54 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Dec 17, 2010 at 4:35 PM, Nishanth Menon <nm@ti.com> wrote:
> jean.pihet at newoldbits.com had written, on 12/17/2010 04:08 AM, the
> following:
>>
>> From: Jean Pihet <j-pihet@ti.com>
>>
>> - Reworked and simplified the execution paths for better
>> ?readability and to avoid duplication of code,
>
> is it possible to split this good rewrite into logical chunks for better and
> easier reviewability?
>
> my suggestion clean each of the paths independently - like the code upto
> wfi.. and then we can clean up the resume path as well separately.
>
>> - Added comments on the entry and exit points and the interaction
>> ?with the ROM code for OFF mode restore,
>> - Reworked the existing comments for better readability.
>
> thanks for doing this, but, just my suggestion, looking at the amount of
> changes done in this patch -> if you can keep one patch for functional
> change which is separate from cosmetic change (such as comment cleanup and
> addition), it makes a reviewer's life easier :)
>
>>
>> Tested on N900 and Beagleboard with full RET and OFF modes,
>> using cpuidle and suspend.
>>
>> Signed-off-by: Jean Pihet <j-pihet@ti.com>
>> ---
>> ?arch/arm/mach-omap2/control.c ? | ? ?9 +-
>> ?arch/arm/mach-omap2/sleep34xx.S | ?313
>> +++++++++++++++++++++++----------------
>> ?2 files changed, 191 insertions(+), 131 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
>> index 728f268..f4b19ed 100644
>> --- a/arch/arm/mach-omap2/control.c
>> +++ b/arch/arm/mach-omap2/control.c
>> @@ -239,7 +239,14 @@ void omap3_save_scratchpad_contents(void)
>> ? ? ? ?struct omap3_scratchpad_prcm_block prcm_block_contents;
>> ? ? ? ?struct omap3_scratchpad_sdrc_block sdrc_block_contents;
>> ?- ? ? ?/* Populate the Scratchpad contents */
>> + ? ? ? /*
>> + ? ? ? ?* Populate the Scratchpad contents
>> + ? ? ? ?*
>> + ? ? ? ?* The "get_*restore_pointer" functions are used to provide a
>> + ? ? ? ?* physical restore address where the ROM code jumps while waking
>> + ? ? ? ?* up from MPU OFF/OSWR state.
>
> Just curious: we dont have OSWR(open switch retention) in l-o unless I am
> mistaken.. we have cswr (closed switch retention).
Yes that is correct. OSWR is not supported for now, OFF is.
>
>> + ? ? ? ?* The restore pointer is stored into the scratchpad.
>> + ? ? ? ?*/
>> ? ? ? ?scratchpad_contents.boot_config_ptr = 0x0;
>> ? ? ? ?if (cpu_is_omap3630())
>> ? ? ? ? ? ? ? ?scratchpad_contents.public_restore_ptr =
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S
>> b/arch/arm/mach-omap2/sleep34xx.S
>> index beeb682..12061fd 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -71,6 +71,13 @@
>> ?* API functions
>> ?*/
>> ?+/*
>> + * The "get_*restore_pointer" functions are used to provide a
>> + * physical restore address where the ROM code jumps while waking
>> + * up from MPU OFF/OSWR state.
>> + * The restore pointer is stored into the scratchpad.
>> + */
>> +
>
> we need to cleanup comments such as those used below:
>
>> ? ? ? ?.text
>> ?/* Function call to get the restore pointer for resume from OFF */
>
> ^^^^
> may be make it explicit what the difference for get_restore_pointer is etc..
>
>> ?ENTRY(get_restore_pointer)
>> @@ -102,7 +109,7 @@ ENTRY(get_es3_restore_pointer_sz)
>> ?/*
>> ?* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
>> ?* This function sets up a flag that will allow for this toggling to take
>> - * place on 3630. Hopefully some version in the future maynot need this
>> + * place on 3630. Hopefully some version in the future may not need this.
>
> I think we should split the patch up for the comment cleanup -> it is a
> little nuisance trying to review the actual functional change mixed with
> comment cleanups together..
>
>> ?*/
>> ?ENTRY(enable_omap3630_toggle_l2_on_restore)
>> ? ? ? ? stmfd ? sp!, {lr} ? ? @ save registers on stack
>> @@ -144,34 +151,158 @@ ENTRY(save_secure_ram_context_sz)
>> ? ? ? ?.word ? . - save_secure_ram_context
>> ?/*
>> + * ======================
>> + * == Idle entry point ==
>> + * ======================
>> + */
>> +
>> +/*
>> ?* Forces OMAP into idle state
>> ?*
>> - * omap34xx_suspend() - This bit of code just executes the WFI
>> - * for normal idles.
>> + * omap34xx_suspend() - This bit of code saves the CPU context if needed
>> + * and executes the WFI instruction
>
> since we are cleaning up, I might as well suggest - what condition do we
> save the CPU context might be worth mentioning. is this called during RET
> transition or OFF transition is not clear..
Re-phrased that.
>>
>> ?*
>> - * Note: This code get's copied to internal SRAM at boot. When the OMAP
>> - * ? ? ?wakes up it continues execution at the point it went to sleep.
>> + * Notes:
>> + * - this code gets copied to internal SRAM at boot.
>> + * - when the OMAP wakes up it continues at different execution points
>> + * ? depending on the low power mode (non-OFF vs OFF modes),
>> + * ? cf. 'Resume path for xxx mode' comments.
>
> Further, might as well help people and say that this is the call
> _omap_sram_idle actually takes ;)
Added
>
> Also might be a little indepth pseudo code overview of this complex code
> flow might help for code maintainers later on..
>
> omap34xx_cpu_suspend
> ? |- if Context save not required -> omap3_do_wfi -> wfi
> ? \- if context save required: -> save_context_wfi
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?|
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?cache maintenance:
> cache maintenance:
> ? ? ? ?- what happens when l1 is lost, what happens when l2 is lost..
This can come later as the code settles down a bit.
>
>> ?*/
>> ?ENTRY(omap34xx_cpu_suspend)
>> ? ? ? ?stmfd ? sp!, {r0-r12, lr} ? ? ? ? ? ? ? @ save registers on stack
>> ?- ? ? ?/* r0 contains restore pointer in sdram */
>> - ? ? ? /* r1 contains information about saving context */
>> - ? ? ? ldr ? ? r4, sdrc_power ? ? ? ? ?@ read the SDRC_POWER register
>> - ? ? ? ldr ? ? r5, [r4] ? ? ? ? ? ? ? ?@ read the contents of SDRC_POWER
>> - ? ? ? orr ? ? r5, r5, #0x40 ? ? ? ? ? @ enable self refresh on idle req
>> - ? ? ? str ? ? r5, [r4] ? ? ? ? ? ? ? ?@ write back to SDRC_POWER
>> register
>> + ? ? ? /*
>> + ? ? ? ?* r0 contains restore pointer in sdram
>> + ? ? ? ?* r1 contains information about saving context:
>> + ? ? ? ?* ? 0 - No context lost
>> + ? ? ? ?* ? 1 - Only L1 and logic lost
>> + ? ? ? ?* ? 2 - Only L2 lost
>> + ? ? ? ?* ? 3 - Both L1 and L2 lost
>
> Since we are cleaning up, one generic Suggestion:
> since these 0 1 2 3 are used by pm34xx.c and this code alone, we might as
> well define it in a common header and save ourselves the pain of defining
> this in 2 places and some one screwing things up later on..
>
That makes perfect sense! However that will be done later since it
touches the code dangerously.
> looking at pm34xx.c, I dont see 2 being defined at all :( unless I missed
> something, pm34xx.c:
> ?switch (mpu_next_state) {
> ?case PWRDM_POWER_ON:
> ?case PWRDM_POWER_RET:
> ? ? ? ? /* No need to save context */
> Which is kind of funny for me. since we use this parameter to determine to
> clean cache or not :D - another misinterpretation of using values instead of
> readable macros ;)
> ? ? ? ? save_state = 0;
> ? ? ? ? break;
> ?case PWRDM_POWER_OFF:
> ? ? ? ? save_state = 3;
> ? ? ? ? break;
>
>> + ? ? ? ?*/
>> ?+ ? ? ?/* Save context only if required */
>> ? ? ? ?cmp ? ? r1, #0x0
>> - ? ? ? /* If context save is required, do that and execute wfi */
>> - ? ? ? bne ? ? save_context_wfi
>> + ? ? ? beq ? ? omap3_do_wfi
>> +
>
> Add comment to fall through here.
>
>> +save_context_wfi:
>> + ? ? ? mov ? ? r8, r0 ? ? ? ? ? ? ? ? ?@ Store SDRAM address in r8
>> + ? ? ? mrc ? ? p15, 0, r5, c1, c0, 1 ? @ Read Auxiliary Control Register
>> + ? ? ? mov ? ? r4, #0x1 ? ? ? ? ? ? ? ?@ Number of parameters for restore
>> call
>> + ? ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> + ? ? ? mrc ? ? p15, 1, r5, c9, c0, 2 ? @ Read L2 AUX ctrl register
>> + ? ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> +
>> + ? ? ? ?/* Check what that target sleep state is from r1 */
>> + ? ? ? cmp ? ? r1, #0x2 ? ? ? ? ? ? ? ?@ Only L2 lost, no need to save
>> context
>> + ? ? ? beq ? ? clean_caches
>
> one suggestion here:
> how about:
> ? ? ? ?and rn, r1, #L2_LOGIC_LOST
> ? ? ? ?cmp rn, #L2_LOGIC_LOST
> ? ? ? ?bleq l2_cleanup
> ? ? ? ?and rn, r1, #L1_LOGIC_LOST
> ? ? ? ?cmp rn, #L1_LOGIC_LOST
> ? ? ? ?bleq l1_cleanup
> ? ? ? ?move the omap3_do_wfi code here
>
> l1_cleanup:
> ? ? ? ?...
> ? ? ? ?save_context
> ? ? ? ?...
> ? ? ? ?return back
>
> l2_cleanup:
> ? ? ? ?...
> ? ? ? ?...
> ? ? ? ?return back
>
> or am I simplifying things too much here?
>
>> +
>> +l1_logic_lost:
>> + ? ? ? /* Store sp and spsr to SDRAM */
>> + ? ? ? mov ? ? r4, sp
>> + ? ? ? mrs ? ? r5, spsr
>> + ? ? ? mov ? ? r6, lr
>> + ? ? ? stmia ? r8!, {r4-r6}
>> + ? ? ? /* Save all ARM registers */
>> + ? ? ? /* Coprocessor access control register */
>> + ? ? ? mrc ? ? p15, 0, r6, c1, c0, 2
>> + ? ? ? stmia ? r8!, {r6}
>> + ? ? ? /* TTBR0, TTBR1 and Translation table base control */
>> + ? ? ? mrc ? ? p15, 0, r4, c2, c0, 0
>> + ? ? ? mrc ? ? p15, 0, r5, c2, c0, 1
>> + ? ? ? mrc ? ? p15, 0, r6, c2, c0, 2
>> + ? ? ? stmia ? r8!, {r4-r6}
>> + ? ? ? /*
>> + ? ? ? ?* Domain access control register, data fault status register,
>> + ? ? ? ?* and instruction fault status register
>> + ? ? ? ?*/
>> + ? ? ? mrc ? ? p15, 0, r4, c3, c0, 0
>> + ? ? ? mrc ? ? p15, 0, r5, c5, c0, 0
>> + ? ? ? mrc ? ? p15, 0, r6, c5, c0, 1
>> + ? ? ? stmia ? r8!, {r4-r6}
>> + ? ? ? /*
>> + ? ? ? ?* Data aux fault status register, instruction aux fault status,
>> + ? ? ? ?* data fault address register and instruction fault address
>> register
>> + ? ? ? ?*/
>> + ? ? ? mrc ? ? p15, 0, r4, c5, c1, 0
>> + ? ? ? mrc ? ? p15, 0, r5, c5, c1, 1
>> + ? ? ? mrc ? ? p15, 0, r6, c6, c0, 0
>> + ? ? ? mrc ? ? p15, 0, r7, c6, c0, 2
>> + ? ? ? stmia ? r8!, {r4-r7}
>> + ? ? ? /*
>> + ? ? ? ?* user r/w thread and process ID, user r/o thread and process ID,
>> + ? ? ? ?* priv only thread and process ID, cache size selection
>> + ? ? ? ?*/
>> + ? ? ? mrc ? ? p15, 0, r4, c13, c0, 2
>> + ? ? ? mrc ? ? p15, 0, r5, c13, c0, 3
>> + ? ? ? mrc ? ? p15, 0, r6, c13, c0, 4
>> + ? ? ? mrc ? ? p15, 2, r7, c0, c0, 0
>> + ? ? ? stmia ? r8!, {r4-r7}
>> + ? ? ? /* Data TLB lockdown, instruction TLB lockdown registers */
>> + ? ? ? mrc ? ? p15, 0, r5, c10, c0, 0
>> + ? ? ? mrc ? ? p15, 0, r6, c10, c0, 1
>> + ? ? ? stmia ? r8!, {r5-r6}
>> + ? ? ? /* Secure or non secure vector base address, FCSE PID, Context
>> PID*/
>> + ? ? ? mrc ? ? p15, 0, r4, c12, c0, 0
>> + ? ? ? mrc ? ? p15, 0, r5, c13, c0, 0
>> + ? ? ? mrc ? ? p15, 0, r6, c13, c0, 1
>> + ? ? ? stmia ? r8!, {r4-r6}
>> + ? ? ? /* Primary remap, normal remap registers */
>> + ? ? ? mrc ? ? p15, 0, r4, c10, c2, 0
>> + ? ? ? mrc ? ? p15, 0, r5, c10, c2, 1
>> + ? ? ? stmia ? r8!,{r4-r5}
>> +
>> + ? ? ? /* Store current cpsr*/
>> + ? ? ? mrs ? ? r2, cpsr
>> + ? ? ? stmia ? r8!, {r2}
>> +
>> + ? ? ? mrc ? ? p15, 0, r4, c1, c0, 0
>> + ? ? ? /* save control register */
>> + ? ? ? stmia ? r8!, {r4}
>> +
>> +clean_caches:
>> + ? ? ? /*
>> + ? ? ? ?* Clean Data or unified cache to POU
>> + ? ? ? ?* How to invalidate only L1 cache???? - #FIX_ME#
>> + ? ? ? ?* mcr ?p15, 0, r11, c7, c11, 1
>> + ? ? ? ?*/
>> + ? ? ? cmp ? ? r1, #0x1 ? ? ? ? ? ? ? ?@ Check whether L2 inval is
>> required
>> + ? ? ? beq ? ? omap3_do_wfi
>> +
>> +clean_l2:
>> + ? ? ? /*
>> + ? ? ? ?* jump out to kernel flush routine
>> + ? ? ? ?* ?- reuse that code is better
>> + ? ? ? ?* ?- it executes in a cached space so is faster than refetch
>> per-block
>> + ? ? ? ?* ?- should be faster and will change with kernel
>> + ? ? ? ?* ?- 'might' have to copy address, load and jump to it
>> + ? ? ? ?*/
>> + ? ? ? ldr r1, kernel_flush
>> + ? ? ? mov lr, pc
>> + ? ? ? bx ?r1
>> +
>> +omap3_do_wfi:
>
> recommend changing the name -> basically the flow is split into two:
> wfi with save of context: save_context_wfi
> wfi without save of context: omap3_do_wfi (I suppose the naming is because
> it is being used in multiple paths)
>
>
>
>> + ? ? ? ldr ? ? r4, sdrc_power ? ? ? ? ?@ read the SDRC_POWER register
>> + ? ? ? ldr ? ? r5, [r4] ? ? ? ? ? ? ? ?@ read the contents of SDRC_POWER
>> + ? ? ? orr ? ? r5, r5, #0x40 ? ? ? ? ? @ enable self refresh on idle req
>> + ? ? ? str ? ? r5, [r4] ? ? ? ? ? ? ? ?@ write back to SDRC_POWER
>> register
>> +
>
> we just changed the functional sequence of when we enable self refresh on
> idle req (previously - this was the first step on entry, now, we do this
> after context save) -> this should be a separate patch of it's own for
> tracking any issues that may be detected by this change i suppose.
>
>> ? ? ? ?/* Data memory barrier and Data sync barrier */
>> ? ? ? ?mov ? ? r1, #0
>> ? ? ? ?mcr ? ? p15, 0, r1, c7, c10, 4
>> ? ? ? ?mcr ? ? p15, 0, r1, c7, c10, 5
>> ?+/*
>> + * ===================================
>> + * == WFI instruction => Enter idle ==
>
> idle is a bit confusing -> cpu idle can hit both RET and OFF..
>
>> + * ===================================
>> + */
>> ? ? ? ?wfi ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ wait for interrupt
>> ?+/*
>> + * ===================================
>> + * == Resume path for non-OFF modes ==
>> + * ===================================
>> + */
>> ? ? ? ?nop
>> ? ? ? ?nop
>> ? ? ? ?nop
>> @@ -184,7 +315,29 @@ ENTRY(omap34xx_cpu_suspend)
>> ? ? ? ?nop
>> ? ? ? ?bl wait_sdrc_ok
>> ?- ? ? ?ldmfd ? sp!, {r0-r12, pc} ? ? ? ? ? ? ? @ restore regs and return
>> +/*
>> + * ===================================
>> + * == Exit point from non-OFF modes ==
>> + * ===================================
>> + */
>> + ? ? ? ldmfd ? sp!, {r0-r12, pc} ? ? ? @ restore regs and return
>
> cosmetic changes like this belong it's own patch to help the reviewer.
>
>> +
>> +
>
> additional EOL?
>>
>> +/*
>> + * ==============================
>> + * == Resume path for OFF mode ==
>> + * ==============================
>> + */
>> +
>> +/*
>> + * The restore_* functions are called by the ROM code
>> + * ?when back from WFI in OFF mode.
>> + * Cf. the get_*restore_pointer functions.
>> + *
>> + * ?restore_es3: applies to 34xx >= ES3.0
>> + * ?restore_3630: applies to 36xx
>> + * ?restore: common code for 3xxx
>> + */
>> ?restore_es3:
>> ? ? ? ?ldr ? ? r5, pm_prepwstst_core_p
>> ? ? ? ?ldr ? ? r4, [r5]
>> @@ -214,12 +367,17 @@ restore_3630:
>> ? ? ? ?ldr ? ? r1, control_mem_rta
>> ? ? ? ?mov ? ? r2, #OMAP36XX_RTA_DISABLE
>> ? ? ? ?str ? ? r2, [r1]
>> - ? ? ? /* Fall thru for the remaining logic */
>> +
>> + ? ? ? /* Fall thru to common code for the remaining logic */
>
> might as well replace thru with through ;)
Done!
>
>> +
>> ?restore:
>> - ? ? ? ?/* Check what was the reason for mpu reset and store the reason
>> in r9*/
>> - ? ? ? ?/* 1 - Only L1 and logic lost */
>> - ? ? ? ?/* 2 - Only L2 lost - In this case, we wont be here */
>> - ? ? ? ?/* 3 - Both L1 and L2 lost */
>> + ? ? ? ?/*
>> + ? ? ? ?* Check what was the reason for mpu reset and store the reason in
>> r9:
>> + ? ? ? ?* ?0 - No context lost
>> + ? ? ? ? * ?1 - Only L1 and logic lost
>> + ? ? ? ? * ?2 - Only L2 lost - In this case, we wont be here
>> + ? ? ? ? * ?3 - Both L1 and L2 lost
>> + ? ? ? ?*/
>
> again something we can skip if we were to use #defines.
>
>> ? ? ? ?ldr ? ? r1, pm_pwstctrl_mpu
>> ? ? ? ?ldr ? ? r2, [r1]
>> ? ? ? ?and ? ? r2, r2, #0x3
>> @@ -422,118 +580,12 @@ usettbr0:
>> ? ? ? ?and ? ? r4, r2
>> ? ? ? ?mcr ? ? p15, 0, r4, c1, c0, 0
>> ?+/*
>> + * ==============================
>> + * == Exit point from OFF mode ==
>> + * ==============================
>> + */
>> ? ? ? ?ldmfd ? sp!, {r0-r12, pc} ? ? ? ? ? ? ? @ restore regs and return
>> -save_context_wfi:
>> - ? ? ? mov ? ? r8, r0 /* Store SDRAM address in r8 */
>> - ? ? ? mrc ? ? p15, 0, r5, c1, c0, 1 ? @ Read Auxiliary Control Register
>> - ? ? ? mov ? ? r4, #0x1 ? ? ? ? ? ? ? ?@ Number of parameters for restore
>> call
>> - ? ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> - ? ? ? mrc ? ? p15, 1, r5, c9, c0, 2 ? @ Read L2 AUX ctrl register
>> - ? ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> - ? ? ? ?/* Check what that target sleep state is:stored in r1*/
>> - ? ? ? ?/* 1 - Only L1 and logic lost */
>> - ? ? ? ?/* 2 - Only L2 lost */
>> - ? ? ? ?/* 3 - Both L1 and L2 lost */
>> - ? ? ? cmp ? ? r1, #0x2 /* Only L2 lost */
>> - ? ? ? beq ? ? clean_l2
>> - ? ? ? cmp ? ? r1, #0x1 /* L2 retained */
>> - ? ? ? /* r9 stores whether to clean L2 or not*/
>> - ? ? ? moveq ? r9, #0x0 /* Dont Clean L2 */
>> - ? ? ? movne ? r9, #0x1 /* Clean L2 */
>> -l1_logic_lost:
>> - ? ? ? /* Store sp and spsr to SDRAM */
>> - ? ? ? mov ? ? r4, sp
>> - ? ? ? mrs ? ? r5, spsr
>> - ? ? ? mov ? ? r6, lr
>> - ? ? ? stmia ? r8!, {r4-r6}
>> - ? ? ? /* Save all ARM registers */
>> - ? ? ? /* Coprocessor access control register */
>> - ? ? ? mrc ? ? p15, 0, r6, c1, c0, 2
>> - ? ? ? stmia ? r8!, {r6}
>> - ? ? ? /* TTBR0, TTBR1 and Translation table base control */
>> - ? ? ? mrc ? ? p15, 0, r4, c2, c0, 0
>> - ? ? ? mrc ? ? p15, 0, r5, c2, c0, 1
>> - ? ? ? mrc ? ? p15, 0, r6, c2, c0, 2
>> - ? ? ? stmia ? r8!, {r4-r6}
>> - ? ? ? /* Domain access control register, data fault status register,
>> - ? ? ? and instruction fault status register */
>> - ? ? ? mrc ? ? p15, 0, r4, c3, c0, 0
>> - ? ? ? mrc ? ? p15, 0, r5, c5, c0, 0
>> - ? ? ? mrc ? ? p15, 0, r6, c5, c0, 1
>> - ? ? ? stmia ? r8!, {r4-r6}
>> - ? ? ? /* Data aux fault status register, instruction aux fault status,
>> - ? ? ? datat fault address register and instruction fault address
>> register*/
>> - ? ? ? mrc ? ? p15, 0, r4, c5, c1, 0
>> - ? ? ? mrc ? ? p15, 0, r5, c5, c1, 1
>> - ? ? ? mrc ? ? p15, 0, r6, c6, c0, 0
>> - ? ? ? mrc ? ? p15, 0, r7, c6, c0, 2
>> - ? ? ? stmia ? r8!, {r4-r7}
>> - ? ? ? /* user r/w thread and process ID, user r/o thread and process ID,
>> - ? ? ? priv only thread and process ID, cache size selection */
>> - ? ? ? mrc ? ? p15, 0, r4, c13, c0, 2
>> - ? ? ? mrc ? ? p15, 0, r5, c13, c0, 3
>> - ? ? ? mrc ? ? p15, 0, r6, c13, c0, 4
>> - ? ? ? mrc ? ? p15, 2, r7, c0, c0, 0
>> - ? ? ? stmia ? r8!, {r4-r7}
>> - ? ? ? /* Data TLB lockdown, instruction TLB lockdown registers */
>> - ? ? ? mrc ? ? p15, 0, r5, c10, c0, 0
>> - ? ? ? mrc ? ? p15, 0, r6, c10, c0, 1
>> - ? ? ? stmia ? r8!, {r5-r6}
>> - ? ? ? /* Secure or non secure vector base address, FCSE PID, Context
>> PID*/
>> - ? ? ? mrc ? ? p15, 0, r4, c12, c0, 0
>> - ? ? ? mrc ? ? p15, 0, r5, c13, c0, 0
>> - ? ? ? mrc ? ? p15, 0, r6, c13, c0, 1
>> - ? ? ? stmia ? r8!, {r4-r6}
>> - ? ? ? /* Primary remap, normal remap registers */
>> - ? ? ? mrc ? ? p15, 0, r4, c10, c2, 0
>> - ? ? ? mrc ? ? p15, 0, r5, c10, c2, 1
>> - ? ? ? stmia ? r8!,{r4-r5}
>> -
>> - ? ? ? /* Store current cpsr*/
>> - ? ? ? mrs ? ? r2, cpsr
>> - ? ? ? stmia ? r8!, {r2}
>> -
>> - ? ? ? mrc ? ? p15, 0, r4, c1, c0, 0
>> - ? ? ? /* save control register */
>> - ? ? ? stmia ? r8!, {r4}
>> -clean_caches:
>> - ? ? ? /* Clean Data or unified cache to POU*/
>> - ? ? ? /* How to invalidate only L1 cache???? - #FIX_ME# */
>> - ? ? ? /* mcr ?p15, 0, r11, c7, c11, 1 */
>> - ? ? ? cmp ? ? r9, #1 /* Check whether L2 inval is required or not*/
>> - ? ? ? bne ? ? skip_l2_inval
>> -clean_l2:
>> - ? ? ? /*
>> - ? ? ? ?* Jump out to kernel flush routine
>> - ? ? ? ?* ?- reuse that code is better
>> - ? ? ? ?* ?- it executes in a cached space so is faster than refetch
>> per-block
>> - ? ? ? ?* ?- should be faster and will change with kernel
>> - ? ? ? ?* ?- 'might' have to copy address, load and jump to it
>> - ? ? ? ?*/
>> - ? ? ? ldr r1, kernel_flush
>> - ? ? ? mov lr, pc
>> - ? ? ? bx ?r1
>> -
>> -skip_l2_inval:
>> - ? ? ? /* Data memory barrier and Data sync barrier */
>> - ? ? ? mov ? ? r1, #0
>> - ? ? ? mcr ? ? p15, 0, r1, c7, c10, 4
>> - ? ? ? mcr ? ? p15, 0, r1, c7, c10, 5
>> -
>> - ? ? ? wfi ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ wait for interrupt
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? nop
>> - ? ? ? bl wait_sdrc_ok
>> - ? ? ? /* restore regs and return */
>> - ? ? ? ldmfd ? sp!, {r0-r12, pc}
>> ? /*
>> @@ -683,5 +735,6 @@ kick_counter:
>> ? ? ? ?.word ? 0
>> ?wait_dll_lock_counter:
>> ? ? ? ?.word ? 0
>> +
>
> spurious change.
>
>> ?ENTRY(omap34xx_cpu_suspend_sz)
>> ? ? ? ?.word ? . - omap34xx_cpu_suspend
>
> as such, this patch:
>
> Tested-by: Nishanth Menon <nm@ti.com>
> Tested on:
> SDP3630
> SDP3430
> Test script:
> http://pastebin.mozilla.org/889933
>
>
> --
> Regards,
> Nishanth Menon
>
Thanks,
Jean
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-16 17:50 [PATCH 0/7 v4] OMAP3: clean up ASM sleep code jean.pihet at newoldbits.com
@ 2010-12-16 17:50 ` jean.pihet at newoldbits.com
2010-12-17 5:04 ` Santosh Shilimkar
0 siblings, 1 reply; 18+ messages in thread
From: jean.pihet at newoldbits.com @ 2010-12-16 17:50 UTC (permalink / raw)
To: linux-arm-kernel
From: Jean Pihet <j-pihet@ti.com>
- Reworked and simplified the execution paths for better
readability and to avoid duplication of code,
- Added comments on the entry and exit points and the interaction
with the ROM code for OFF mode restore,
- Reworked the existing comments for better readability.
Tested on N900 and Beagleboard with full RET and OFF modes,
using cpuidle and suspend.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
---
arch/arm/mach-omap2/control.c | 10 +-
arch/arm/mach-omap2/sleep34xx.S | 309 ++++++++++++++++++++++----------------
2 files changed, 188 insertions(+), 131 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 728f268..5cb7276 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -239,7 +239,15 @@ void omap3_save_scratchpad_contents(void)
struct omap3_scratchpad_prcm_block prcm_block_contents;
struct omap3_scratchpad_sdrc_block sdrc_block_contents;
- /* Populate the Scratchpad contents */
+ /*
+ * Populate the Scratchpad contents
+ *
+ * The get_*restore_pointer functions are used to get the resume
+ * function pointer to be called by the ROM code when back from WFI
+ * in OFF mode.
+ * The restore pointer is stored into the scratchpad for later access
+ * by the ROM code.
+ */
scratchpad_contents.boot_config_ptr = 0x0;
if (cpu_is_omap3630())
scratchpad_contents.public_restore_ptr =
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 426af02..55ddd5a 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -70,6 +70,11 @@
* API functions
*/
+/*
+ * The get_*restore_pointer functions are returning the resume
+ * function pointer to be called by the ROM code when back from WFI
+ * in OFF mode.
+ */
.text
/* Function call to get the restore pointer for resume from OFF */
ENTRY(get_restore_pointer)
@@ -101,7 +106,7 @@ ENTRY(get_es3_restore_pointer_sz)
/*
* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
* This function sets up a flag that will allow for this toggling to take
- * place on 3630. Hopefully some version in the future maynot need this
+ * place on 3630. Hopefully some version in the future maynot need this.
*/
ENTRY(enable_omap3630_toggle_l2_on_restore)
stmfd sp!, {lr} @ save registers on stack
@@ -143,34 +148,156 @@ ENTRY(save_secure_ram_context_sz)
.word . - save_secure_ram_context
/*
+ * ======================
+ * == Idle entry point ==
+ * ======================
+ */
+
+/*
* Forces OMAP into idle state
*
- * omap34xx_suspend() - This bit of code just executes the WFI
- * for normal idles.
+ * omap34xx_suspend() - This bit of code saves the CPU context if needed
+ * and executes the WFI instruction
*
- * Note: This code get's copied to internal SRAM at boot. When the OMAP
- * wakes up it continues execution at the point it went to sleep.
+ * Notes:
+ * - this code gets copied to internal SRAM at boot.
+ * - when the OMAP wakes up it continues at different execution points
+ * depending on the low power mode (non-OFF vs OFF modes),
+ * cf. 'Resume path for xxx mode' comments.
*/
ENTRY(omap34xx_cpu_suspend)
stmfd sp!, {r0-r12, lr} @ save registers on stack
- /* r0 contains restore pointer in sdram */
- /* r1 contains information about saving context */
- ldr r4, sdrc_power @ read the SDRC_POWER register
- ldr r5, [r4] @ read the contents of SDRC_POWER
- orr r5, r5, #0x40 @ enable self refresh on idle req
- str r5, [r4] @ write back to SDRC_POWER register
+ /*
+ * r0 contains restore pointer in sdram
+ * r1 contains information about saving context:
+ * 0 - No context lost
+ * 1 - Only L1 and logic lost
+ * 2 - Only L2 lost
+ * 3 - Both L1 and L2 lost
+ */
+ /* Save context only if required */
cmp r1, #0x0
- /* If context save is required, do that and execute wfi */
- bne save_context_wfi
+ beq omap3_do_wfi
+
+save_context_wfi:
+ mov r8, r0 @ Store SDRAM address in r8
+ mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
+ mov r4, #0x1 @ Number of parameters for restore call
+ stmia r8!, {r4-r5} @ Push parameters for restore call
+ mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
+ stmia r8!, {r4-r5} @ Push parameters for restore call
+
+ /* Check what that target sleep state is from r1 */
+ cmp r1, #0x2 @ Only L2 lost, no need to save context
+ beq clean_caches
+
+l1_logic_lost:
+ /* Store sp and spsr to SDRAM */
+ mov r4, sp
+ mrs r5, spsr
+ mov r6, lr
+ stmia r8!, {r4-r6}
+ /* Save all ARM registers */
+ /* Coprocessor access control register */
+ mrc p15, 0, r6, c1, c0, 2
+ stmia r8!, {r6}
+ /* TTBR0, TTBR1 and Translation table base control */
+ mrc p15, 0, r4, c2, c0, 0
+ mrc p15, 0, r5, c2, c0, 1
+ mrc p15, 0, r6, c2, c0, 2
+ stmia r8!, {r4-r6}
+ /*
+ * Domain access control register, data fault status register,
+ * and instruction fault status register
+ */
+ mrc p15, 0, r4, c3, c0, 0
+ mrc p15, 0, r5, c5, c0, 0
+ mrc p15, 0, r6, c5, c0, 1
+ stmia r8!, {r4-r6}
+ /*
+ * Data aux fault status register, instruction aux fault status,
+ * data fault address register and instruction fault address register
+ */
+ mrc p15, 0, r4, c5, c1, 0
+ mrc p15, 0, r5, c5, c1, 1
+ mrc p15, 0, r6, c6, c0, 0
+ mrc p15, 0, r7, c6, c0, 2
+ stmia r8!, {r4-r7}
+ /*
+ * user r/w thread and process ID, user r/o thread and process ID,
+ * priv only thread and process ID, cache size selection
+ */
+ mrc p15, 0, r4, c13, c0, 2
+ mrc p15, 0, r5, c13, c0, 3
+ mrc p15, 0, r6, c13, c0, 4
+ mrc p15, 2, r7, c0, c0, 0
+ stmia r8!, {r4-r7}
+ /* Data TLB lockdown, instruction TLB lockdown registers */
+ mrc p15, 0, r5, c10, c0, 0
+ mrc p15, 0, r6, c10, c0, 1
+ stmia r8!, {r5-r6}
+ /* Secure or non secure vector base address, FCSE PID, Context PID*/
+ mrc p15, 0, r4, c12, c0, 0
+ mrc p15, 0, r5, c13, c0, 0
+ mrc p15, 0, r6, c13, c0, 1
+ stmia r8!, {r4-r6}
+ /* Primary remap, normal remap registers */
+ mrc p15, 0, r4, c10, c2, 0
+ mrc p15, 0, r5, c10, c2, 1
+ stmia r8!,{r4-r5}
+
+ /* Store current cpsr*/
+ mrs r2, cpsr
+ stmia r8!, {r2}
+
+ mrc p15, 0, r4, c1, c0, 0
+ /* save control register */
+ stmia r8!, {r4}
+
+clean_caches:
+ /* Clean Data or unified cache to POU*/
+ /* How to invalidate only L1 cache???? - #FIX_ME# */
+ /* mcr p15, 0, r11, c7, c11, 1 */
+ cmp r1, #0x1 @ Check whether L2 inval is required
+ beq omap3_do_wfi
+
+clean_l2:
+ /*
+ * jump out to kernel flush routine
+ * - reuse that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
+ */
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
+
+omap3_do_wfi:
+ ldr r4, sdrc_power @ read the SDRC_POWER register
+ ldr r5, [r4] @ read the contents of SDRC_POWER
+ orr r5, r5, #0x40 @ enable self refresh on idle req
+ str r5, [r4] @ write back to SDRC_POWER register
+
/* Data memory barrier and Data sync barrier */
mov r1, #0
mcr p15, 0, r1, c7, c10, 4
mcr p15, 0, r1, c7, c10, 5
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
wfi @ wait for interrupt
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
nop
nop
nop
@@ -183,7 +310,29 @@ ENTRY(omap34xx_cpu_suspend)
nop
bl wait_sdrc_ok
- ldmfd sp!, {r0-r12, pc} @ restore regs and return
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
+
+
+/*
+ * ==============================
+ * == Resume path for OFF mode ==
+ * ==============================
+ */
+
+/*
+ * The restore_* functions are called by the ROM code
+ * when back from WFI in OFF mode.
+ * Cf. the get_*restore_pointer functions.
+ *
+ * restore_es3: applies to 34xx >= ES3.0
+ * restore_3630: applies to 36xx
+ * restore: common code for 3xxx
+ */
restore_es3:
ldr r5, pm_prepwstst_core_p
ldr r4, [r5]
@@ -213,12 +362,17 @@ restore_3630:
ldr r1, control_mem_rta
mov r2, #OMAP36XX_RTA_DISABLE
str r2, [r1]
- /* Fall thru for the remaining logic */
+
+ /* Fall thru to common code for the remaining logic */
+
restore:
- /* Check what was the reason for mpu reset and store the reason in r9*/
- /* 1 - Only L1 and logic lost */
- /* 2 - Only L2 lost - In this case, we wont be here */
- /* 3 - Both L1 and L2 lost */
+ /*
+ * Check what was the reason for mpu reset and store the reason in r9:
+ * 0 - No context lost
+ * 1 - Only L1 and logic lost
+ * 2 - Only L2 lost - In this case, we wont be here
+ * 3 - Both L1 and L2 lost
+ */
ldr r1, pm_pwstctrl_mpu
ldr r2, [r1]
and r2, r2, #0x3
@@ -421,118 +575,12 @@ usettbr0:
and r4, r2
mcr p15, 0, r4, c1, c0, 0
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
ldmfd sp!, {r0-r12, pc} @ restore regs and return
-save_context_wfi:
- mov r8, r0 /* Store SDRAM address in r8 */
- mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
- mov r4, #0x1 @ Number of parameters for restore call
- stmia r8!, {r4-r5} @ Push parameters for restore call
- mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
- stmia r8!, {r4-r5} @ Push parameters for restore call
- /* Check what that target sleep state is:stored in r1*/
- /* 1 - Only L1 and logic lost */
- /* 2 - Only L2 lost */
- /* 3 - Both L1 and L2 lost */
- cmp r1, #0x2 /* Only L2 lost */
- beq clean_l2
- cmp r1, #0x1 /* L2 retained */
- /* r9 stores whether to clean L2 or not*/
- moveq r9, #0x0 /* Dont Clean L2 */
- movne r9, #0x1 /* Clean L2 */
-l1_logic_lost:
- /* Store sp and spsr to SDRAM */
- mov r4, sp
- mrs r5, spsr
- mov r6, lr
- stmia r8!, {r4-r6}
- /* Save all ARM registers */
- /* Coprocessor access control register */
- mrc p15, 0, r6, c1, c0, 2
- stmia r8!, {r6}
- /* TTBR0, TTBR1 and Translation table base control */
- mrc p15, 0, r4, c2, c0, 0
- mrc p15, 0, r5, c2, c0, 1
- mrc p15, 0, r6, c2, c0, 2
- stmia r8!, {r4-r6}
- /* Domain access control register, data fault status register,
- and instruction fault status register */
- mrc p15, 0, r4, c3, c0, 0
- mrc p15, 0, r5, c5, c0, 0
- mrc p15, 0, r6, c5, c0, 1
- stmia r8!, {r4-r6}
- /* Data aux fault status register, instruction aux fault status,
- datat fault address register and instruction fault address register*/
- mrc p15, 0, r4, c5, c1, 0
- mrc p15, 0, r5, c5, c1, 1
- mrc p15, 0, r6, c6, c0, 0
- mrc p15, 0, r7, c6, c0, 2
- stmia r8!, {r4-r7}
- /* user r/w thread and process ID, user r/o thread and process ID,
- priv only thread and process ID, cache size selection */
- mrc p15, 0, r4, c13, c0, 2
- mrc p15, 0, r5, c13, c0, 3
- mrc p15, 0, r6, c13, c0, 4
- mrc p15, 2, r7, c0, c0, 0
- stmia r8!, {r4-r7}
- /* Data TLB lockdown, instruction TLB lockdown registers */
- mrc p15, 0, r5, c10, c0, 0
- mrc p15, 0, r6, c10, c0, 1
- stmia r8!, {r5-r6}
- /* Secure or non secure vector base address, FCSE PID, Context PID*/
- mrc p15, 0, r4, c12, c0, 0
- mrc p15, 0, r5, c13, c0, 0
- mrc p15, 0, r6, c13, c0, 1
- stmia r8!, {r4-r6}
- /* Primary remap, normal remap registers */
- mrc p15, 0, r4, c10, c2, 0
- mrc p15, 0, r5, c10, c2, 1
- stmia r8!,{r4-r5}
-
- /* Store current cpsr*/
- mrs r2, cpsr
- stmia r8!, {r2}
-
- mrc p15, 0, r4, c1, c0, 0
- /* save control register */
- stmia r8!, {r4}
-clean_caches:
- /* Clean Data or unified cache to POU*/
- /* How to invalidate only L1 cache???? - #FIX_ME# */
- /* mcr p15, 0, r11, c7, c11, 1 */
- cmp r9, #1 /* Check whether L2 inval is required or not*/
- bne skip_l2_inval
-clean_l2:
- /*
- * Jump out to kernel flush routine
- * - reuse that code is better
- * - it executes in a cached space so is faster than refetch per-block
- * - should be faster and will change with kernel
- * - 'might' have to copy address, load and jump to it
- */
- ldr r1, kernel_flush
- mov lr, pc
- bx r1
-
-skip_l2_inval:
- /* Data memory barrier and Data sync barrier */
- mov r1, #0
- mcr p15, 0, r1, c7, c10, 4
- mcr p15, 0, r1, c7, c10, 5
-
- wfi @ wait for interrupt
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- bl wait_sdrc_ok
- /* restore regs and return */
- ldmfd sp!, {r0-r12, pc}
/*
@@ -682,5 +730,6 @@ kick_counter:
.word 0
wait_dll_lock_counter:
.word 0
+
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.7.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-16 17:50 ` [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths jean.pihet at newoldbits.com
@ 2010-12-17 5:04 ` Santosh Shilimkar
2010-12-17 10:14 ` Jean Pihet
0 siblings, 1 reply; 18+ messages in thread
From: Santosh Shilimkar @ 2010-12-17 5:04 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of jean.pihet at newoldbits.com
> Sent: Thursday, December 16, 2010 11:21 PM
> To: linux-omap at vger.kernel.org
> Cc: khilman at deeprootsystems.com; linux-arm-kernel at lists.infradead.org;
> Jean Pihet
> Subject: [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
>
> From: Jean Pihet <j-pihet@ti.com>
>
> - Reworked and simplified the execution paths for better
> readability and to avoid duplication of code,
> - Added comments on the entry and exit points and the interaction
> with the ROM code for OFF mode restore,
> - Reworked the existing comments for better readability.
>
> Tested on N900 and Beagleboard with full RET and OFF modes,
> using cpuidle and suspend.
>
> Signed-off-by: Jean Pihet <j-pihet@ti.com>
> ---
> arch/arm/mach-omap2/control.c | 10 +-
> arch/arm/mach-omap2/sleep34xx.S | 309
++++++++++++++++++++++------------
> ----
> 2 files changed, 188 insertions(+), 131 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c
b/arch/arm/mach-omap2/control.c
> index 728f268..5cb7276 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -239,7 +239,15 @@ void omap3_save_scratchpad_contents(void)
> struct omap3_scratchpad_prcm_block prcm_block_contents;
> struct omap3_scratchpad_sdrc_block sdrc_block_contents;
>
> - /* Populate the Scratchpad contents */
> + /*
> + * Populate the Scratchpad contents
> + *
> + * The get_*restore_pointer functions are used to get the resume
> + * function pointer to be called by the ROM code when back from
WFI
> + * in OFF mode.
Align your text here.
> + * The restore pointer is stored into the scratchpad for later
> access
> + * by the ROM code.
The text needs to be reworked a bit.
The "get_*restore_pointer" functions are used to provide a physical
restore
address where ROM code jumps while waking up from MPU OFF/OSWR state.
The restore pointer is stored into the scratchpad
> + */
> scratchpad_contents.boot_config_ptr = 0x0;
> if (cpu_is_omap3630())
> scratchpad_contents.public_restore_ptr =
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 426af02..55ddd5a 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -70,6 +70,11 @@
> * API functions
> */
>
> +/*
> + * The get_*restore_pointer functions are returning the resume
> + * function pointer to be called by the ROM code when back from WFI
> + * in OFF mode.
Ditto
The "get_*restore_pointer" functions are used to provide a physical
restore
address where ROM code jumps while waking up from MPU OFF/OSWR state.
The restore pointer is stored into the scratchpad
> + */
> .text
> /* Function call to get the restore pointer for resume from OFF */
> ENTRY(get_restore_pointer)
> @@ -101,7 +106,7 @@ ENTRY(get_es3_restore_pointer_sz)
> /*
> * L2 cache needs to be toggled for stable OFF mode functionality on
3630.
> * This function sets up a flag that will allow for this toggling to
take
> - * place on 3630. Hopefully some version in the future maynot need this
> + * place on 3630. Hopefully some version in the future maynot need
this.
'maynot' ..... may not
> */
> ENTRY(enable_omap3630_toggle_l2_on_restore)
> stmfd sp!, {lr} @ save registers on stack
> @@ -143,34 +148,156 @@ ENTRY(save_secure_ram_context_sz)
> .word . - save_secure_ram_context
>
> /*
> + * ======================
> + * == Idle entry point ==
> + * ======================
> + */
> +
> +/*
> * Forces OMAP into idle state
> *
> - * omap34xx_suspend() - This bit of code just executes the WFI
> - * for normal idles.
> + * omap34xx_suspend() - This bit of code saves the CPU context if
needed
> + * and executes the WFI instruction
> *
> - * Note: This code get's copied to internal SRAM at boot. When the OMAP
> - * wakes up it continues execution at the point it went to sleep.
> + * Notes:
> + * - this code gets copied to internal SRAM at boot.
> + * - when the OMAP wakes up it continues at different execution points
> + * depending on the low power mode (non-OFF vs OFF modes),
> + * cf. 'Resume path for xxx mode' comments.
> */
> ENTRY(omap34xx_cpu_suspend)
> stmfd sp!, {r0-r12, lr} @ save registers on stack
>
> - /* r0 contains restore pointer in sdram */
> - /* r1 contains information about saving context */
> - ldr r4, sdrc_power @ read the SDRC_POWER register
> - ldr r5, [r4] @ read the contents of SDRC_POWER
> - orr r5, r5, #0x40 @ enable self refresh on idle req
> - str r5, [r4] @ write back to SDRC_POWER
register
> + /*
> + * r0 contains restore pointer in sdram
> + * r1 contains information about saving context:
> + * 0 - No context lost
> + * 1 - Only L1 and logic lost
> + * 2 - Only L2 lost
> + * 3 - Both L1 and L2 lost
> + */
>
> + /* Save context only if required */
> cmp r1, #0x0
> - /* If context save is required, do that and execute wfi */
> - bne save_context_wfi
> + beq omap3_do_wfi
> +
> +save_context_wfi:
> + mov r8, r0 @ Store SDRAM address in r8
> + mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
> + mov r4, #0x1 @ Number of parameters for restore
call
> + stmia r8!, {r4-r5} @ Push parameters for restore call
> + mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
> + stmia r8!, {r4-r5} @ Push parameters for restore call
> +
> + /* Check what that target sleep state is from r1 */
> + cmp r1, #0x2 @ Only L2 lost, no need to save
context
> + beq clean_caches
> +
> +l1_logic_lost:
> + /* Store sp and spsr to SDRAM */
> + mov r4, sp
> + mrs r5, spsr
> + mov r6, lr
> + stmia r8!, {r4-r6}
> + /* Save all ARM registers */
> + /* Coprocessor access control register */
You might want to fix above commenting style as well
> + mrc p15, 0, r6, c1, c0, 2
> + stmia r8!, {r6}
> + /* TTBR0, TTBR1 and Translation table base control */
> + mrc p15, 0, r4, c2, c0, 0
> + mrc p15, 0, r5, c2, c0, 1
> + mrc p15, 0, r6, c2, c0, 2
> + stmia r8!, {r4-r6}
> + /*
> + * Domain access control register, data fault status register,
> + * and instruction fault status register
> + */
> + mrc p15, 0, r4, c3, c0, 0
> + mrc p15, 0, r5, c5, c0, 0
> + mrc p15, 0, r6, c5, c0, 1
> + stmia r8!, {r4-r6}
> + /*
> + * Data aux fault status register, instruction aux fault status,
> + * data fault address register and instruction fault address
> register
> + */
> + mrc p15, 0, r4, c5, c1, 0
> + mrc p15, 0, r5, c5, c1, 1
> + mrc p15, 0, r6, c6, c0, 0
> + mrc p15, 0, r7, c6, c0, 2
> + stmia r8!, {r4-r7}
> + /*
> + * user r/w thread and process ID, user r/o thread and process ID,
> + * priv only thread and process ID, cache size selection
> + */
> + mrc p15, 0, r4, c13, c0, 2
> + mrc p15, 0, r5, c13, c0, 3
> + mrc p15, 0, r6, c13, c0, 4
> + mrc p15, 2, r7, c0, c0, 0
> + stmia r8!, {r4-r7}
> + /* Data TLB lockdown, instruction TLB lockdown registers */
> + mrc p15, 0, r5, c10, c0, 0
> + mrc p15, 0, r6, c10, c0, 1
> + stmia r8!, {r5-r6}
> + /* Secure or non secure vector base address, FCSE PID, Context
PID*/
> + mrc p15, 0, r4, c12, c0, 0
> + mrc p15, 0, r5, c13, c0, 0
> + mrc p15, 0, r6, c13, c0, 1
> + stmia r8!, {r4-r6}
> + /* Primary remap, normal remap registers */
> + mrc p15, 0, r4, c10, c2, 0
> + mrc p15, 0, r5, c10, c2, 1
> + stmia r8!,{r4-r5}
> +
> + /* Store current cpsr*/
> + mrs r2, cpsr
> + stmia r8!, {r2}
> +
> + mrc p15, 0, r4, c1, c0, 0
> + /* save control register */
> + stmia r8!, {r4}
> +
> +clean_caches:
> + /* Clean Data or unified cache to POU*/
> + /* How to invalidate only L1 cache???? - #FIX_ME# */
> + /* mcr p15, 0, r11, c7, c11, 1 */
And this one too...
> + cmp r1, #0x1 @ Check whether L2 inval is
required
> + beq omap3_do_wfi
> +
> +clean_l2:
> + /*
> + * jump out to kernel flush routine
> + * - reuse that code is better
> + * - it executes in a cached space so is faster than refetch per-
> block
> + * - should be faster and will change with kernel
> + * - 'might' have to copy address, load and jump to it
> + */
> + ldr r1, kernel_flush
> + mov lr, pc
> + bx r1
> +
> +omap3_do_wfi:
> + ldr r4, sdrc_power @ read the SDRC_POWER register
> + ldr r5, [r4] @ read the contents of SDRC_POWER
> + orr r5, r5, #0x40 @ enable self refresh on idle req
> + str r5, [r4] @ write back to SDRC_POWER
register
> +
> /* Data memory barrier and Data sync barrier */
> mov r1, #0
> mcr p15, 0, r1, c7, c10, 4
> mcr p15, 0, r1, c7, c10, 5
>
> +/*
> + * ===================================
> + * == WFI instruction => Enter idle ==
> + * ===================================
> + */
> wfi @ wait for interrupt
>
> +/*
> + * ===================================
> + * == Resume path for non-OFF modes ==
> + * ===================================
> + */
> nop
> nop
> nop
> @@ -183,7 +310,29 @@ ENTRY(omap34xx_cpu_suspend)
> nop
> bl wait_sdrc_ok
>
> - ldmfd sp!, {r0-r12, pc} @ restore regs and return
> +/*
> + * ===================================
> + * == Exit point from non-OFF modes ==
> + * ===================================
> + */
> + ldmfd sp!, {r0-r12, pc} @ restore regs and return
> +
> +
> +/*
> + * ==============================
> + * == Resume path for OFF mode ==
> + * ==============================
> + */
> +
> +/*
> + * The restore_* functions are called by the ROM code
> + * when back from WFI in OFF mode.
> + * Cf. the get_*restore_pointer functions.
> + *
> + * restore_es3: applies to 34xx >= ES3.0
> + * restore_3630: applies to 36xx
> + * restore: common code for 3xxx
> + */
> restore_es3:
> ldr r5, pm_prepwstst_core_p
> ldr r4, [r5]
> @@ -213,12 +362,17 @@ restore_3630:
> ldr r1, control_mem_rta
> mov r2, #OMAP36XX_RTA_DISABLE
> str r2, [r1]
> - /* Fall thru for the remaining logic */
> +
> + /* Fall thru to common code for the remaining logic */
> +
> restore:
> - /* Check what was the reason for mpu reset and store the reason
> in r9*/
> - /* 1 - Only L1 and logic lost */
> - /* 2 - Only L2 lost - In this case, we wont be here */
> - /* 3 - Both L1 and L2 lost */
> + /*
> + * Check what was the reason for mpu reset and store the reason in
> r9:
> + * 0 - No context lost
> + * 1 - Only L1 and logic lost
> + * 2 - Only L2 lost - In this case, we wont be here
> + * 3 - Both L1 and L2 lost
> + */
> ldr r1, pm_pwstctrl_mpu
> ldr r2, [r1]
> and r2, r2, #0x3
> @@ -421,118 +575,12 @@ usettbr0:
> and r4, r2
> mcr p15, 0, r4, c1, c0, 0
>
> +/*
> + * ==============================
> + * == Exit point from OFF mode ==
> + * ==============================
> + */
> ldmfd sp!, {r0-r12, pc} @ restore regs and return
> -save_context_wfi:
> - mov r8, r0 /* Store SDRAM address in r8 */
> - mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
> - mov r4, #0x1 @ Number of parameters for restore
call
> - stmia r8!, {r4-r5} @ Push parameters for restore call
> - mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
> - stmia r8!, {r4-r5} @ Push parameters for restore call
> - /* Check what that target sleep state is:stored in r1*/
> - /* 1 - Only L1 and logic lost */
> - /* 2 - Only L2 lost */
> - /* 3 - Both L1 and L2 lost */
> - cmp r1, #0x2 /* Only L2 lost */
> - beq clean_l2
> - cmp r1, #0x1 /* L2 retained */
> - /* r9 stores whether to clean L2 or not*/
> - moveq r9, #0x0 /* Dont Clean L2 */
> - movne r9, #0x1 /* Clean L2 */
> -l1_logic_lost:
> - /* Store sp and spsr to SDRAM */
> - mov r4, sp
> - mrs r5, spsr
> - mov r6, lr
> - stmia r8!, {r4-r6}
> - /* Save all ARM registers */
> - /* Coprocessor access control register */
> - mrc p15, 0, r6, c1, c0, 2
> - stmia r8!, {r6}
> - /* TTBR0, TTBR1 and Translation table base control */
> - mrc p15, 0, r4, c2, c0, 0
> - mrc p15, 0, r5, c2, c0, 1
> - mrc p15, 0, r6, c2, c0, 2
> - stmia r8!, {r4-r6}
> - /* Domain access control register, data fault status register,
> - and instruction fault status register */
> - mrc p15, 0, r4, c3, c0, 0
> - mrc p15, 0, r5, c5, c0, 0
> - mrc p15, 0, r6, c5, c0, 1
> - stmia r8!, {r4-r6}
> - /* Data aux fault status register, instruction aux fault status,
> - datat fault address register and instruction fault address
> register*/
> - mrc p15, 0, r4, c5, c1, 0
> - mrc p15, 0, r5, c5, c1, 1
> - mrc p15, 0, r6, c6, c0, 0
> - mrc p15, 0, r7, c6, c0, 2
> - stmia r8!, {r4-r7}
> - /* user r/w thread and process ID, user r/o thread and process ID,
> - priv only thread and process ID, cache size selection */
> - mrc p15, 0, r4, c13, c0, 2
> - mrc p15, 0, r5, c13, c0, 3
> - mrc p15, 0, r6, c13, c0, 4
> - mrc p15, 2, r7, c0, c0, 0
> - stmia r8!, {r4-r7}
> - /* Data TLB lockdown, instruction TLB lockdown registers */
> - mrc p15, 0, r5, c10, c0, 0
> - mrc p15, 0, r6, c10, c0, 1
> - stmia r8!, {r5-r6}
> - /* Secure or non secure vector base address, FCSE PID, Context
PID*/
> - mrc p15, 0, r4, c12, c0, 0
> - mrc p15, 0, r5, c13, c0, 0
> - mrc p15, 0, r6, c13, c0, 1
> - stmia r8!, {r4-r6}
> - /* Primary remap, normal remap registers */
> - mrc p15, 0, r4, c10, c2, 0
> - mrc p15, 0, r5, c10, c2, 1
> - stmia r8!,{r4-r5}
> -
> - /* Store current cpsr*/
> - mrs r2, cpsr
> - stmia r8!, {r2}
> -
> - mrc p15, 0, r4, c1, c0, 0
> - /* save control register */
> - stmia r8!, {r4}
> -clean_caches:
> - /* Clean Data or unified cache to POU*/
> - /* How to invalidate only L1 cache???? - #FIX_ME# */
> - /* mcr p15, 0, r11, c7, c11, 1 */
> - cmp r9, #1 /* Check whether L2 inval is required or not*/
> - bne skip_l2_inval
> -clean_l2:
> - /*
> - * Jump out to kernel flush routine
> - * - reuse that code is better
> - * - it executes in a cached space so is faster than refetch per-
> block
> - * - should be faster and will change with kernel
> - * - 'might' have to copy address, load and jump to it
> - */
> - ldr r1, kernel_flush
> - mov lr, pc
> - bx r1
> -
> -skip_l2_inval:
> - /* Data memory barrier and Data sync barrier */
> - mov r1, #0
> - mcr p15, 0, r1, c7, c10, 4
> - mcr p15, 0, r1, c7, c10, 5
> -
> - wfi @ wait for interrupt
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - nop
> - bl wait_sdrc_ok
> - /* restore regs and return */
> - ldmfd sp!, {r0-r12, pc}
>
>
> /*
> @@ -682,5 +730,6 @@ kick_counter:
> .word 0
> wait_dll_lock_counter:
> .word 0
> +
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 18+ messages in thread* [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
2010-12-17 5:04 ` Santosh Shilimkar
@ 2010-12-17 10:14 ` Jean Pihet
0 siblings, 0 replies; 18+ messages in thread
From: Jean Pihet @ 2010-12-17 10:14 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Dec 17, 2010 at 6:04 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
>> owner at vger.kernel.org] On Behalf Of jean.pihet at newoldbits.com
>> Sent: Thursday, December 16, 2010 11:21 PM
>> To: linux-omap at vger.kernel.org
>> Cc: khilman at deeprootsystems.com; linux-arm-kernel at lists.infradead.org;
>> Jean Pihet
>> Subject: [PATCH 5/7] OMAP3: rework of the ASM sleep code execution paths
>>
>> From: Jean Pihet <j-pihet@ti.com>
>>
>> - Reworked and simplified the execution paths for better
>> ? readability and to avoid duplication of code,
>> - Added comments on the entry and exit points and the interaction
>> ? with the ROM code for OFF mode restore,
>> - Reworked the existing comments for better readability.
>>
>> Tested on N900 and Beagleboard with full RET and OFF modes,
>> using cpuidle and suspend.
>>
>> Signed-off-by: Jean Pihet <j-pihet@ti.com>
>> ---
>> ?arch/arm/mach-omap2/control.c ? | ? 10 +-
>> ?arch/arm/mach-omap2/sleep34xx.S | ?309
> ++++++++++++++++++++++------------
>> ----
>> ?2 files changed, 188 insertions(+), 131 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/control.c
> b/arch/arm/mach-omap2/control.c
>> index 728f268..5cb7276 100644
>> --- a/arch/arm/mach-omap2/control.c
>> +++ b/arch/arm/mach-omap2/control.c
>> @@ -239,7 +239,15 @@ void omap3_save_scratchpad_contents(void)
>> ? ? ? struct omap3_scratchpad_prcm_block prcm_block_contents;
>> ? ? ? struct omap3_scratchpad_sdrc_block sdrc_block_contents;
>>
>> - ? ? /* Populate the Scratchpad contents */
>> + ? ? /*
>> + ? ? ?* Populate the Scratchpad contents
>> + ? ? ?*
>> + ? ? ?* The get_*restore_pointer functions are used to get the resume
>> + ? ? ?* ?function pointer to be called by the ROM code when back from
> WFI
>> + ? ? ?* ?in OFF mode.
> Align your text here.
>> + ? ? ?* The restore pointer is stored into the scratchpad for later
>> access
>> + ? ? ?* ?by the ROM code.
> The text needs to be reworked a bit.
>
> The "get_*restore_pointer" functions are used to provide a physical
> restore
> address where ROM code jumps while waking up from MPU OFF/OSWR state.
> The restore pointer is stored into the scratchpad
That sounds better. Fixed.
>
>> + ? ? ?*/
>> ? ? ? scratchpad_contents.boot_config_ptr = 0x0;
>> ? ? ? if (cpu_is_omap3630())
>> ? ? ? ? ? ? ? scratchpad_contents.public_restore_ptr =
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
>> omap2/sleep34xx.S
>> index 426af02..55ddd5a 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -70,6 +70,11 @@
>> ? * API functions
>> ? */
>>
>> +/*
>> + * The get_*restore_pointer functions are returning the resume
>> + * ?function pointer to be called by the ROM code when back from WFI
>> + * ?in OFF mode.
> Ditto
> The "get_*restore_pointer" functions are used to provide a physical
> restore
> address where ROM code jumps while waking up from MPU OFF/OSWR state.
> The restore pointer is stored into the scratchpad
Idem
>
>> + */
>> ? ? ? .text
>> ?/* Function call to get the restore pointer for resume from OFF */
>> ?ENTRY(get_restore_pointer)
>> @@ -101,7 +106,7 @@ ENTRY(get_es3_restore_pointer_sz)
>> ?/*
>> ? * L2 cache needs to be toggled for stable OFF mode functionality on
> 3630.
>> ? * This function sets up a flag that will allow for this toggling to
> take
>> - * place on 3630. Hopefully some version in the future maynot need this
>> + * place on 3630. Hopefully some version in the future maynot need
> this.
> 'maynot' ..... may not
Fixed
>> ? */
>> ?ENTRY(enable_omap3630_toggle_l2_on_restore)
>> ? ? ? ? ?stmfd ? sp!, {lr} ? ? @ save registers on stack
>> @@ -143,34 +148,156 @@ ENTRY(save_secure_ram_context_sz)
>> ? ? ? .word ? . - save_secure_ram_context
>>
>> ?/*
>> + * ======================
>> + * == Idle entry point ==
>> + * ======================
>> + */
>> +
>> +/*
>> ? * Forces OMAP into idle state
>> ? *
>> - * omap34xx_suspend() - This bit of code just executes the WFI
>> - * for normal idles.
>> + * omap34xx_suspend() - This bit of code saves the CPU context if
> needed
>> + * and executes the WFI instruction
>> ? *
>> - * Note: This code get's copied to internal SRAM at boot. When the OMAP
>> - * ? ?wakes up it continues execution at the point it went to sleep.
>> + * Notes:
>> + * - this code gets copied to internal SRAM at boot.
>> + * - when the OMAP wakes up it continues at different execution points
>> + * ? depending on the low power mode (non-OFF vs OFF modes),
>> + * ? cf. 'Resume path for xxx mode' comments.
>> ? */
>> ?ENTRY(omap34xx_cpu_suspend)
>> ? ? ? stmfd ? sp!, {r0-r12, lr} ? ? ? ? ? ? ? @ save registers on stack
>>
>> - ? ? /* r0 contains restore pointer in sdram */
>> - ? ? /* r1 contains information about saving context */
>> - ? ? ldr ? ? r4, sdrc_power ? ? ? ? ?@ read the SDRC_POWER register
>> - ? ? ldr ? ? r5, [r4] ? ? ? ? ? ? ? ?@ read the contents of SDRC_POWER
>> - ? ? orr ? ? r5, r5, #0x40 ? ? ? ? ? @ enable self refresh on idle req
>> - ? ? str ? ? r5, [r4] ? ? ? ? ? ? ? ?@ write back to SDRC_POWER
> register
>> + ? ? /*
>> + ? ? ?* r0 contains restore pointer in sdram
>> + ? ? ?* r1 contains information about saving context:
>> + ? ? ?* ? 0 - No context lost
>> + ? ? ?* ? 1 - Only L1 and logic lost
>> + ? ? ?* ? 2 - Only L2 lost
>> + ? ? ?* ? 3 - Both L1 and L2 lost
>> + ? ? ?*/
>>
>> + ? ? /* Save context only if required */
>> ? ? ? cmp ? ? r1, #0x0
>> - ? ? /* If context save is required, do that and execute wfi */
>> - ? ? bne ? ? save_context_wfi
>> + ? ? beq ? ? omap3_do_wfi
>> +
>> +save_context_wfi:
>> + ? ? mov ? ? r8, r0 ? ? ? ? ? ? ? ? ?@ Store SDRAM address in r8
>> + ? ? mrc ? ? p15, 0, r5, c1, c0, 1 ? @ Read Auxiliary Control Register
>> + ? ? mov ? ? r4, #0x1 ? ? ? ? ? ? ? ?@ Number of parameters for restore
> call
>> + ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> + ? ? mrc ? ? p15, 1, r5, c9, c0, 2 ? @ Read L2 AUX ctrl register
>> + ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> +
>> + ? ? ? ?/* Check what that target sleep state is from r1 */
>> + ? ? cmp ? ? r1, #0x2 ? ? ? ? ? ? ? ?@ Only L2 lost, no need to save
> context
>> + ? ? beq ? ? clean_caches
>> +
>> +l1_logic_lost:
>> + ? ? /* Store sp and spsr to SDRAM */
>> + ? ? mov ? ? r4, sp
>> + ? ? mrs ? ? r5, spsr
>> + ? ? mov ? ? r6, lr
>> + ? ? stmia ? r8!, {r4-r6}
>> + ? ? /* Save all ARM registers */
>> + ? ? /* Coprocessor access control register */
> You might want to fix above commenting style as well
>> + ? ? mrc ? ? p15, 0, r6, c1, c0, 2
>> + ? ? stmia ? r8!, {r6}
>> + ? ? /* TTBR0, TTBR1 and Translation table base control */
>> + ? ? mrc ? ? p15, 0, r4, c2, c0, 0
>> + ? ? mrc ? ? p15, 0, r5, c2, c0, 1
>> + ? ? mrc ? ? p15, 0, r6, c2, c0, 2
>> + ? ? stmia ? r8!, {r4-r6}
>> + ? ? /*
>> + ? ? ?* Domain access control register, data fault status register,
>> + ? ? ?* and instruction fault status register
>> + ? ? ?*/
>> + ? ? mrc ? ? p15, 0, r4, c3, c0, 0
>> + ? ? mrc ? ? p15, 0, r5, c5, c0, 0
>> + ? ? mrc ? ? p15, 0, r6, c5, c0, 1
>> + ? ? stmia ? r8!, {r4-r6}
>> + ? ? /*
>> + ? ? ?* Data aux fault status register, instruction aux fault status,
>> + ? ? ?* data fault address register and instruction fault address
>> register
>> + ? ? ?*/
>> + ? ? mrc ? ? p15, 0, r4, c5, c1, 0
>> + ? ? mrc ? ? p15, 0, r5, c5, c1, 1
>> + ? ? mrc ? ? p15, 0, r6, c6, c0, 0
>> + ? ? mrc ? ? p15, 0, r7, c6, c0, 2
>> + ? ? stmia ? r8!, {r4-r7}
>> + ? ? /*
>> + ? ? ?* user r/w thread and process ID, user r/o thread and process ID,
>> + ? ? ?* priv only thread and process ID, cache size selection
>> + ? ? ?*/
>> + ? ? mrc ? ? p15, 0, r4, c13, c0, 2
>> + ? ? mrc ? ? p15, 0, r5, c13, c0, 3
>> + ? ? mrc ? ? p15, 0, r6, c13, c0, 4
>> + ? ? mrc ? ? p15, 2, r7, c0, c0, 0
>> + ? ? stmia ? r8!, {r4-r7}
>> + ? ? /* Data TLB lockdown, instruction TLB lockdown registers */
>> + ? ? mrc ? ? p15, 0, r5, c10, c0, 0
>> + ? ? mrc ? ? p15, 0, r6, c10, c0, 1
>> + ? ? stmia ? r8!, {r5-r6}
>> + ? ? /* Secure or non secure vector base address, FCSE PID, Context
> PID*/
>> + ? ? mrc ? ? p15, 0, r4, c12, c0, 0
>> + ? ? mrc ? ? p15, 0, r5, c13, c0, 0
>> + ? ? mrc ? ? p15, 0, r6, c13, c0, 1
>> + ? ? stmia ? r8!, {r4-r6}
>> + ? ? /* Primary remap, normal remap registers */
>> + ? ? mrc ? ? p15, 0, r4, c10, c2, 0
>> + ? ? mrc ? ? p15, 0, r5, c10, c2, 1
>> + ? ? stmia ? r8!,{r4-r5}
>> +
>> + ? ? /* Store current cpsr*/
>> + ? ? mrs ? ? r2, cpsr
>> + ? ? stmia ? r8!, {r2}
>> +
>> + ? ? mrc ? ? p15, 0, r4, c1, c0, 0
>> + ? ? /* save control register */
>> + ? ? stmia ? r8!, {r4}
>> +
>> +clean_caches:
>> + ? ? /* Clean Data or unified cache to POU*/
>> + ? ? /* How to invalidate only L1 cache???? - #FIX_ME# */
>> + ? ? /* mcr ?p15, 0, r11, c7, c11, 1 */
> And this one too...
>> + ? ? cmp ? ? r1, #0x1 ? ? ? ? ? ? ? ?@ Check whether L2 inval is
> required
>> + ? ? beq ? ? omap3_do_wfi
>> +
>> +clean_l2:
>> + ? ? /*
>> + ? ? ?* jump out to kernel flush routine
>> + ? ? ?* ?- reuse that code is better
>> + ? ? ?* ?- it executes in a cached space so is faster than refetch per-
>> block
>> + ? ? ?* ?- should be faster and will change with kernel
>> + ? ? ?* ?- 'might' have to copy address, load and jump to it
>> + ? ? ?*/
>> + ? ? ldr r1, kernel_flush
>> + ? ? mov lr, pc
>> + ? ? bx ?r1
>> +
>> +omap3_do_wfi:
>> + ? ? ldr ? ? r4, sdrc_power ? ? ? ? ?@ read the SDRC_POWER register
>> + ? ? ldr ? ? r5, [r4] ? ? ? ? ? ? ? ?@ read the contents of SDRC_POWER
>> + ? ? orr ? ? r5, r5, #0x40 ? ? ? ? ? @ enable self refresh on idle req
>> + ? ? str ? ? r5, [r4] ? ? ? ? ? ? ? ?@ write back to SDRC_POWER
> register
>> +
>> ? ? ? /* Data memory barrier and Data sync barrier */
>> ? ? ? mov ? ? r1, #0
>> ? ? ? mcr ? ? p15, 0, r1, c7, c10, 4
>> ? ? ? mcr ? ? p15, 0, r1, c7, c10, 5
>>
>> +/*
>> + * ===================================
>> + * == WFI instruction => Enter idle ==
>> + * ===================================
>> + */
>> ? ? ? wfi ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ wait for interrupt
>>
>> +/*
>> + * ===================================
>> + * == Resume path for non-OFF modes ==
>> + * ===================================
>> + */
>> ? ? ? nop
>> ? ? ? nop
>> ? ? ? nop
>> @@ -183,7 +310,29 @@ ENTRY(omap34xx_cpu_suspend)
>> ? ? ? nop
>> ? ? ? bl wait_sdrc_ok
>>
>> - ? ? ldmfd ? sp!, {r0-r12, pc} ? ? ? ? ? ? ? @ restore regs and return
>> +/*
>> + * ===================================
>> + * == Exit point from non-OFF modes ==
>> + * ===================================
>> + */
>> + ? ? ldmfd ? sp!, {r0-r12, pc} ? ? ? @ restore regs and return
>> +
>> +
>> +/*
>> + * ==============================
>> + * == Resume path for OFF mode ==
>> + * ==============================
>> + */
>> +
>> +/*
>> + * The restore_* functions are called by the ROM code
>> + * ?when back from WFI in OFF mode.
>> + * Cf. the get_*restore_pointer functions.
>> + *
>> + * ?restore_es3: applies to 34xx >= ES3.0
>> + * ?restore_3630: applies to 36xx
>> + * ?restore: common code for 3xxx
>> + */
>> ?restore_es3:
>> ? ? ? ldr ? ? r5, pm_prepwstst_core_p
>> ? ? ? ldr ? ? r4, [r5]
>> @@ -213,12 +362,17 @@ restore_3630:
>> ? ? ? ldr ? ? r1, control_mem_rta
>> ? ? ? mov ? ? r2, #OMAP36XX_RTA_DISABLE
>> ? ? ? str ? ? r2, [r1]
>> - ? ? /* Fall thru for the remaining logic */
>> +
>> + ? ? /* Fall thru to common code for the remaining logic */
>> +
>> ?restore:
>> - ? ? ? ?/* Check what was the reason for mpu reset and store the reason
>> in r9*/
>> - ? ? ? ?/* 1 - Only L1 and logic lost */
>> - ? ? ? ?/* 2 - Only L2 lost - In this case, we wont be here */
>> - ? ? ? ?/* 3 - Both L1 and L2 lost */
>> + ? ? ? ?/*
>> + ? ? ?* Check what was the reason for mpu reset and store the reason in
>> r9:
>> + ? ? ?* ?0 - No context lost
>> + ? ? ? ? * ?1 - Only L1 and logic lost
>> + ? ? ? ? * ?2 - Only L2 lost - In this case, we wont be here
>> + ? ? ? ? * ?3 - Both L1 and L2 lost
>> + ? ? ?*/
>> ? ? ? ldr ? ? r1, pm_pwstctrl_mpu
>> ? ? ? ldr ? ? r2, [r1]
>> ? ? ? and ? ? r2, r2, #0x3
>> @@ -421,118 +575,12 @@ usettbr0:
>> ? ? ? and ? ? r4, r2
>> ? ? ? mcr ? ? p15, 0, r4, c1, c0, 0
>>
>> +/*
>> + * ==============================
>> + * == Exit point from OFF mode ==
>> + * ==============================
>> + */
>> ? ? ? ldmfd ? sp!, {r0-r12, pc} ? ? ? ? ? ? ? @ restore regs and return
>> -save_context_wfi:
>> - ? ? mov ? ? r8, r0 /* Store SDRAM address in r8 */
>> - ? ? mrc ? ? p15, 0, r5, c1, c0, 1 ? @ Read Auxiliary Control Register
>> - ? ? mov ? ? r4, #0x1 ? ? ? ? ? ? ? ?@ Number of parameters for restore
> call
>> - ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> - ? ? mrc ? ? p15, 1, r5, c9, c0, 2 ? @ Read L2 AUX ctrl register
>> - ? ? stmia ? r8!, {r4-r5} ? ? ? ? ? ?@ Push parameters for restore call
>> - ? ? ? ?/* Check what that target sleep state is:stored in r1*/
>> - ? ? ? ?/* 1 - Only L1 and logic lost */
>> - ? ? ? ?/* 2 - Only L2 lost */
>> - ? ? ? ?/* 3 - Both L1 and L2 lost */
>> - ? ? cmp ? ? r1, #0x2 /* Only L2 lost */
>> - ? ? beq ? ? clean_l2
>> - ? ? cmp ? ? r1, #0x1 /* L2 retained */
>> - ? ? /* r9 stores whether to clean L2 or not*/
>> - ? ? moveq ? r9, #0x0 /* Dont Clean L2 */
>> - ? ? movne ? r9, #0x1 /* Clean L2 */
>> -l1_logic_lost:
>> - ? ? /* Store sp and spsr to SDRAM */
>> - ? ? mov ? ? r4, sp
>> - ? ? mrs ? ? r5, spsr
>> - ? ? mov ? ? r6, lr
>> - ? ? stmia ? r8!, {r4-r6}
>> - ? ? /* Save all ARM registers */
>> - ? ? /* Coprocessor access control register */
>> - ? ? mrc ? ? p15, 0, r6, c1, c0, 2
>> - ? ? stmia ? r8!, {r6}
>> - ? ? /* TTBR0, TTBR1 and Translation table base control */
>> - ? ? mrc ? ? p15, 0, r4, c2, c0, 0
>> - ? ? mrc ? ? p15, 0, r5, c2, c0, 1
>> - ? ? mrc ? ? p15, 0, r6, c2, c0, 2
>> - ? ? stmia ? r8!, {r4-r6}
>> - ? ? /* Domain access control register, data fault status register,
>> - ? ? and instruction fault status register */
>> - ? ? mrc ? ? p15, 0, r4, c3, c0, 0
>> - ? ? mrc ? ? p15, 0, r5, c5, c0, 0
>> - ? ? mrc ? ? p15, 0, r6, c5, c0, 1
>> - ? ? stmia ? r8!, {r4-r6}
>> - ? ? /* Data aux fault status register, instruction aux fault status,
>> - ? ? datat fault address register and instruction fault address
>> register*/
>> - ? ? mrc ? ? p15, 0, r4, c5, c1, 0
>> - ? ? mrc ? ? p15, 0, r5, c5, c1, 1
>> - ? ? mrc ? ? p15, 0, r6, c6, c0, 0
>> - ? ? mrc ? ? p15, 0, r7, c6, c0, 2
>> - ? ? stmia ? r8!, {r4-r7}
>> - ? ? /* user r/w thread and process ID, user r/o thread and process ID,
>> - ? ? priv only thread and process ID, cache size selection */
>> - ? ? mrc ? ? p15, 0, r4, c13, c0, 2
>> - ? ? mrc ? ? p15, 0, r5, c13, c0, 3
>> - ? ? mrc ? ? p15, 0, r6, c13, c0, 4
>> - ? ? mrc ? ? p15, 2, r7, c0, c0, 0
>> - ? ? stmia ? r8!, {r4-r7}
>> - ? ? /* Data TLB lockdown, instruction TLB lockdown registers */
>> - ? ? mrc ? ? p15, 0, r5, c10, c0, 0
>> - ? ? mrc ? ? p15, 0, r6, c10, c0, 1
>> - ? ? stmia ? r8!, {r5-r6}
>> - ? ? /* Secure or non secure vector base address, FCSE PID, Context
> PID*/
>> - ? ? mrc ? ? p15, 0, r4, c12, c0, 0
>> - ? ? mrc ? ? p15, 0, r5, c13, c0, 0
>> - ? ? mrc ? ? p15, 0, r6, c13, c0, 1
>> - ? ? stmia ? r8!, {r4-r6}
>> - ? ? /* Primary remap, normal remap registers */
>> - ? ? mrc ? ? p15, 0, r4, c10, c2, 0
>> - ? ? mrc ? ? p15, 0, r5, c10, c2, 1
>> - ? ? stmia ? r8!,{r4-r5}
>> -
>> - ? ? /* Store current cpsr*/
>> - ? ? mrs ? ? r2, cpsr
>> - ? ? stmia ? r8!, {r2}
>> -
>> - ? ? mrc ? ? p15, 0, r4, c1, c0, 0
>> - ? ? /* save control register */
>> - ? ? stmia ? r8!, {r4}
>> -clean_caches:
>> - ? ? /* Clean Data or unified cache to POU*/
>> - ? ? /* How to invalidate only L1 cache???? - #FIX_ME# */
>> - ? ? /* mcr ?p15, 0, r11, c7, c11, 1 */
>> - ? ? cmp ? ? r9, #1 /* Check whether L2 inval is required or not*/
>> - ? ? bne ? ? skip_l2_inval
>> -clean_l2:
>> - ? ? /*
>> - ? ? ?* Jump out to kernel flush routine
>> - ? ? ?* ?- reuse that code is better
>> - ? ? ?* ?- it executes in a cached space so is faster than refetch per-
>> block
>> - ? ? ?* ?- should be faster and will change with kernel
>> - ? ? ?* ?- 'might' have to copy address, load and jump to it
>> - ? ? ?*/
>> - ? ? ldr r1, kernel_flush
>> - ? ? mov lr, pc
>> - ? ? bx ?r1
>> -
>> -skip_l2_inval:
>> - ? ? /* Data memory barrier and Data sync barrier */
>> - ? ? mov ? ? r1, #0
>> - ? ? mcr ? ? p15, 0, r1, c7, c10, 4
>> - ? ? mcr ? ? p15, 0, r1, c7, c10, 5
>> -
>> - ? ? wfi ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ wait for interrupt
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? nop
>> - ? ? bl wait_sdrc_ok
>> - ? ? /* restore regs and return */
>> - ? ? ldmfd ? sp!, {r0-r12, pc}
>>
>>
>> ?/*
>> @@ -682,5 +730,6 @@ kick_counter:
>> ? ? ? .word ? 0
>> ?wait_dll_lock_counter:
>> ? ? ? .word ? 0
>> +
>> ?ENTRY(omap34xx_cpu_suspend_sz)
>> ? ? ? .word ? . - omap34xx_cpu_suspend
>> --
>> 1.7.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
Jean
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