From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: Improve the L2 cache performance when PL310 is used
Date: Tue, 15 Feb 2011 16:43:40 +0000 [thread overview]
Message-ID: <1297788220.28844.3.camel@e102109-lin.cambridge.arm.com> (raw)
In-Reply-To: <AANLkTi=zUei0tNVObW18+bRd0f7oLSEoDMFTd+3=7JSZ@mail.gmail.com>
On Tue, 2011-02-15 at 11:29 +0000, Srinidhi Kasagar wrote:
> Just curious to know, why the spinlock surrounding
> l2x0_cache_sync still exists? I see that
> Catalin's first version adds void lock for PL310
> as they are atomic.
On PL310, range operations and the cache sync don't need the spinlock.
However, TI pushed optimisations to use "all" operations for large
ranges. These operations are background and you need to use a cache sync
until completed. You also need locks around since starting other
operations while a background one is active is unpredictable.
--
Catalin
prev parent reply other threads:[~2011-02-15 16:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-09 10:14 [PATCH] ARM: Improve the L2 cache performance when PL310 is used Catalin Marinas
2010-03-09 10:30 ` Colin Tuckley
2010-03-09 10:52 ` Catalin Marinas
2010-03-09 11:07 ` Colin Tuckley
2010-03-09 11:28 ` Shilimkar, Santosh
2010-03-13 13:34 ` Shilimkar, Santosh
2011-02-15 11:29 ` Srinidhi Kasagar
2011-02-15 16:43 ` Catalin Marinas [this message]
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