[PATCH 0/3] Tegra 640x480 HDMI audio patches

[PATCH 0/3] Tegra 640x480 HDMI audio patches

[Stephen Warren]

This patch set fixes 640x480 HDMI video clocking, audio over HDMI at 640x80,
and especially 44.1KHz audio at that resolution.

It was generated against linux-tegra-2.6.37, but probably is worth applying
to, or merging into, all of:

for-next
android-tegra-2.6.37
linux-tegra-2.6.37
android-tegra-2.6.36
linux-tegra-2.6.36

Stephen Warren (3):
  ARM: Tegra: Add pll_d table entries for 252MHz
  video: tegra: Fix CTS/N table for 25.2MHz pclk, 44.1Hz audio
  video: tegra: Run pll_d at 252mhz for HDMI 640x480

 arch/arm/mach-tegra/tegra2_clocks.c |    5 +++++
 drivers/video/tegra/dc/dc.c         |    4 +++-
 drivers/video/tegra/dc/hdmi.c       |    2 +-
 3 files changed, 9 insertions(+), 2 deletions(-)

[PATCH 1/3] ARM: Tegra: Add pll_d table entries for 252MHz

[Stephen Warren]

This rate is required for correct generation of 640x480 HDMI video;
see subsequent patches.

Note: I tested the entry with 12MHz input. The other entries are untested,
but appear logically correct. However, I'm not familiar enough with PLLs
to know if they perhaps exceed the PLL VCO frequency, nor whether the
cpcon values are strictly correct.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 arch/arm/mach-tegra/tegra2_clocks.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 41f5953..f3ead19 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1531,6 +1531,11 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
 	{ 19200000, 216000000, 135, 12, 1, 3},
 	{ 26000000, 216000000, 216, 26, 1, 4},
 
+	{ 12000000, 252000000, 252, 12, 1, 4},
+	{ 13000000, 252000000, 252, 13, 1, 4},
+	{ 19200000, 252000000, 210, 16, 1, 3},
+	{ 26000000, 252000000, 252, 26, 1, 4},
+
 	{ 12000000, 594000000, 594, 12, 1, 8},
 	{ 13000000, 594000000, 594, 13, 1, 8},
 	{ 19200000, 594000000, 495, 16, 1, 8},
-- 
1.7.1

[PATCH 2/3] video: tegra: Fix CTS/N table for 25.2MHz pclk, 44.1Hz audio

[Stephen Warren]

The existing values are for a 25.25MHz clock, not a 25.20MHz clock:

25250000 * 14112 / (128 * 63125) == 44100.000
25200000 * 5656  / (128 * 25250) == 44100.000

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 drivers/video/tegra/dc/hdmi.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c
index 878cca5..9210737 100644
--- a/drivers/video/tegra/dc/hdmi.c
+++ b/drivers/video/tegra/dc/hdmi.c
@@ -152,7 +152,7 @@ const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
 };
 
 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
-	{25200000,	14112,	63125},
+	{25200000,	5656,	25250},
 	{27000000,	6272,	30000},
 	{54000000,	6272,	60000},
 	{74250000,	6272,	82500},
-- 
1.7.1

[PATCH 3/3] video: tegra: Run pll_d at 252mhz for HDMI 640x480

[Stephen Warren]

Using a pll_d clock rate of 216MHz yields a 24MHz pixel clock instead of
25.2MHz. This is just under a 5% error. Instead, use a 252MHz pll_d rate,
which generates 25.2MHz exactly.

This makes it more likely that monitors will sync to the emitted signal.

This also fixes HDMI audio issues, since the CTS/N tables are now based
on the actual pixel clock rate, not merely the intended pixel clock rate.

Tested with a 12MHz pll_m rate on Seaboard, all of 32/44.1/48KHz audio,
all video modes supported by the Tegra dc HDMI driver, and a Dell U2410
dislay.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 drivers/video/tegra/dc/dc.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 16789c2..c1eea05 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -699,8 +699,10 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
 
 		if (dc->mode.pclk > 70000000)
 			rate = 594000000;
-		else
+		else if (dc->mode.pclk >= 27000000)
 			rate = 216000000;
+		else
+			rate = 252000000;
 
 		if (rate != clk_get_rate(pll_d_clk))
 			clk_set_rate(pll_d_clk, rate);
-- 
1.7.1

[PATCH 1/3] ARM: Tegra: Add pll_d table entries for 252MHz

[Erik Gilling]

These look good.  Have you run these through a CTS tester at 720x480
and 1280x720?  We pass those now and I want to make sure there's not
regressions.  We're supposed to be getting one in a week or two.  If
you haven't run it by then, I'll run a pass with these then merge.

Cheers,
   Erik

On Fri, Feb 18, 2011 at 3:18 PM, Stephen Warren <swarren@nvidia.com> wrote:
> This rate is required for correct generation of 640x480 HDMI video;
> see subsequent patches.
>
> Note: I tested the entry with 12MHz input. The other entries are untested,
> but appear logically correct. However, I'm not familiar enough with PLLs
> to know if they perhaps exceed the PLL VCO frequency, nor whether the
> cpcon values are strictly correct.
>
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
> ?arch/arm/mach-tegra/tegra2_clocks.c | ? ?5 +++++
> ?1 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
> index 41f5953..f3ead19 100644
> --- a/arch/arm/mach-tegra/tegra2_clocks.c
> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
> @@ -1531,6 +1531,11 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
> ? ? ? ?{ 19200000, 216000000, 135, 12, 1, 3},
> ? ? ? ?{ 26000000, 216000000, 216, 26, 1, 4},
>
> + ? ? ? { 12000000, 252000000, 252, 12, 1, 4},
> + ? ? ? { 13000000, 252000000, 252, 13, 1, 4},
> + ? ? ? { 19200000, 252000000, 210, 16, 1, 3},
> + ? ? ? { 26000000, 252000000, 252, 26, 1, 4},
> +
> ? ? ? ?{ 12000000, 594000000, 594, 12, 1, 8},
> ? ? ? ?{ 13000000, 594000000, 594, 13, 1, 8},
> ? ? ? ?{ 19200000, 594000000, 495, 16, 1, 8},
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

[PATCH 1/3] ARM: Tegra: Add pll_d table entries for 252MHz

[Stephen Warren]

Erik Gilling wrote at Friday, February 18, 2011 4:46 PM:
>
> These look good.  Have you run these through a CTS tester at 720x480
> and 1280x720?  We pass those now and I want to make sure there's not
> regressions.  We're supposed to be getting one in a week or two.  If
> you haven't run it by then, I'll run a pass with these then merge.

Unfortunately, I don't have one available, so no.

(although I don't believe I made any changes to clocking, CTS, or N
for those two modes, just 640x480).

Thanks for the review and offer to test!

> 
> Cheers,
>    Erik
> 
> On Fri, Feb 18, 2011 at 3:18 PM, Stephen Warren <swarren@nvidia.com>
> wrote:
> > This rate is required for correct generation of 640x480 HDMI video;
> > see subsequent patches.
> >
> > Note: I tested the entry with 12MHz input. The other entries are untested,
> > but appear logically correct. However, I'm not familiar enough with PLLs
> > to know if they perhaps exceed the PLL VCO frequency, nor whether the
> > cpcon values are strictly correct.
> >
> > Signed-off-by: Stephen Warren <swarren@nvidia.com>
> > ---
> > ?arch/arm/mach-tegra/tegra2_clocks.c | ? ?5 +++++
> > ?1 files changed, 5 insertions(+), 0 deletions(-)

-- 
Nvpublic