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From: santosh.shilimkar@ti.com (Santosh Shilimkar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 6/6] omap3: pm: Use exported set_cr() instead of a custom one.
Date: Mon, 21 Feb 2011 18:49:25 +0530	[thread overview]
Message-ID: <1298294365-30770-7-git-send-email-santosh.shilimkar@ti.com> (raw)
In-Reply-To: <1298294365-30770-1-git-send-email-santosh.shilimkar@ti.com>

Remove the custom restore_control_register() and use the exported
set_cr() instead to set the system control register(SCTRL) value.

No functional change.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..63a3e1d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -311,11 +311,6 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
-static void restore_control_register(u32 val)
-{
-	__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
-}
-
 /* Function to restore the table entry that was modified for enabling MMU */
 static void restore_table_entry(void)
 {
@@ -337,7 +332,7 @@ static void restore_table_entry(void)
 	control_reg_value = __raw_readl(scratchpad_address
 					+ OMAP343X_CONTROL_REG_VALUE_OFFSET);
 	/* This will enable caches and prediction */
-	restore_control_register(control_reg_value);
+	set_cr(control_reg_value);
 }
 
 void omap_sram_idle(void)
-- 
1.6.0.4

  parent reply	other threads:[~2011-02-21 13:19 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-02-21 13:19 [PATCH 0/6] omap3: pm: Fixes for low power code Santosh Shilimkar
2011-02-21 13:19 ` [PATCH 1/6] omap3: pm: Use amrv7 supported instructions instead of legacy cp15 ones Santosh Shilimkar
2011-02-21 13:19 ` [PATCH 2/6] omap3: pm: Fix the mmu on sequence in the asm code Santosh Shilimkar
2011-02-21 13:19 ` [PATCH 3/6] omap3: pm: Allow the cache clean when L1 is lost Santosh Shilimkar
2011-02-21 13:19 ` [PATCH 4/6] omap3: pm: Remove un-necessary cp15 registers form low power cpu context Santosh Shilimkar
2011-02-21 13:19 ` [PATCH 5/6] omap3: pm: Clear the SCTLR C bit in asm code to prevent data cache allocation Santosh Shilimkar
2011-02-21 13:19 ` Santosh Shilimkar [this message]
2011-03-03  1:22 ` [PATCH 0/6] omap3: pm: Fixes for low power code Kevin Hilman
2011-03-04  6:54   ` Santosh Shilimkar
2011-03-08 11:41   ` Santosh Shilimkar

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