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Mai 2026, 23:09:15 Mitteleurop=C3=A4ische Sommerzeit sch= rieb Heiko Stuebner: > Do not put the reset control, retain exclusive control over it. > After turning on a CPU, the corresponding reset line must stay > deasserted. >=20 > This also avoids calling reset_control_put() before workqueues > are operational. >=20 > Fixes: 78ebbff6d1a0 ("reset: handle removing supplier before consumers") > Signed-off-by: Philipp Zabel > Tested-by: Steven Price > Signed-off-by: Heiko Stuebner =46orgot to add Bartosz to the Cc list, sorry Heiko > --- > arch/arm/mach-rockchip/platsmp.c | 16 ++++++++++------ > 1 file changed, 10 insertions(+), 6 deletions(-) >=20 > diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/pl= atsmp.c > index f432d22bfed8..f659d894bfae 100644 > --- a/arch/arm/mach-rockchip/platsmp.c > +++ b/arch/arm/mach-rockchip/platsmp.c > @@ -34,6 +34,7 @@ static int ncores; > =20 > static struct regmap *pmu; > static int has_pmu =3D true; > +static struct reset_control *cpu_rstc[4]; > =20 > static int pmu_power_domain_is_on(int pd) > { > @@ -64,9 +65,11 @@ static struct reset_control *rockchip_get_core_reset(i= nt cpu) > static int pmu_set_power_domain(int pd, bool on) > { > u32 val =3D (on) ? 0 : BIT(pd); > - struct reset_control *rstc =3D rockchip_get_core_reset(pd); > + struct reset_control *rstc; > int ret; > =20 > + rstc =3D pd < ARRAY_SIZE(cpu_rstc) ? cpu_rstc[pd] : ERR_PTR(-EINVAL); > + > if (IS_ERR(rstc) && read_cpuid_part() !=3D ARM_CPU_PART_CORTEX_A9) { > pr_err("%s: could not get reset control for core %d\n", > __func__, pd); > @@ -100,11 +103,8 @@ static int pmu_set_power_domain(int pd, bool on) > } > } > =20 > - if (!IS_ERR(rstc)) { > - if (on) > - reset_control_deassert(rstc); > - reset_control_put(rstc); > - } > + if (!IS_ERR(rstc) && on) > + reset_control_deassert(rstc); > =20 > return 0; > } > @@ -312,6 +312,10 @@ static void __init rockchip_smp_prepare_cpus(unsigne= d int max_cpus) > ncores =3D ((l2ctlr >> 24) & 0x3) + 1; > } > =20 > + /* Collect cpu core reset control for each core */ > + for (i =3D 0; i < ncores; i++) > + cpu_rstc[i] =3D rockchip_get_core_reset(i); > + > /* Make sure that all cores except the first are really off */ > for (i =3D 1; i < ncores; i++) > pmu_set_power_domain(0 + i, false); >=20